FPGA Design Flow and synthesis Techniques
- 1. For Academic Use Only Presentation Name 1 FPGA Design Flow
- 2. For Academic Use Only Presentation Name 2 Sintesi
- 3. For Academic Use Only Presentation Name 3 Translate
- 4. For Academic Use Only Presentation Name 4 Circuit netlist Netlist: A text description of the circuit connectivity. It is basically a list of connectors, a list of instances, and, for each instance, a list of the signals connected to the instance terminals. In addition, the netlist contains attribute information.
- 5. For Academic Use Only Presentation Name 5 Mapping
- 6. For Academic Use Only Presentation Name 6 Placing
- 7. For Academic Use Only Presentation Name 7 Routing
- 8. For Academic Use Only Presentation Name 8 Static timing analyzer
- 9. For Academic Use Only Presentation Name 9 Static timing analyzer
- 10. For Academic Use Only Presentation Name 10 Static timing analyzer
- 11. For Academic Use Only Presentation Name 11 Configuration
- 12. ISE Software Flow ! " # $ %
- 13. For Academic Use Only Presentation Name 13 Outline • & ' • # ' • & • • # (
- 14. For Academic Use Only Presentation Name 14 Foundation Series ISE • ! & & ' & ( ' ) • ! * $ + , $ - . . . / 0 1 2. • ! 3 / 4 * 5 &
- 15. For Academic Use Only Presentation Name 15 Translate Map Place & Route Xilinx Design Flow Plan & Budget HDL RTL Simulation Synthesize to create netlist Functional Simulation Create Bit File Attain Timing Closure Timing Simulation Implement Create Code/ Schematic
- 16. For Academic Use Only Presentation Name 16 Advanced design management through project navigator • 3 6 • • " ( 7 ' 7 & 7 7 & 7
- 17. For Academic Use Only Presentation Name 17 Processes and Tools & ( % Step 1:Design Step 2: Synthesize to create netlist Step 3: Implement design Step 4: Configuration
- 18. For Academic Use Only Presentation Name 18 Context Sensitive Flow ) 8 9 ! !
- 19. For Academic Use Only Presentation Name 19 ISE Push Button Flow • & :: • & : 2 1 " " # $ # $ % % 3
- 20. For Academic Use Only Presentation Name 20 Design Entry • 6 * # • 0 ( * 5 # 7 " $ ; ) • $ ) ( ' # ! 4 ! " 7 * & & ! " 4 & 0 • & ( % < & # # ' ! ! ( " ! ) ) )
- 21. For Academic Use Only Presentation Name 21 Schematic Source File • ( * = / ( & & • 4 3 • 5 # % ( • 3 > 7 0 / # ?
- 22. For Academic Use Only Presentation Name 22 Options and Symbols • ) • ' & • & / ! • 7 @ . + . A , . - B . 7 . + . A , . - B . • 0 ( 7 ! ( (
- 23. For Academic Use Only Presentation Name 23 HDL Source File • 0 5 # 7 ? 5 # 2) 7 ? 2) 7 " ' :5 # 2 • & (
- 24. For Academic Use Only Presentation Name 24 Xilinx CORE Generator System GUI Core type, version, device support, and vendor Cores can be organized by function, vendor, or device family
- 25. For Academic Use Only Presentation Name 25 Core Customize Window Parameters tab allows you to customize the core Contact tab provides information about the vendor Data sheet access Core Overview tab provides version information and a brief functional description
- 26. For Academic Use Only Presentation Name 26 • & ' ) * • & • & & C • ( : • ! " " ( • & ' ! ( • 4 & 0 4 & 0 5.1i Synthesis Solutions
- 27. For Academic Use Only Presentation Name 27 XST Flow To Implementation Tools Synthesis Report File Synthesis Technology Specific Optimization Supported Families: Virtex XC9500 Virtex-E XC9500XL Virtex-II XC9500XV Virtex-IIPro CoolRunner Spartan-II CoolRunner-II Spartan-IIE Constraints VHDL Verilog .LOG .NGC ISE 5.1i PC & WS
- 28. For Academic Use Only Presentation Name 28 Xilinx Implementation • • 0 ) 7 @ 7 0 7 ! 7 ! " ' 7 < Translate Map Place & Route Implement . . . . . .
- 29. For Academic Use Only Presentation Name 29 What is Implementation? • = 8 6 @ 9 • 7 7 7 • ' ( 4 ! ! " ' 4 ( : 6 @
- 30. For Academic Use Only Presentation Name 30 Implement • ' ) ( ) : : 7 0 D : 7 D ! D ( ! " ' 7 6 @ D & D ! ) ( D ! " ' ) ( D " ; (
- 31. For Academic Use Only Presentation Name 31 Download • ! " 7 0 * 0 2 • 0 0 ( ! " ) @ (
- 32. For Academic Use Only Presentation Name 32 Program the FPGA • 0 ( ( ! " 7 0 @ ) D E ( @ ( 7 # D 3 " 0