IBM III-V workshop 2010

Electrical properties of III-V/oxide
interfaces
G. Brammertz, H.C. Lin, A. Alian, S. Sioncke, L. Nyns, C.
Merckling, W.-E. Wang, M.Caymax, M. Meuris., M. Heyns.,
T. Hoffmann

© IMEC 2010 / CONFIDENTIAL G. Brammertz, PT/LDD

Outline

• Introduction: interface states
• Electrical interface state characterization techniques:
• Conductance method
• Terman method
• Berglund method
• Combined high and low frequency method
• Full simulation of electrostatics
• GaAs/oxide interface properties
• In0.53Ga0.47As/oxide interface properties
• InP/oxide interface properties
• Electrostatic effect of interface states on MOS-HEMT
devices
• Conclusions
© IMEC 2010 / CONFIDENTIAL G. Brammertz, PT/LDD 2

Interface states
Interface states arise from the sudden disruption of the lattice structure, which
creates carrier energy levels different from the usual energy band structure.
DOS
Derived mainly Derived mainly
from As from Ga
wavefunctions wavefunctions

EV EC Energy
DOS
~1015 cm-2 broken bonds ~1015 cm-2 interface states
Donors Acceptors

EV EC Energy

Charge trapping/emission at the interface
Interface defects are small localized potential wells at the surface of the material,
if their energy level lies within the bandgap.

EC EC
∆E ∆E
Eg Eg

EV EV

Charge trapping Charge emission
 ∆E 
1 exp 
τt = τ e (∆E) =  kT 
σv t N c σv t N c

• The charge trapping time τt depends only on the capture cross section of the trap
(σ), the thermal velocity (vt) and the density of states (Nc).
• The charge emission time also depends exponentially on the trap depth ΔE.


σ =10-14 cm2
Characteristic frequencies

Characteristic trap frequency (Hz)

10
10
8
GaN 10
10
GaAs 10 InP
4 8 8
10 10 10
0 6
6
10 10 10
-4
10 4
10
4
10
-8
10 2 2
-12
10 10
10 0 0
-16 10 10
10
-2 -2
-20 10 10
10
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2
Energy in bandgap (eV) Energy in bandgap (eV) Energy in bandgap (eV)



10 10 10
10 Si 10 In0.53Ga0.47As 10 InAs
8 8 8
10 10 10
6 6 6
10 10 10
4 4 4
10 10 10
2 2 2
10 10 10
0 0 0
10 10 10
-2 -2 -2
10 10 10
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0 0.2

The characteristic trap frequency varies strongly with the energy level of the trap
in the bandgap, such that with typical AC measurement frequencies only small
parts of the bandgap can be measured.

σ =10-16 cm2


10 10
10
8
GaN 10 GaAs 10 InP
4 8 8
10 10 10
0
10 6 6
10 10
-4
10 4 4
10 10
-8
10 2 2
-12 10 10
10 0
0
-16 10 10
10
-2 -2
10
-20 10 10
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2


10 10 10
10 Si 10 In0.53Ga0.47As 10 InAs
8 8 8
10 10 10
6 6 6
10 10 10
4 4 4
10 10 10
2 2 2
10 10 10
0 0 0
10 10 10
-2 -2 -2
10 10 10
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0 0.2


σ =10-18 cm2


10 10
10
8
GaN 10 GaAs 10 InP
4 8 8
10 10 10
0 6 6
10 10 10
-4
10 4
10
4
10
-8
10 2 2
-12
10 10
10 0
0
-16 10 10
10
-2 -2
-20 10 10
10
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2


10 10 10
10 Si 10 In0.53Ga0.47As 10 InAs
8 8 8
10 10 10
6 6 6
10 10 10
4 4 4
10 10 10
2 2 2
10 10 10
0 0 0
10 10 10
-2 -2 -2
10 10 10
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0 0.2


Outline

• Terman method
• Berglund method
devices
• Conclusions

Conductance method
• Interface states induce an additional capacitance
and loss contribution in the MOS structure,
represented by Cit and Rit in parallel with the
M O S
depletion capacitance.
• The capacitance and resistance of the
interface traps will be measured only if the
measurement frequency is equal to the
characteristic trap frequency at the Fermi
Ef level position.
eVG

f = 1 kHz α Dit

Cd
Cox Rs

Cit Rit

• In the example case, at Vg=1V, the Fermi level at the
semiconductor surface passes through the trap
level with a characteristic frequency of 1 kHz.

Conductance method: pitfalls*
1. Depending on the size of the bandgap of
the material, only small portions of the
bandgap can be measured with the
conductance method. Performing
measurements at lower and higher
temperatures might help for
characterizing larger parts of the bandgap
(Beware of weak inversion effects!).

2. The amplitude of the measured interface
state conductance is limited by the oxide
capacitance, such that the largest Dit that
can be extracted is of the order of Cox/q.
Dit values that approach this value will be
strongly leveled off.

*K. Martens et al., TED 55 (2), 547, 2008

Conductance method: pitfalls*
3. Weak inversion responses, due to frequencies shown
interactions of minority carriers with 1kHz → 1MHz
interface states, do behave similarly to 300K
majority carrier interface state responses.
This can lead to overestimation of the Dit,
if one applies equations that only take
majority carriers into account.

0.7

Capacitance (µF/cm )
2
4. Flatband voltage determination for 0.6 100 Hz
energy-voltage relationship extraction can
0.5
be very problematic if large frequency
0.4
dependent flatband voltage shift is present. 1 MHz
0.3
0.2

-3 -2 -1 0 1 2 3
Gate voltage (V)

*K. Martens et al., TED 55 (2), 547, 2008

Terman method (high frequency CV)
Comparison of high frequency CV curve to  dψ  −1 
C it (ψ s ) = C ox  s 
− 1 − C s (ψ s )
theoretical CV curve without interface states:  dVg 
 
 

High frequency CV-curve meaning in this case:
1. Interface states do not respond to the measurement frequency and do not add any capacitance.

10
10
In0.53Ga0.47As
• If there is a large density of fast interface states at the band edges or 10
8

even inside the conduction band of III-V semiconductors, this
6
10
4
10
condition for application of the method is not verified. 10
2

• f.ex. in the InGaAs case there is typically a large density of very fast Dit close 10
0

to the valence band as well as inside the conduction band. 10
-2

0 0.2 0.4 0.6
EV Energy in bandgap (eV) EC
2. Interface states do respond to the bias sweep, which leads to stretch out of the CV-curve.

10

• If there is a large density of very slow interface states inside the III-V
10
8
GaAs
10
semiconductor bandgap, this condition for application of the method 10
6

is not verified. 10
4

2
10
• f.ex. in the GaAs case there is typically a large density of very slow Dit close to 10
0

mid-gap, which does not respond to the bias sweep. 10
-2

0 0.2 0.4 0.6 0.8 1 1.2 1.4
Energy in bandgap (eV)

For pretty much all III-V/oxide interfaces, at least one of the conditions is not verified,
such that this method will in most cases lead to errors in the derived Dit values.

Berglund method (low frequency CV)
Comparison of low frequency CV curve to  1 1 
−1

C it =  −  − Cs
theoretical CV curve without interface states:  C LF C ox 

Low frequency CV-curve meaning in this case:
1. Interface states fully respond to the measurement frequency and add capacitance to the CV.
2. Interface states do respond to the bias sweep, which leads to stretch out of the CV-curve.
• If there is a large density of very slow interface states inside the III-V

10
10
8
GaAs
semiconductor bandgap, this condition for application of the method 10
6
10
is not verified. 10
4

• f.ex. in the GaAs case there is typically a large density of very slow Dit close to 10
2

mid-gap, which does not respond to the bias sweep, unless very slow sweep is 10
0

-2
10
used. 0 0.2 0.4 0.6 0.8 1 1.2 1.4
Energy in bandgap (eV)

Due to low conduction band density of states the theoretical Energy-Voltage curves are more
complicated than in the Si case:
• Not a limitation, just a complication that can be addressed by using the correct theoretical model
including Fermi-Dirac statistics for carrier concentrations.

For low bandgap materials (In0.53Ga0.47As, InAs, InSb,...) these conditions are typically verified,
BUT: slow oxide traps can also introduce stretchout, which could falsify the results.


Combined high-low frequency method
Derivation of Dit from both high and low  1
−1
1   1 1 
−1

C it =  −  − C − C 
frequency CV curves.  C LF C ox   HF ox 

High and low frequency CV-curves need to verify the conditions of the Terman and Berglund method
respectively, which makes this method very restrictive.

For pretty much all III-V/oxide interfaces, at least one of the conditions is not verified,
such that this method will in most cases lead to errors in the derived Dit values.


Full simulation of electrostatics
Solution of the Poisson equation,

d 2 V(x) ρ ( x)
2
=−
dx εs

Including the correct carrier In thermal equilibrium
concentrations for degenerate (Similar to Berglund method)
semiconductors, including Fermi-Dirac • For low bandgap materials (In0.53Ga0.47As, InAs,
statistics. InSb,...) these conditions are typically verified,
BUT: slow oxide traps can also introduce
stretchout, which could falsify the
results.

Ev Ei In0.53Electrons As
Ga

Trap response frequency (Hz)
Vfb Ec 10
10 Holes 0.47
8
10

6
10

4
10 AC-CV
2
10

0
10 QS-CV
-2
10
0.0 0.2 0.4 0.6
Trap energy within bandgap (eV)


Full model*
Integrating the Poisson equation:
d 2V ( x) dE ( x) e( N d − N a + p ( x ) − n ( x ) ) 2 π ∞ (E − EC )1 / 2
= E ( x) =− ,where n(V ( x) ) = N C ∫E dE
dx 2 dV ( x) εs (kT )3 / 2 C 1 + e ( E −V ( x )) / kT

yields:
V '( x ) e( N d − N a + p(V ( x)) − n(V ( x)) )
E (V ' ( x) ) = 2Sign(V s ) ∫ψ − dV ( x)
B εs .
• Applying Gauss’ theorem from the bulk to the surface of the semiconductor gives:
Vs
Es = −Qs / ε s and accordingly: Q s (V s ) = −2Sign(V s ) ∫ψ − eε s ( N d − N a + p(V ( x)) − n(V ( x)) )dV ( x)
B
.
• The semiconductor and interface state capacitances can be written as:

C s (V s ) = −
dQ s (V s )
and
d (∫
Vs
+∞ V
Dit , D dE − ∫− ∞ Dit , A dE
s
) respectively.
dVs C it (V s ) =
dV s

• The total capacitance of the MOS structure:
1 1 1
= +
C tot (V s ) C ox C s (V s ) + C it (V s ) .
• Finally, gate voltage and surface potential are related through:
Q s (V s ) Qit (V s )
VG = V s + φ m − φ s −
C ox
−
C ox .
OR, full self-consistent numerical solution of the Poisson equation for more complicated
semiconductor heterostructures
* G. Brammertz et al., APL 95, 202109 (2010)

Outline

• Terman method
• Berglund method
devices
• Conclusions

Dit distribution of GaAs with Al2O3 (S-pass. and FGA)*
p-type n-type
25°C 150°C 150°C 25°C
0.8 0.7
0.7 100Hz



2
100Hz
2

2
0.7 100Hz 0.6

2
0.7
100Hz 0.6
0.6
0.5
0.6 0.5
0.5 0.5 0.4
0.4
0.4 0.4 0.3
0.3
0.3 1MHz 0.3 1MHz 0.2 1MHz 0.2
1MHz
0.2 0.1
-3 -2 -1 0 1 2 -2 -1 0 1 2 -2 -1 0 1 2 -2 -1 0 1 2 3
Gate voltage (V) Gate voltage (V) Gate voltage (V) Gate voltage (V)

Measuring n- and p-type GaAs at both 25°C and 150°C shows the
interface state distribution in the complete bandgap.
*G. Brammertz et al., APL 93, 183504 (2008)

Dit distribution of GaAs-amorphous oxide interfaces

GaAs-Gd2O3 (MBE) GaAs-HfO2 (ALD) GaAs-Al2O3 (ALD)

Not shown here, but also measured and showing similar interface state distribution:
• GaAs-Al2O3 (MBE)
• GaAs-Ge-GeO2-Al2O3 (MBE)
• GaAs-LaAlO3 (MBE)
• GaAs-ZrO2 (ALD)
• GaAs-In-In2O3-Al2O3 (MBE)

The interface state distribution of the GaAs-amorphous oxide interface
depends rather little on the nature and the deposition condition of the oxide.


Physical identity of GaAs interface states:
Dangling bond states*
Which defect peak corresponds to what physical defect?

GaAs-Al2O3 before FGA GaAs-Al2O3 after FGA

EV EC EV EC

As dangling bonds Ga dangling bonds As dangling bonds Ga dangling bonds
passivated passivated

H passivates dangling bond states.

*G. Brammertz et al., APL 93, 183504 (2008)

Oxygen bond states*
Which defect peak corresponds to what physical defects?

Ga 3+ detectable GaAs-Al2O3 after FGA Ga 3+ not detectable

EV EC
Ga 3+

Remaining defects close to the conduction band seem
to be due to Ga3+ oxidation state (Hinkle et al.).
* C. Hinkle et al., APL 94, 162101 (2009).

Vacancies (Ga-Ga, As-As bonds)*
Which defect peak corresponds to what physical defects?

GaAs-Al2O3 after FGA

Donor

Acceptor

EV EC
As vacancy (Ga-Ga bond)
Ga vacancy (As-As bond)

The dominating mid-gap peaks, one donor-like, one acceptor-like,
are likely due to structural defects at the interface (vacancies)*
*W. E. Spicer et al., JVST 16(5), 1422 (1979).

GaAs/oxide interfaces that diverge considerably from
this picture

GaAs-Ga2O-GGO1 GaAs-aSi-HfO22
1.0
25°C 25°C

2
0.8

0.6

0.4

0.2
-1.0 0.0 1.0 2.0
VG (V)

150°C 1.0 150°C

2
0.8

0.6

0.4

0.2
-1.0 0.0 1.0 2.0
VG (V)

1 M. Passlack 1 J. De Souza et al., APL 92, 153508 (2008).
et al., EDL 30 (1), 2 (2009).
M. Passlack et al., accepted by TED (2010). C. Marchiori et al., JAP 106, 114112, (2010).

Outline

• Terman method
• Berglund method
devices
• Conclusions

Dit distribution of In0.53Ga0.47As with Al2O3 (S-pass.) :
Conductance method*
p-In0.53Ga0.47As-Al2O3-Pt n-In0.53Ga0.47As-Al2O3-Pt
300°K 300°K 77°K
77°K 0.7

0.7

2
100Hz

0.7

2

0.7

2
0.6

2
0.6 0.6
0.6
100Hz 0.5
0.5
0.5
0.5 0.4
0.4
0.4
0.3 0.3
0.4 0.3 1MHz
1MHz 0.2
0.2
-3 -2 -1 0 1 2 3 -2 -1 0 1 2 -2 -1 0 1 2 3
-3 -2 -1 0 1 Gate voltage (V)
Gate voltage (V) Gate voltage (V)
Gate voltage (V)
210°K 0.7
180°K

2

0.6
2

0.6
0.5
0.5
0.4 0.4

0.3 0.3
0.2
0.2
-3.0 -2.0 -1.0 0.0 -2 -1 0 1 2 3

*H.C. Lin et al., Microelectronic
Engineering 86, 1554 (2009)

Dit distribution of In0.53Ga0.47As with Al2O3 (S-pass.):
Conductance method
Analysis of the trap properties:

Gp/Aωq-f of p-InGaAs at 25°C Schematic band diagram
EC

EF
EV Vg = 0.5 V
0

EC

+ EF Vg = 0.1 V
0 EV

Band bending fluctuations increase as the Fermi level
approaches the valence band => donor-like interface states.

Dit distribution of In0.53Ga0.47As with Al2O3 (S-pass.):
Full electrostatic simulations*
n-In0.53Ga0.47As-Al2O3-Pt p-In0.53Ga0.47As-Al2O3-Pt

40
Acceptor D it
Donor Dit
Dit (1012/eVcm 2)

30

20

10

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Ev E-Ev (eV) Ec

Large acceptor-like Dit peak in the conduction band allows
good fit of experimental quasi-static C-V data

Comparison:
Conductance method – electrostatic simulation*
40
D it from electrostatic simulations
35
D it from conductance method
30

Dit (1012/eVcm 2)
25

20

15

10

5

0
0 0.2 0.4 0.6 0.8 1
Ev E-Ev (eV) Ec
Conductance method Electrostatic simulations
Horizontal errors arise from: Capture cross section uncertainty Gate metal work function uncertainty
Vertical errors arise from: Cox limitation of conductance Cox limitation of capacitance
Uncertainty on Cox value Uncertainty on Cox value
Non-parabolic conduction band
Charge quantization

Within the error margins there is good agreement between
the electrostatic simulation model and the conductance data

Dit distribution of In0.53Ga0.47As-amorphous oxide interfaces

InGaAs-Al2O3 (ALD) InGaAs-HfO2 (ALD) InGaAs-Al2O3 (MBE)
40 40 40
Acceptor D it Acceptor D it Acceptor Dit
35 35 35
Donor Dit Donor Dit Donor Dit
30 30 30
Dit (1012/eVcm 2)

Dit (1012/eVcm 2)

Dit (1012/eVcm 2)
25 25 25
20 20 20
15 15 15
10 10 10
5 5 5
0 0
0 0.2 0.4 0.6 0.8 1 0
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
E-Ev (eV) E-Ev (eV) E-Ev (eV)

Not shown here, but also measured and showing similar interface state distribution:
• InGaAs-Al2O3 (ALD, O3)
• InGaAs-LaAlO3 (ALD, O3)
• InGaAs-Ge-GeO2-Al2O3 (MBE)
• InGaAs-GdAlO3 (ALD)
• InGaAs-ZrO2 (ALD)

The interface state distribution of the In0.53Ga0.47As-amorphous oxide interface
depends rather little on the nature and the deposition conditions of the oxide.
Nevertheless, Hf- and Zr-based oxides usually show higher Dit at the conduction
band edge energy as compared to Al-, Gd- and La-based oxides.

Effect of ALD precursor H2O vs O3
n-In0.53Ga0.47As with HCl-clean and 10 nm ALD Al2O3
H2O ALD precursor O3 ALD precursor
0.8 0.8
Capacitance ( µ F/cm 2)

0.7 0.7
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
Gate voltage V g (V) Gate voltage V g (V)
40 40
Acceptor D it Acceptor D it
35 35
Donor D it
Donor Dit
30

Dit (1012/eVcm 2)
30
Dit (1012/eVcm 2)

25 25
20 20
15 15
10 10
5 5
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
E-Ev (eV)
E-Ev (eV)

O3-based ALD increases the Dit at the conduction band edge
energy as compared to H2O-based ALD


Effect of forming gas anneal
n-In0.53Ga0.47As with (NH4)2S-clean and 10 nm ALD Al2O3
No FGA with FGA
0.8 0.8

Capacitance (µ F/cm 2)

0.7 0.7
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
40 40
Acceptor D it Acceptor D it
35 35
Donor Dit Donor Dit
30 30

Dit (1012/eVcm 2)
2
Dit (10 /eVcm )

25 25

20 20
12

15 15

10 10

5 5

0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
E-Ev (eV) E-Ev (eV)

Forming gas anneal reduces the Dit over the full bandgap.
80% of the improvement is a thermal effect and not related to H (not shown).


Effect of (NH4)2S clean
n-In0.53Ga0.47As with 10 nm ALD Al2O3 and FGA
HCl clean (NH4)2S clean
0.8 0.8

0.7 0.7
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
40 40
Acceptor D it Acceptor Dit
35 35
Donor D it Donor Dit
30 30
Dit (1012/eVcm 2)

Dit (1012/eVcm 2)
25 25

20 20

15 15

10 10

5 5

0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
E-Ev (eV) E-Ev (eV)

(NH4)2S cleaned samples are better than HCl (10%) cleaned samples.
The difference between the two interfaces is rather small though.


Effect of oxide scaling
n-In0.53Ga0.47As with (NH4)2S-clean, ALD Al2O3 and FGA
5 nm Al2O3 10 nm Al2O3
1.6 1.6
1.4

1.4

1.2 1.2

1 1

0.8 0.8

0.6 0.6
0.4 0.4
0.2 0.2
0 0
-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3
40 40
Acceptor D it Acceptor Dit
35 35
Donor D it Donor D it
30 30

Dit (1012/eVcm 2)
Dit (1012/eVcm 2

25 25

20 20

15 15

10 10
5 5
0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
E-Ev (eV) E-Ev (eV)

Dit profile does not change much when the Al2O3 is thinned to 5 nm


Comparison to literature results
p-type n-type
0.7

0.7

2
2
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
-3 -2 -1 0 1 2 3 ALD Al2O3 -2 -1 0 1 2
ALD Al2O3
Shin et al., APL 96, Kim et al., APL 96,
152908 (2010) 012906 (2010)

ALD HfO2 MBE LaAlO3 Sputtered HfO2
Sputtered HfO2
O’Connor et al., APL 92, Goel et al., APL 91, Kim et al., APL 93,
Kim et al., APL 93, ALD Al2O3 022902 (2008) 091507 (2007) 062111 (2008)
062111 (2008) Xuan et al., EDL 28,
935 (2007)

ALD AlN-HfO2 ALD ZrO2 Sputtered Si-HfO2
MBE HfO2 Shahrjerdi et al., EDL 29, Koveshnikov et al., APL 92, Zhu et al., ESL 12 (4),
Hwang et al., APL 96, 558 (2008) 222904 (2008) H131 (2009)
102910 (2010)

There does not seem to be any In0.53Ga0.47As/oxides interface
in literature that diverges considerably from this picture

Outline

• Terman method
• Berglund method
devices
• Conclusions

Dit distribution of InP with Al2O3 (S-pass.) :
Conductance method
0.40 0.7
0.6 0.6
300K 300K 180K 77K



2

2

2

2
0.35 0.6
0.5 0.5
0.30
0.25
p-type 0.5 n-type 0.4 n-type 0.4
n-type
0.4
0.20 0.3 0.3
0.15 0.3
0.2 0.2
0.10 0.2
0.1 0.1
-3 -2 -1 0 1 2 -1 0 1 2 3 -1 0 1 2 3 -1 0 1 2 3
Gate voltage (V) Gate voltage (V) Gate voltage (V) Gate voltage (V)

InP presents very large Dit in the lower half of the bandgap that is impossible to
measure as the Fermi level pins well before reaching that part of the bandgap.
Dit close to the conduction band edge energy is low, similar to InGaAs.

Outline

• Terman method
• Berglund method
devices
• Conclusions

MOS implant-free quantum-well transistor
Transistor geometry:
Gate metal Al2O3

SiO2 1. Highly doped n+ source and drain are in-situ grown and
etched on top of the channel.
n+InGaAs
2. After surface clean, ALD Al2O3 oxide is grown followed by
30 nm ud-In0.53Ga0.47As gate metal deposition.
100 nm ud-In0.53Al0.47As 3. Source and Drain areas are opened and contacted with a
metal.
SI-InP substrate

Band diagrams: 1
Off On
0.5

0.5
0
Potential (eV)

Potential (eV)
0
-0.5
-0.5

-1
-1

-1.5 -1.5
0 20 40 60 80 100 120 0 20 40 60 80 100 120
Position (nm) Position (nm)


1D electrostatic device simulation:
In0.53Ga0.47As/oxide interface
Device: - 4 nm EOT oxide.
- Metal gate (Φm = 4.7 eV).
- Dit distribution as measured on capacitors. 2

Semiconductor charge (10 12/cm 2)
10

1

Surface potential (V)
0.8 0
10
0.6

0.4
~3 1012 cm-3
0.2
10
-2
mobile carriers
0
in channel
-0.2
Off On 10
-4

-1.5 -1 -0.5 0 0.5 1 1.5 SS ~ 110 mV/dec.
Gate voltage V g (V)

40
Off 40
On
35 35

30 30
Dit (1012/eVcm 2

~1012 cm-3

Dit (1012/eVcm 2
25

20
25

20
~2 1012 cm-3
15 fixed charges 15 fixed charges
10 10

5

0
+ 5
-
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
E-Ev (eV) E-Ev (eV)

Influence of Dit on the electrostatics of the device is relatively limited.

Comparison to experimental data1 2

Gate metal Gate oxide: 8 nm ALD Al2O3
Al2O3
Pretreatment: HCl + (NH4)2S
SiO2 Channel: 30nm ud-InGaAs (53%)
FGA @ 370C,15min
*
n+InGaAs
30 nm ud-In0.53Ga0.47As

100 nm ud-In0.53Al0.47As
CET 3.8 nm
S.S. 115 mV/dec
SI-InP substrate
Low field mobility 1600 cm2/Vs

10 m gate length device:
50 Vg Vd
2V 30 2.1V
1.5V 1.6V
40

gm (mS/mm)
Id (mA/mm)

1V 1.1V
0.5V 0.6V
30 20 0.1V

20
10
10
0 0
0.0 0.5 1.0 1.5 2.0 2.5 -3 -2 -1 0 1 2 3
Vd (V) VG (V)

Experimental subthreshold slope in agreement with measured Dit values
1 A. Alian et al., submitted to Microelectronic Engineering (2010).
2 H. Zhao et al., JVST B 27 (4), 2024 (2009).

* M. Radosavljevic et al., IEDM 2009.
1D electrostatic device simulation:
InP/oxide interface *
Device: - 1 nm EOT oxide (1.6 nm CET).
- 2 nm InP top layer – In0.53Ga0.47As channel.
- Metal gate (Φm = 4.9 eV).
- Dit distribution as measured on capacitors.
2

Semiconductor charge (10 12/cm 2)
10
1.5

Surface potential (V)
0
10
1
~3 1012 cm-3
0.5
10
-2 mobile carriers
in channel
0
Off On
-1.5 -1 -0.5 0 0.5 1
10
1.5
-4
SS ~ 90 mV/dec.
Gate voltage V g (V)

Off On

Interface state density D it (1012/eVcm 2)
Interface state density D it (1012/eVcm 2)

50 50
Acceptor Dit Acceptor Dit

Donor Dit Donor Dit
40 40

30 30

~1012 cm-3 20
20

fixed charges ~ no fixed
10 10
charges
0
-0.2 0 0.2 0.4 0.6 0.8
+1 1.2 1.4
0
-0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4
Ef-Ev (eV) Ef-Ev (eV)

Influence of Dit on the electrostatics of the device is relatively limited.

Conclusions
Schematic representation of different III-V/amorphous oxide Dit profiles.

GaAs InP In0.53Ga0.47As
Acceptor Dit
1.6
Donor Dit

1.4
? Acceptor Dit
1.6
1.2 Donor Dit
1 Acceptor D it
1.4
1 Donor Dit
E-E (eV)

0.8
1.2
0.8
v

E-E (eV)
0.6
1
0.6

E-E (eV)

v
0.4
0.8

v
0.4
0.2
0.6
0.2
0 11
0.4 12 13 14
0 11 10 10 10 10
12 13 14
10 10 10 10 Dit (1012/eVcm 2)
12 2 0.2
Dit (10 /eVcm )

0 11 12 13 14
10 10 10 10
Dit (1012/eVcm 2)

Despite high Dit in most parts of the bandgap, nMOS devices based on InP and
InGaAs interfaces move the surface potential in an energy region close to the
FLSE with relatively low Dit, which makes close to ideal device operation possible.

Acknowledgements

European Commission for financial support in the DualLogic project no.
214579.

IMEC core partners within the IIAP on Logic-DRAM.


IBM III-V workshop 2010

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