ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits
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This document presents an ILP formulation to maximize toggling in combinational circuits for power estimation. It defines variables and constraints for logic gates. The constraints include I/O behavior, linearization of products, and toggling. The objective is to maximize the sum of toggles on all nets. The approach was tested on ISCAS benchmarks and found to toggle over 50% of nets within hours on a desktop computer using ILP solvers like GLPK and CPLEX. Future work includes handling delays, weighted fanouts, and extending the approach to sequential circuits.
![Power Pattern Generation
Maximum power estimation for sequential circuits using a test generation
based technique [Kaushik Roy et al, CICC, 1996]
Greedy toggle assignment proportional to
fan-out factor
– Gates are sorted in non-increasing order by their
fan-out
– In each iteration of algorithm, the gate having
larger fan-out and not yet tried is assigned a 0->1
or 1->0 toggle.
Assignment is then justified like D-algorithm
Heuristic based on larger fan-out alone, may not
estimate the worst case pattern
6 07/10/12](https://image.slidesharecdn.com/vdat2012presentationv6-2-120710034446-phpapp02/85/ILP-Based-Approach-for-Input-Vector-Controlled-IVC-Toggle-Maximization-in-Combinational-Circuits-6-320.jpg)
![Boolean Satisfiability based
technique (SAT)
Using SAT-based techniques in power estimation, [F. Aloul et al,
Elsevier, 2007]
8 07/10/12](https://image.slidesharecdn.com/vdat2012presentationv6-2-120710034446-phpapp02/85/ILP-Based-Approach-for-Input-Vector-Controlled-IVC-Toggle-Maximization-in-Combinational-Circuits-8-320.jpg)
ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits
- 1. ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits VDAT 2012 Jaynarayan Tudu, IISc Bangalore Deepak Malani, IIT Bombay Virendra Singh, IIT Bombay
- 2. Outline Introduction and Motivation to Power Estimation Previous Work ILP based formulation of combinational logic – Constraints – Optimization Function Performance on ISCAS Benchmarks Roadmap 2 07/10/12
- 3. Introduction Power dissipation Static Power Dynamic Power 2 Vdd * Istatic CL* Vdd * Ptran * fclock 3 07/10/12
- 4. Motivation Estimation of peak-power dissipation determines – Maximum current demand – VDD droop (due to IR-drop) – Design of power delivery network (PDN) VDD IR-drop 4 07/10/12 Clock
- 5. Power Estimation Approaches Vector-less – Probabilistic Vector-based – Power pattern generation 5 07/10/12
- 6. Power Pattern Generation Maximum power estimation for sequential circuits using a test generation based technique [Kaushik Roy et al, CICC, 1996] Greedy toggle assignment proportional to fan-out factor – Gates are sorted in non-increasing order by their fan-out – In each iteration of algorithm, the gate having larger fan-out and not yet tried is assigned a 0->1 or 1->0 toggle. Assignment is then justified like D-algorithm Heuristic based on larger fan-out alone, may not estimate the worst case pattern 6 07/10/12
- 7. Mathematical Expressions for logic gates GATE Type Boolean Algebraic SAT* Expression Expression Expression x z z= x z=1-x (x+z).(x+z) x z z = x.y z = 1 – x.y (x+z).(y+z). (x+y+z) y *CNF: Conjunctive Normal Form 7 07/10/12
- 8. Boolean Satisfiability based technique (SAT) Using SAT-based techniques in power estimation, [F. Aloul et al, Elsevier, 2007] 8 07/10/12
- 9. Boolean Satisfiability based technique (SAT) Formulation is expressed as pseudo Boolean SAT expression – CNF expressions – Objective function ILP solver found to be comparatively efficient than SAT solvers – CPLEX (ILP solver) v/s PBS, Galena, MiniSAT+ 9 07/10/12
- 10. Quest directions SAT solver SAT formulation ILP solver ILP formulation ILP solver 10 07/10/12
- 11. ILP Formulation Steps 1) Variable definition 2) Constraints 3) Optimization function 4) Solver (iterative) 11 07/10/12
- 12. ILP Formulation 2.a) I/O Constraints – INV : y=1-x – NAND2 : y = 1 – x1* x2 – NOR2 : y = 1 – (x1 + x2) + x1* x2 12 07/10/12
- 13. ILP Formulation 2.b) Product Linearization Constraint z = 1 – x*y define p = x*y s.t. z=1–p p≤x p≤y x+y–p≤1 13 07/10/12
- 14. ILP Formulation Example y = 1 – x1* x2 p = x1* x2 s.t. x1 y y=1–p x2 p ≤ x1 z p ≤ x2 x3 x1 + x2 – p ≤ 1 z = 1 - y * x3 q = y* x3 s.t. z=1–q q≤y q ≤ x3 14 07/10/12 y + x3 – q ≤ 1
- 15. ILP Formulation 2.c) Toggle count constraint – For each net five variables are defined – x1 and x2 successive logic values of net ‘x’ 1) x1 2) x1 = 1- x1 3) x2 4) x2 = 1- x2 5) tgate_x = x1.x2 + x1.x2 3) Optimization function – Maximize ∑ (tgate_i) i = 1:N 15 07/10/12
- 16. ILP Formulation t1 = y1.y2 + y1.y2 x1 y1 t2 = z1.z2 + z1.z2 x2 y2 z1 x3 z2 16 07/10/12
- 17. ILP Formulation - Summary Variable definition Constraints I/O Linearization Toggle Optimization function Toggle Maximization Solver Generate successive pair of primary input vectors 17 07/10/12
- 18. ILP Formulation I/O Constraints for n-input gates – NAND: y = 1 – ∏ xi – NOR : y = 1 – ∑ xi * xj + … (-1)n ∏ xi 18 07/10/12
- 19. Performance Analysis ISCAS-85 benchmarks Machine – Dual Core AMD Opteron, @1GHz ILP Solvers – GLPK, CPLEX 19 07/10/12
- 20. Observations Circuit #PI #Nets #Toggle %Toggle Solver Time (sec) c04 1 4 4 100 0.09 c05 3 8 7 87.5 0.05 c11 3 6 5 83.3 0.02 c14 2 4 3 75 0.03 c17 5 6 6 100 0.02 c432 36 296 243 82 8.86 c499 41 626 360 57.5 3406.00 c880 60 592 491 82.9 21.55 c1355 41 690 415 60.1 3616.48 c1908 33 1291 832 64.4 2371.53 c2670 233 1925 1362 70.7 559.65 c5315 178 4897 2635 53.80 3399 20 07/10/12
- 21. Conclusion Any large combinational circuit can be represented as BIP Can use ILP solver for Toggle maximization and thereby generate Input Vector pair >53% nets toggling Cuts method speeds up optimal polyhedron computation 21 07/10/12
- 22. Roadmap Non-zero delay consideration – define multiple levels in combinational logic Fanout consideration – weighted function Implementation of the methodology to sequential circuits, by unfolding Explore SAT Solvers – MiniSAT+ 22 07/10/12
- 23. Resources Source code, Slides, Paper – www.DeepakMalani.in 23 07/10/12
- 24. Acknowledgements LSI R&D Center, Bangalore – Research grant Pramod Subramanyan, Princeton University – for support in BILP formulation 24 07/10/12
Editor's Notes
- #12: Converted all gates to NAND and NOR gates, Universal gates
- #13: Converted all gates to NAND and NOR gates, Universal gates
- #14: Converted all gates to NAND and NOR gates, Universal gates
- #15: Converted all gates to NAND and NOR gates, Universal gates
- #17: Converted all gates to NAND and NOR gates, Universal gates
- #19: * Hide this slide. * Converted all gates to NAND and NOR gates, Universal gates