Introduction to Microprocessor & Microcontroller.ppt

Editor's Notes

• #2: To do this week: get book, order a board, {read chapters 1 and 2 of the book or ebook 2 3 4}, do ws01, HW1, install Keil uVision 4.73 on laptop
• #5: Consumer electronics: Washing machine, Exercise equipment, Remote controls, Clocks and watches, Games and toys, Audio/video electronics, Set-back thermostats, Camera, Camcoder, Television, VCR, cable box Communication systems: Answering machines, Telephones, Fax machines, Radios, Cellular phones, pagers Automotive systems: Automatic breaking, Noise cancellation, Locks, Electronic ignition, Power windows and seats, Cruise control, Collision avoidance, Climate control, Emission control, Instrumentation Military hardware: Smart weapons, Missile guidance systems, Global positioning systems, Surveillance systems Business applications: Cash registers, Vending machines, ATM machines, Traffic controllers, Industrial robots, Bar code readers and writers, Automatic sprinklers, Elevator controllers, RFID systems, Lighting and heating systems Medical devices: Monitors, Drug delivery systems, Cancer treatments, Pacemakers, Prosthetic devices, Dialysis machines
• #7: Processor There are two classifications of computers: complex instruction set computer (CISC) and reduced instruction set computer (RISC). In reality, there is a spectrum of architectures that we can classify as CISC or RISC. We make these general observations when deciding whether to call a computer CISC or RISC: Complex instruction set computers (CISC) Early computers offered CPUs that were much faster than available memories. Fetching instructions limited performance A single complex instruction could perform many operations Example: Find the zeros of a polynomial Complex instructions require many processor clock cycles to complete and most instructions can access memory A program running on a CISC computer employed a relatively small number of complex instructions High code density, many instruction types w/ varying length, fewer and specialized registers, many addressing modes Complexity is embedded in the processor hardware (overhead) Examples: Intel (x86), Freescal 9S12 Reduced Instruction Set Computers (RISC) Memories match CPU speed No large penalty for instruction fetch Instructions simplified Example: dedicated load/store instructions, regular instructions can not access memory but only registers Single processor clock cycle per instruction (pipelined) A program running on a RISC computer employs a relatively larger number of simplified instructions Reduced code density, few instructions w/ fixed delay (pipeline!), many identical general-purpose registers, few addressing modes Complexity exists in the assembly code generated by the programmer or compiler, hardware is simple (low overhead/low power) Examples: LC3, MIPS, ARM, SPARC, PowerPC Which architecture is best is beyond the scope of this class, but it is important to recognize the terminology. It is very difficult to compare the execution speed of two computers, especially between a CISC and a RISC. One way to compare is to run a benchmark program on both, and measure the time it takes to execute. Time to execute benchmark = Instructions/program * Average cycles/instruction * Seconds/cycle For example, the 50 MHz ARM Cortex M has one bus cycle every 20ns. One average it may require 1.5 cycles per instruction. If the benchmark program executes 10,000,000 assembly instructions, then the time to execute the benchmark will be 0.3 seconds. Memory: EPROMs are Erasable Programmable ROMs. The mechanism used to erase and write is UV light EEPROMs are Electrically Erasable Flash memory is like EEPROM however writes are performed in large blocks as opposed to single bytes. Cheaper hence popular DRAMs require a periodic refresh SRAMs don’t. Both are volatile therefore are lost when powered down. Interfaces: Parallel - binary data is available simultaneously on groups of lines Serial - binary data is available one bit at a time on a single line Analog - data is encoded as a variable voltage Time - data is encoded as a period, frequency, pulse width or phase shift I/O Memory-mapped I/O I/O ports/registers appear as addresses on common bus with memory I/O ports/registers are accessed as though they are locations in memory Employed on the ARM, Freescale and TI processors I/O-mapped I/O I/O ports/registers have separate control signals from those used with memory Special instructions are used to access I/O ports/registers Employed on Intel x86 processors
• #9: The Fork-Join construct is used in Parallel programming. This is different from multi-threading used in concurrent (Distributed) programming. In multi-threading there may be multiple threads that are active but at any given instant only one of them is being executed. In desktop systems that have multiple cores and parallel computers with several processors, multiple threads can be simultaneously executed.
• #11: < : Hardware Interrupt causing the main program to be suspended and the corresponding ISR to execute > : Return from Interrupt causing the control to be returned to the point where the main program was suspended. The execution sequence of this simple system might be something like: ABCDB<E>CDBC<E>DBCD<E>BCD… We say this code is multi-threaded because we have two threads: The foreground thread computes the primes and the background thread issues a pulse. They are both active at the same time.
• #12: The LC3 computer from EE 306 had an address space of 64Ki and an addressability of 16-bit for a total of 128KiB. The Memory Address Register (MAR) is 16 bits and the Memory Data Register (MDR) is also 16-bits. Vs. On the ARM, the MAR is still 32-bits. Total addressable memory is 4GiB. It has flexible addressability (bit,byte-8bits,halfword-16bits,word-32bits)
• #14: The PC points to the address of the current instruction (Program Counter) The Link Register is akin to Register R7 in LC3 used to store the return address on subroutine calls. The stack is a temporary storage implemented in the RAM. We push and pop elements onto and off the stack as we desire. The stack pointer (SP) keeps track of the current location of the “top” of the stack. The CC (condition-code) bits contains codes that reflect the results of the most recent instruction. Many “branch” type instructions “test” these bits for their operation. The Program Status Register (PSR) has them.
• #17: The lines marked in red are “leagacy code” the next slide shows what the new way is. If we are using portF pin 0 or portD pin 7, we have to perform an additional step to unlock these ports by writing the following: GPIO_PORTF_LOCK_R = 0x4C4F434B; // *) unlock GPIO Port F GPIO_PORTD_LOCK_R = 0x4C4F434B; // *) unlock GPIO Port D
• #18: If we are using portF pin 0 or portD pin 7, we have to perform an additional step to unlock these ports by writing the following: GPIO_PORTF_LOCK_R = 0x4C4F434B; // *) unlock GPIO Port F GPIO_PORTD_LOCK_R = 0x4C4F434B; // *) unlock GPIO Port D
• #28: Debugging principles Control and observability Can’t see everything; need to be smart when debugging
• #29: Minimally intrusive Dumps execute faster (<1us) compared to print statements (10ms)
• #30: Commands given: 1: WS 1, `VarName,0x10 Puts the variable called VarName in the first watch window 2: LA (PORTD & 0x02)>>1 Puts port D pin 2 in logic anlayzer
• #31: Black box testing Control inputs, observe outputs White box testing 0) pick the most likely place of failure 1) desk check: conceive of what you expect will happen at each step 2) breakpoint at the start of the place 3) single step (or step over) 4) compare what actually happened to what you wanted to have happen