Lecture03-Modelling-Structuresqweqweqwe.pdf

Lecture 03
Modeling Structures

Chapter Overview
2
Last Time
•Objectives
•Introduction
•Hierarchy
•Modules
•Ports
Today
•Modeling Structures
 Parameters
 Registers
 Primitives
 Continuous Assignments
 Procedural Blocks
 Tasks and Functions

Modelling Structures
 Parameters
 Nets
 Registers
 Primitives and Instances
 Continuous Assignments
 Procedural Blocks
 Task/Function definitions
3

Parameters - Redefinition
 Parameters can be redefined on a module instance  useful
for vector widths.
 For example, the following module implements a shifter:
module shift (shiftOut, dataIn, shiftCount);
parameter width = 4;
output [width-1:0] shiftOut;
input [width-1:0] dataIn;
input [31:0] shiftCount;
assign shiftOut = dataIn << shiftCount;
endmodule
 This module can now be used for shifters of various sizes, simply
by changing the width parameter. Parameters can be changed per
instance in either of two ways. 5

Modelling Structures – Parameters –
Redefinition (cont.)
Two ways to change parameter values from their defaults:
defparam statements and module instance parameter
assignment.
6
 defparam: change a module instance parameter directly
from another module.
Example:
shift sh1 (shiftedVal, inVal, 7); //instantiation of shift module
defparam sh1.width = 16; // parameter redefinition
 Note that the defparam statement changes just the
named parameter in the named module instance.

Modelling Structures – Parameters – Redefinition
(cont.)
 Parameter values can be specified in the module
instantiation directly:
 shift #(16) sh1 (shiftedVal, inVal, 7); //instance of 16-bit shift module
When there is more than one parameter in the module being
instantiated, all parameters to be given new values are listed in the
parentheses, in the order they are defined in the module definition,
and the new values are assigned positionally.
7

 So, if there are 3 parameters in the module, named par1, par2, and
par3, then the instantiation would look like:
foo #(10,20,30) f1 ( in1, out1);
 However, this method has a problem if you want to redefine
some, but not all, parameters in an instance.
 Can do that using defparam, since it is insensitive to parameter
order.
8

12

Modelling Structures – Nets
 Nets  connect model components together
 thought of as wires in a circuit, declared in
statements like this:
net_type [range] [delay3] list_of_net_identifier;
 or
net_type [drive_strength] [range] [delay3]
list_of_net_decl_assignments;
13

Modelling Structures – Nets
 Typical net declarations would be:
wire w1, w2;
tri [31:0] bus32;
wire wire_number_5 = wire_number_2 & wire_number_3;
 Nets should be declared before they are used.
 However, if you don't declare one before it is used
in an instance port list, it will default to a predefined
net type, normally a scalar wire.
14

Modelling Structures – Nets (cont.)
 net_type: wire, tri, tri0, tri1, wand, wor, triand, trior,
supply0, supply1. (Use the wand to insert an and gate and the
wor type to create an or gate; tri type is driven to high impedance)
 Range: Indication of how many bits wide the net should
be. The form is [msb:lsb].
 The range specifier can be used to declare a multi-bit
quantity for a net.
wire o_nor; // single bit scalar net
wire [7:0] o_flop; // 8-bit vector net
reg parity; // single bit scalar variable
reg [31:0] addr; // 32-bit vector variable to store address
 general syntax: <type> <size> <variable_name>;
15

delay3
 specifies the length of time between when a driver on this net
changes value and when that value is seen by other elements the net
drives.
 The "3" indicates rise, fall, and turnoff delays.
The default delay is zero.
If only one delay value is specified then it is used for all signal changes.
If two delays are specified then the first delay specifies the rise delay and
the second delay specifies the fall delay.
If the signal changes to high-impedance (z) or to unknown (x) then the
smaller value will be used. This means that if delays are specified as
follows: #(4,3) then the second value (3) will be used for signal changes to
z or x value.
If three values are given, then the first value specifies the rise delay, the
second specifies the fall delay, and the third specifies turn-off delay. If the
signal changes to unknown (x) value, then the smallest of these three
values will be used. 16

Modelling Structures – Nets (cont.))
 drive_strength: This is an indication of the strength of the signal
being driven by the assignment
17
A strength specification
has two components:
1. the strength of the 0 portion
of the net value, designated
<STRENGTH0>
2. the strength of the 1 portion
of the net value, designated
<STRENGTH1>
Simplified Syntax
(Strength1, Strength0)
(Strength0, Strength1)

18
The ability to model varying signal levels as produced by digital hardware is
fundamentally important for the simulation of switch level circuits.
Strength Name Strength Level Element Modelled
Declaration
Abbreviation
Supply Drive 7
Power supply
connections.
supply
Strong Drive 6
Default gate & assign
output strength.
strong
Pull Drive 5
Gate & assign output
strength.
pull
Large Capacitor 4
Size of trireg net
capacitor.
large
Weak Capacitor 3
Gate & assign output
strength.
weak
Medium Capacitor 2
Size of trireg net
capacitor.
medium
Small Capacitor 1
Size of trireg net
capacitor.
small
High Impedence 0 Not Applicable. highz
Signal strength definitions.

19
Modelling of weak (resistive) transistors :
• Any signal passed through transistor is degraded
• This is modelled within Verilog using signal strengths which are
reduced when they encounter resistive transistors.
Input Strength Output Strength
supply pull
strong pull
pull weak
weak medium
large medium
medium small
small small
highz highz

20
Modelling of weak (resistive) transistors :
 Simple latch circuit exhibiting signal contention.

21
• The situation: two signals drive one node in a circuit resulting in signal
contention.
• The strength and logic value of the two signals are used to resolve the
signal conflict to produce a single logic value and strength on the node.
a) Similar logic, strength contention.
b) Similar strength, logic contention.
c) Logic and strength contention.

Question
 Are the following statements syntactically
correct?
a. Yes No wire [1:0] w1, w2;
b. Yes No wire w1, [1:0] w2;
22

Question
correct?
a. Yes No wire [1:0] w1, w2;
b. Yes No wire w1, [1:0] w2;
23
The first statement is correct and the second statement is
incorrect.
Here is an example of a correct statement for b.:
b. wire w1; wire[1:0]w2;
Yes
No

Modelling Structures – Registers
Registers are storage elements.
Values are stored in registers in
procedural assignment statements.
24
Registers can be used as the source for a primitive or
module instance (i.e. registers can be connected to input
ports).

Modelling Structures – Registers
Registers are declared in statements like this:
reg [range] list_of_register_identifiers ;
or integer list_of_register_identifiers ;
or time list_of_register_identifiers ;
or real list_of_real_identifiers ;
or realtime list_of_real_identifiers ;
 Typical register declarations would be:
reg r1, r2;
reg [31:0] bus32;
integer i;
real fx1, fx2;
25

Modelling Structures – Registers – Types and Data
Values
There are four types of registers:
 1. Reg:
+ A reg declaration can specify registers which are 1 bit
wide to 1 million bits wide.
+ A register declared as a reg is always unsigned.
 2. Integer: are 32 bit signed values.
+ Arithmetic done on integers is 2's complement.
26

Modelling Structures – Registers – Types and Data
Values
 3. Time: Registers declared with the time keyword are
64-bit unsigned integers.
 4. Real (and Realtime):
+ Real registers are 64-bit IEEE floating point.
+ Not all operators can be used with real operands.
+ Real and realtime are synonymous.
+ Each bit in a register can take on one of four values: 0, 1, x,
or z.
27

Question
correct?
 a. Yes No reg x, y, z;
 b. Yes No reg [5:0] x, [5:0] y;
28

Question
correct?
 a. Yes No reg x, y, z;
 b. Yes No reg [5:0] x, [5:0] y;
29
The first statement is correct and the second statement is
incorrect.
Here is an example of a correct statement for for b.:
b. reg [5:0]x, y;
correct
incorrect.

Modelling Structures - Primitives
 Primitives are pre-defined module types.
 They can be instantiated just like any other module type.
 The Verilog primitives are sometimes called gates, because
for the most part, they are simple logical primitives.
1-output 1-input tristate pull
and, nand buf, not bufif0,notif0 pullup
or, nor bufif1,notif1 pulldown
xor, xnor
30

Modelling Structures – Primitives – Built-In -
Example
 The following module implements a 2-bit to 4 decoder.
module decodeX4 (b0, b1, b2, b3, in0, in1);
output b0, b1, b2, b3;
input in0, in1; // select inputs
not N1 (t0, in0); // invert inputs
not N2 (t1, in1);
and A1 (b0, t1, t0); // decode inputs => outputs
and A2 (b1, t1, in0);
and A3 (b2, in1, t0);
and A4 (b3, in1, in0);
endmodule
31

Modelling Structures – Primitives – Built-In -
Example
 The following module implements a 2-bit to 4 decoder.
not N1 (t0, in0); // invert inputs
not N2 (t1, in1);
and A1 (b0, t1, t0); // decode inputs => outputs
and A2 (b1, t1, in0);
and A3 (b2, in1, t0);
and A4 (b3, in1, in0);
endmodule
32

Question
Are the following statements syntactically correct?
a. Yes No and #1 a1 (a, b, c);
b. Yes No and (a,b,c), (d,e,f);
c. Yes No AND #1 (a, b, c);
33

Question
34
Here are two examples of correct statements for c.:
c. and #1 (a,b,c);
or
c. AND #1 myand (a,b,c);
Note that "AND #1 myand (a,b,c);" instantiates a module which is
not a primitive.
correct
correct
incorrect

Question
35
Here are two examples of correct statements for c.:
c. and #1 (a,b,c);
or
c. AND #1 myand (a,b,c);
Note that "AND #1 myand (a,b,c);" instantiates a module which is
not a primitive.
correct
correct
incorrect

Chapter Overview
36
Last Time
•Objectives
•Introduction
•Hierarchy
•Modules
•Ports
Today
•Parameters Registers
•Primitives
•Continuous Assignments
•Procedural Blocks
•Tasks and Functions

Modelling Structures - Continuous assignments
 are data flow statements because they describe how
data moves from one place, either a net or register, to
another.
 representing combinational logic.
 logic functionality which can be implemented by means
of a continuous assignment can also be implemented
using primitive instances.
37

Modelling Structures - Continuous assignments
 A continuous assignment looks like this:
assign [drive strength] [delay3] list_of_net_assignments;
 Examples:
assign w1 = w2 & w3;
assign (strong1, pull0) mynet = enable;
assign #1 busout = enable ? data : 16'bz;
38

Continuous assignments - Example
assign b0 = ~in1 & ~in0; // decode inputs => outputs
assign b1 = ~in1 & in0;
assign b2 = in1 & ~in0;
assign b3 = in1 & in0;
endmodule
39

Continuous assignments - Example
assign b0 = ~in1 & ~in0; // decode inputs => outputs
assign b1 = ~in1 & in0;
assign b2 = in1 & ~in0;
assign b3 = in1 & in0;
endmodule
40

Question
correct?
 a. Yes No assign #10 x = f(y);
 b. Yes No assign x = f(y);
 c. Yes No assign #(5,10) x = a ? b : c;
41

Question
correct?
 a. Yes No assign #10 x = f(y);
 b. Yes No assign x = f(y);
 c. Yes No assign #(5,10) x = a ? b : c;
42
You got it. All three statements are syntactically correct.

Modelling Structures - Procedural blocks
 Procedural blocks represents sequential behavior.
 The statements in each block are executed sequentially,
 but the blocks themselves are concurrent and
asynchronous to other blocks.
43

Modelling Structures - Procedural blocks (cont.)
 There are two types of procedural blocks: initial
blocks and always blocks.
initial <statement>
always <statement>
 All initial and always blocks contain a single
statement, which may be a compound statement:
44
initial
begin
statement1 ;
statement2 ;
...
end

Modelling Structures - Procedural blocks - initial
All initial blocks begin at time 0 and execute
the initial statement.
Statements within initial block are used in
Verilog for generating test signals, example
clocks, resets etc.
45

Procedural blocks - initial
46
 Initial statements can’t be synthesized because
actual behavior of hardware is difficult to model
using fixed delays.
 Are used only for testbench purposes and to
initialize the values at zero simulation time.

Modelling Structures - Procedural blocks - initial
 There may be time or event controls, as well as all
of the control constructs in the language.
 An initial block may cause activity to occur
throughout the entire simulation of the model.
47

Example
initial x = 0; // a simple initialization
initial begin
x = 1; // an initialization
y = f(x);
#1 x = 0; // a value change 1 time unit later
y = f(x);
end
initial begin
a = 0;
@(posedge clk)
a = 1; // change value on the clock edge
for (i=0; i<10; i=i+1)
@(posedge clk) ; // wait for 10 clock cycles
$finish; // terminate simulation
end 48

Modelling Structures - Procedural blocks -
Always
 Always blocks also begin at time 0.
 The only difference between an always block and an
initial block is that when the always statement finishes
execution, it starts executing again.
 Note that if there is no time or event control in the always
block, simulation time can never advance beyond time 0.
Example:
always
#10 clock = ~clock;
49

Modelling Structures - Procedural blocks -
Asynchronicity
 There may be many initial and always blocks in the entire
model.
 All of them begin execution at time 0. However, there is no
defined order between them.
 There is a time or event control to establish that
relationship.
50

Question
 What is the correct way to sample the signal x
whenever clock transitions from 0 to 1?
 a. always (clock) sample = x;
 b. always @(posedge clock) #1 sample = x;
 c. always @(posedge clock) sample = #1 x;
 d. always @(posedge clock) sample = x;
 e. always @(clock) sample = x;
 f. always (posedge clock) sample = x;
 g. a or f
 h. b or c
 i. c or d
 j. none of the above 51

Question
 What is the correct way to sample the signal x
whenever clock transitions from 0 to 1?
 a. always (clock) sample = x;
 b. always @(posedge clock) #1 sample = x;
 c. always @(posedge clock) sample = #1 x;
 d. always @(posedge clock) sample = x;
 e. always @(clock) sample = x;
 f. always (posedge clock) sample = x;
 g. a or f
 h. b or c
 i. c or d
 j. none of the above 52
The correct answer is i

Chapter Overview
53
Last Time
•Objectives
•Introduction
•Hierarchy
•Modules
•Ports
Today
•Parameters Registers
•Primitives
•Continuous Assignments
•Procedural Blocks
•Tasks and Functions

Modelling Structures - Tasks and functions
 Task:
a set of procedural statements which are treated
as a sub-unit. Tasks may be invoked from other
procedural blocks, including other tasks.
 Function:
a set of procedural statements whose execution
results in a single value. Functions may be used
as operands in any expression. 54

 To execute common procedures from several different
places in a description.
 For breaking up large procedures into smaller ones to
make it easier to read and debug the source descriptions.
 Input, output, and inout argument values can be passed
into and out of both tasks and functions.
55

Distinctions Between Tasks and Functions:
 A function must execute in one simulation time
unit;
 A task can contain time-controlling statements.
 A function cannot enable a task;
 A task can enable other tasks and functions. 56

Distinctions Between Tasks and Functions:
 A function must have at least one input argument;
 A task can have zero or more arguments of any
type.
 A function returns a single value;
 A task does not return a value. 57

Modelling Structures - Tasks and
functions
 Tasks may only be used in procedural blocks.
 A task invocation, or task enable is a statement by
itself.
 Tasks may not be used as an operand in an
expression.
58

functions
 Functions are used as operands in expressions.
 A function may be used in either a procedural block
or a continuous assignment,
 or indeed, any place where an expression may
appear.
59

functions
Task Enabling
 A task is enabled from a statement that defines
the argument values to be passed to the task and
the variables that will receive the results.
 Control is passed back to the enabling process
after the task has completed.
60

Task Enabling
61
• A task can enable other tasks, which in turn can
enable still other tasks—with no limit on the
number of tasks enabled.
• Regardless of how many tasks have been enabled,
control does not return until all enabled tasks have
completed

Tasks and functions – Tasks (cont.)
Simplified Syntax
task identifier;
parameter_declaration;
input_declaration;
output_declaration;
inout_declaration;
register_declaration;
event_declaration;
statement;
endtask
62

Tasks and functions – Tasks (cont.)
Time can elapse during the execution of a task, according to
time and event controls in the task definition. For example,
task do_read;
input [15:0] addr;
output [7:0] value;
begin
adbus_reg = addr; // put address out
adbus_en = 1; // drive address bus
@(posedge clk); // wait for the next clock
while (~ack)
@(posedge ack); // wait for ack
value = data_bus; // take returned value
adbus_en = 0; // turn off address
bus count = count + 1; // how many have we done
end
endtask
63

Modelling Structures - functions
 Functions must execute in a single instant of
simulated time.
  not time or delay controls are allowed in a
function.
 Function arguments are also restricted to inputs
only.
 Output and inout arguments are not allowed.
 The output of a function is indicated by an
assignment to the function name.
64

65
Simplified Syntax
function type_or_range identifier;
parameter_declaration;
input_declaration;
register_declaration;
event_declaration;
statement;
endfunction

66
For example:
function [15:0] relocate;
input [11:0] addr;
input [3:0] relocation_factor;
begin
relocate = addr + (relocation_factor<<12);
count = count + 1;
end
endfunction

67
// Using inline declaration of the inputs
function integer addition (input integer in_a, in_b);
addition = in_a + in_b; // Return the sum of the two inputs
endfunction : addition
// Declaring the inputs in the function body
function integer addition;
input integer in_a;
input integer in_b;
begin
addition = in_a + in_b; // Return the sum of the two inputs
end
endfunction
// Calling a verilog function
func_out = addition(a, b);

68
We can use the
automatic keyword to
write recursive
functions in verilog.
This means we can
create functions
which call
themselves to
perform a calculation.
module function_auto ();
function automatic [7:0] factorial;
input [7:0] i_Num;
begin
if (i_Num == 1)
factorial = 1;
else
factorial = i_Num * factorial(i_Num-1);
end
endfunction
initial
begin
$display("Factorial of 1 = %d", factorial(1));
end
endmodule

Question
What is wrong with the following function
definition?
function f(x);
input x;
f = ~x[2];
endfunction
a. x should be declared reg.
b. x has the wrong declaration for selecting bit 2.
c. function needs a return type
d. the statement f = ~x[2]; needs to be surrounded by
begin - end.
e. nothing
69

Question
What is wrong with the following function
definition?
function f(x);
input x;
f = ~x[2];
endfunction
a. x should be declared reg.
b. x has the wrong declaration for selecting bit 2.
c. function needs a return type
d. the statement f = ~x[2]; needs to be surrounded by begin
- end.
e. nothing
70
The correct answer is b. x has the
wrong declaration for selecting bit 2

Exercises – Q1
Which one of the following Verilog structures
may occur outside of other structures?
a. modules
b. ports
c. parameters
d. instances
71

Exercises – Q1
Which one of the following Verilog structures
may occur outside of other structures?
a. modules
b. ports
c. parameters
d. instances
72
Of these structures, only modules may
occur outside other structures.

Exercises – Q2
What is wrong with the following module
instantiation?
module modA;
...
modB #(1,2) (p1, p2,, p4);
...
endmodule
a. missing ports are not allowed in instantiations
b. the module instance name is missing
c. the module instance parameter values must be after the
port list
d. nothing
73

Exercises – Q2
What is wrong with the following module
instantiation?
module modA;
...
modB #(1,2) (p1, p2,, p4);
...
endmodule
a. missing ports are not allowed in instantiations
b. the module instance name is missing
c. the module instance parameter values must be after the
port list
d. nothing
74
The correct answer is b. The module
instance name is missing.

Exercises – Q3
Given the following module:
module modB (port1, port2, port3, port4);
input port1, port2;
inout port3;
output port4; ...
parameter par1 = 1, par2 = 2, par3 = par1+par2;
... endmodule
75
a. Legal Illegal modB mb2 (p1, , p3, p4);
b. Legal Illegal modB #(7,8,9,10) mb2 (p1, p2, p3, p4);
c. Legal Illegal modB mb2 (p1, p2, p3);
d. Legal Illegal modB mb2 (p1, p2, p3, );
Indicate whether the following instances of modB
above are legal or illegal.
port 2 không được kết nối, dấu phẩy này vẫn chấp nhận đc
có 4 tham số, nhưng đây chỉ khai báo có 3 tham số dẫn đến số lượng cổng ko
đúng
tương tự câu a

Exercises – Q3
module modB (port1, port2, port3, port4);
input port1, port2;
inout port3;
output port4; ...
parameter par1 = 1, par2 = 2, par3 = par1+par2;
... endmodule
a. Legal Illegal modB mb2 (p1, , p3, p4);
b. Legal Illegal modB #(7,8,9,10) mb2 (p1, p2, p3, p4);
c. Legal Illegal modB mb2 (p1, p2, p3);
d. Legal Illegal modB mb2 (p1, p2, p3, );
These are the correct answers.
76

Exercises – Q4
 Are these two ways of redefining the parameter par2
equivalent?
Yes No
modB #(,5,) mb1 (p1, p2, p3, p4);
and
modB mb1 (p1, p2, p3, p4);
defparam mb1.par2 = 5;
77

Exercises – Q5
 Are these two ways of redefining the parameter par2
equivalent?
Yes No
modB #(,5,) mb1 (p1, p2, p3, p4);
and
modB mb1 (p1, p2, p3, p4);
defparam mb1.par2 = 5;
78
You can't do what this is attempting by means of a module instance
parameter assignment. The defparam is the only way to change the value of
only the second parameter in a module.
Yes No

Exercises – Q5
 Are the following statements syntactically correct?
a. Yes No reg [5] x;
b. Yes No reg #10 x;
79

Exercises – Q5
a. Yes No reg [5] x;
b. Yes No reg #10 x;
80
They're both incorrect.
Here are examples of correct statements:
a. reg[5:1]x;
b. reg x;// can't attach a delay to reg definition

Exercises – Q6
correct?
a. Yes No wire w1; wire [1:0] w2;
b. Yes No wire #10 x;
81

Exercises – Q6
correct?
a. Yes No wire w1; wire [1:0] w2;
b. Yes No wire #10 x;
82
Yes. Both statements are correct.

Exercises – Q7
a. Yes No and #1 a1 (a,b,c), a2 (d,e,f);
b. Yes No buf #10 (o1, in1);
83

Exercises – Q7
a. Yes No and #1 a1 (a,b,c), a2 (d,e,f);
b. Yes No buf #10 (o1,in1);
84
Yes. Both statements are correct.

Exercises – Q8
correct?
a. Yes No initial x #1= f(y);
b. Yes No initial x = #1 f(y);
c. Yes No initial begin x = 1; y = 0; end
85

Exercises – Q8
correct?
a. Yes No initial x #1 = f(y);
b. Yes No initial x = #1 f(y);
c. Yes No initial begin x = 1; y = 0; end
86
Only the first statement is incorrect.
Here are two examples of correct statements for a.:
a. initial #1 x = f(y);
or
b. initial x = #1 f(y);

Exercises – Q9
correct?
a. Yes No function f [1:0] (x);
b. Yes No function f (x[1:0]);
87

Exercises – Q9
correct?
a. Yes No function f [1:0] (x);
b. Yes No function f (x[1:0]);
88
Both statements are incorrect.
Here are examples of correct statements:
a. b. function f; input [1:0]x;

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