ME - applied electronics VLSI UNIT I.ppt

VLSI Design Techniques 2
Outline
 A Brief History
 VLSI Design Process
 Architectural Design
 Logic Design
 Physical Design
 Layout Styles
 Full Custom Design
 Semi Custom Design

A Brief History
 1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas
Instruments
 2010
– Intel Core i7 processor
• 2.3 billion transistors
– 64 Gb Flash memory
• > 16 billion transistors
Courtesy Texas Instruments
[Trinh09]
© 2009 IEEE

Invention of the Transistor
 Vacuum tubes ruled in first half of 20th
century Large,
expensive, power-hungry, unreliable
 1947: first point contact transistor
– John Bardeen and Walter Brattain at Bell Labs
– See Crystal Fire
by Riordan, Hoddeson
AT&T Archives.
Reprinted with
permission.

VLSI Design Techniques
1: Circuits & Layout 5
Transistor Types
 Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration

 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle
 1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
[Vadasz69]
© 1969 IEEE.
Intel
Museum.
Reprinted
with
permission.

Moore’s Law: Then
 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
[Moore65]
Electronics Magazine

And Now…

Feature Size
 Minimum feature size shrinking 30% every 2-3 years

Gajski Y-Chart

VLSI Design Cycle

VLSI Design cycle:
VLSI design cycle start with a formal
specification of a VLSI chip, follows a
series of steps, and eventually produces a
packaged chip.

A simple VLSI design cycle:
1. System Specification
2. Functional design
3. Logic design
4. Circuit design
5. Physical design
6. Fabrication
7. Packaging, Testing and Debugging

VLSI Design Cycle
System Specification
Architectural Design
Architectural Design
Logic Design
Logic Design
Circuit Design
Circuit Design
Physical Design
Physical Design
Functional Design
Functional Design Fabrication
Fabrication
Packaging
Packaging

1. First step of design process is to lay down the specification
of the system.
2. High level representation of the system.
3. Factors considered:
a) Performance
b) Functionality
c) Physical dimension
d) Design technique
e) Fabrication technology
4. It is a compromise between market requirements,
technological and economical viability.

System Specification contd.
The end results are specifications of
1. Size
2. Speed
3. Power and
4. Functionality of the VLSI system
5. Basic architecture of the system are also specified,
such as
a) Floating point unit
b) RISC versus CISC system
c) Number of ALU’s
d) Number and structure of the pipelines
e) Size of the cache, etc.

Functional Design
1. Main functional units of the system are identified
2. Identifies the interconnect requirements
between the units
1. The area, power and other parameters of each unit
are estimated
2. The behavioral aspects of the system are considered
not implementation specification
- multiplication needed but does not specify its
hardware
3. The key idea is to specify behavior, in terms of
a) Input
b) Output
c) Timing of each unit
Without specifying the internal structure.

Functional Design contd.
4. The outcome of functional design is usually a timing
diagram or other relationships between units.
5. This information leads to improvement of the overall
design process and reduction of complexity of the
subsequent phases.
6. Functional design provides a quick emulation of the
system and allows fast debugging of the full system.

Logic Design
Design the logic, that is,
1. Boolean expressions,
2. control flow,
3. word width,
4. register allocation, etc.
The outcome is called an RTL (Register Transfer Level)
description. RTL is expressed in a HDL (Hardware
Description Language), such as VHDL and Verilog.
This description can be used in simulation and
verification.
• As this description consists of Boolean expressions, so
they can be minimized to achieve the smallest logic
design.
X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)

Circuit Design
1. The purpose of the circuit design is to develop a circuit
representation based on the logic design.
2. The Boolean expression can be converted into a circuit
representation by taking into consideration the speed and
power requirements of the original design.
3. Design the circuit including gates, transistors,
interconnections, etc. The outcome is called a netlist.
4. Circuit simulation is used to verify the correctness and
timing of component.

Physical Design
1. The circuit representation of each component is converted into
geometric representation.
2. Convert the netlist into a geometric representation. The
outcome is called a layout.
3. Connections between different components are also expressed
as a geometric pattern.
4. Exact details depends upon design rules
5. It is a complex process and usually broken down
into sub-steps.
6. Various verification and validation checks are performed on the
layout during physical
design.

Fabrication
1. Fabrication: Process includes lithography, polishing,
deposition, diffusion, etc., to produce a chip.
2. Fabrication process consists of several steps and
requires various masks.
3. Before the chip is mass produced, a prototype is
made and tested.

Packaging, Testing and Debugging
1. Packaging – Put together the chips on a PCB
(Printed Circuit Board) or an MCM (Multi-Chip
Module)
2. Each chip is then packaged and tested to
ensure that it meets all the design
specifications and that it functions properly.

VLSI Design Cycle
Architectural
Specification
RTL in HDL
Netlist
Layout
Timing & relationship
between functional units
Chips
Packaged and
tested chips
Architectural
Design
Functional
Design
Logic
Design
Physical
Design
Fabrication
Packaging
Circuit Design
or
Logic Synthesis

Physical Design Cycle
Circuit Partitioning
Floorplanning & Placement
Routing
Layout Compaction
Extraction and Verification
The input of the physical design cycle is a circuit
diagram and the output is the layout of the circuit.

Circuit Partitioning
1. A chip may contain several million transistors.
So layout of the entire circuit can not be
handled due to the limitation of memory space
and computation power available.




Circuit Partitioning contd.
2. Partition a large circuit into sub-circuits
(called blocks).
3. Factors like #blocks, block sizes,
interconnection between blocks, etc., are
considered.
4. The output of partitioning is a set of blocks
and the interconnections between them.
5. Partitioning may be hierarchical.

Floorplanning
• This step is concerned with selecting good layout for each block
as well as the entire chip.
• The area of each block can be estimated after partitioning
based approximately on the number and type of components of
that block.
• Interconnect area between blocks is also considered.
• Done by design engineer rather than CAD tools: human is better
in visualization.
• Certain components are often required to be located at a
specific position on the chip.
Deadspace

Placement
1. The blocks are exactly positioned on the chip.
2. The goal is to minimize the area arrangement for the
blocks that allows completion of interconnections between
the blocks while meeting the performance constraints.
For example: routable blocks but fails timing goals.
Feedthrough
Standard cell type 1
Standard cell type 2
v

Placement contd.
1. Two phases: initial placement is created in the first phase.
In second phase, initial placement is evaluated and
iterative improvements are made until the layout has
minimum area.
2. Quality of placement will not be evident until the routing
phase has been completed. Placement may lead to an un
routable design: More space may be needed.
3. Good routing and circuit performance heavily depends on a
good placement algorithm.
4. This is due to the fact that after the position of the
block has been fixed, routing can do nothing.

Routing
1. Objectives is to complete the interconnections between
modules.
2. Routing space is partitioned into channels and
switchboxes.
3. Two phases : global routing and detailed routing.
Feedthrough
Type 1 standard cel1
Type 2 standard cell
v

Global routing (GR)
1. In global routing, connections are completed between
proper blocks of the circuit disregarding exact
geometric details of each wire and pin.
2. For each wire GR finds a lists of channels which are to
be used as a passageways for that wire. In other
words, GR specifies different regions in the routing
space through which a wire should be routed.
Detailed routing (DR)
•DR completes point-to-point connections between pins on
the blocks. GR is converted into exact routing by specifying
geometric information such as location and spacing of wires
and their layer assignments.
•It includes channel and switchbox routing.

Compaction & Verification
Compaction – Compress the layout from all directions to
minimize the total chip area. Advantages:
1. Making chip smaller, wire lengths are reduced.
2. Reduces signal delays.
3. More chip on a small area, so manufacturing cost
reduced.
But should ensure design rules.
Verification – Check the correctness of the
layout. Include DRC (Design Rule Checking),
circuit extraction (generate a circuit from the
layout to compare with the original netlist),
performance verification, reliability
verification.

Review – Physical Design
 The final physical layout of a complicated circuit on a small piece
of silicon is generated in a set of steps using CAD tools
Partitioning
Placement/
Floorplanning
Routing
Break the circuit
up into smaller
segments
Place the segments
on the chip
Layout out the
wire paths
K-L and F-M Algorithms
K-L and F-M Algorithms
Constructive &
Constructive &
K-L Algorithms
K-L Algorithms

Over View of Physical Design

Physical Design Style

Why Design Style?
Physical design is an extremely complex process and
even after breaking the entire process into several easier
steps.
Each step is computationally very hard .
Market requirements demand quick time-to-market and
high yield.
As a result, restricted models and design styles are used
to reduce the complexity of physical design.

Comparison
Style
Style
Full-custom
Full-custom Standard cell
Standard cell Gate Array
Gate Array FPGA
FPGA
Area
Area Compact
Compact Compact to
Compact to
moderate
moderate
Moderate
Moderate Large
Large
Performance
Performance High
High High to moderate
High to moderate Moderate
Moderate Low
Low
Fabrication
Fabrication All layers
All layers All layers
All layers Routing
Routing
layers only
layers only
No layers
No layers

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