![Approved for Public Release, Distribution UnlimitedT21.1
Bandwidth/Power Challenges
• Host-to-Memory challenges
– “… future many-core processors will require the
introduction of optical interconnect.” Ref[1]
• DDR4 successor?
– DDR5? … no JEDEC Task Group
– Hybrid Memory Cube
– In-Package-Memory (e.g. WIO, HBM, etc.)
• Photonic Interconnect?
– Power and Bandwidth?
– Cost? Bulk CMOS!
Slide 2
REF[1]: Ian Young, "Optical I/O Technology for Tera-Scale Computing", IEEE JOURNAL OF SOLID-STATE CIRCUITS,
VOL. 45, NO. 1, JANUARY 2010](https://image.slidesharecdn.com/fb43ea80-a9f4-45da-a948-6ab4c23db866-150907213211-lva1-app6891/85/Meade_presentation_T21p1_VLSI_2014-3-320.jpg)
![Approved for Public Release, Distribution UnlimitedT21.1
Bulk CMOS/Polysilicon Loss Mechanisms
• Evanescent coupling to substrate
– Proximity of additional modes
• High attenuation in polysilicon waveguides
– “Simple” polysilicon waveguides 9-15 dB/cm Ref[1]
– Integrated polysilcion waveguides > 60 dB/cm
Slide 12
Ref[1]: L. Liao, et al, “Optical Transmission Losses in Polycrystalline Silicon Strip Waveguides: Effects of
Waveguide Dimensions, Thermal Treatment, Hydrogen Passivation, and Wavelength”, Journal of Electronic
Materials, Vol. 29, No. 12, 2000](https://image.slidesharecdn.com/fb43ea80-a9f4-45da-a948-6ab4c23db866-150907213211-lva1-app6891/85/Meade_presentation_T21p1_VLSI_2014-13-320.jpg)
![Approved for Public Release, Distribution UnlimitedT21.1
Bulk CMOS/Polysilicon Loss Mechanisms
• Evanescent coupling to substrate
– Proximity of additional modes
• High attenuation in polysilicon waveguides
– “Short Flow” polysilicon waveguides 9-15 dB/cm Ref[1]
– Integrated polysilicon waveguides > 60 dB/cm
Slide 18
Ref[1]: L. Liao, et al, “Optical Transmission Losses in Polycrystalline Silicon Strip Waveguides: Effects of
Waveguide Dimensions, Thermal Treatment, Hydrogen Passivation, and Wavelength”, Journal of Electronic
Materials, Vol. 29, No. 12, 2000](https://image.slidesharecdn.com/fb43ea80-a9f4-45da-a948-6ab4c23db866-150907213211-lva1-app6891/85/Meade_presentation_T21p1_VLSI_2014-19-320.jpg)
![Approved for Public Release, Distribution UnlimitedT21.1
Factors Affecting Polysilicon WG Loss
• Line Width Roughness
– Side wall scattering
• Silicon Nitride absorption
– PECVD Silicon Nitride loss >20 dB/cm Ref[1]
– PECVD Silicon Nitride Slab mode (this work) ~ 20 dB/cm
Slide 22
Ref[1]: D. Sparacin, et al, "Low Loss Amorphous Silicon Channel Waveguides for Integrated Photonics", 3rd IEEE
International Conference on Group IV Photonics, 2006](https://image.slidesharecdn.com/fb43ea80-a9f4-45da-a948-6ab4c23db866-150907213211-lva1-app6891/85/Meade_presentation_T21p1_VLSI_2014-23-320.jpg)
![Approved for Public Release, Distribution UnlimitedT21.1
Bulk CMOS Compatible Photodetector
Slide 29
Ref[1]: K.K. Mehta, et al, “Polycrystalline silicon ring resonator photodiodes in a bulk CMOS
process”, Optics Letters, Vol. 39, Issue 4, pp. 1061-1064 (2014)
Ref: C. Sun, et al, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS”,
VLSI Circuits, 2014 . Digest of Technical Papers, 2014 Symposium on. 2014
Ref[1]](https://image.slidesharecdn.com/fb43ea80-a9f4-45da-a948-6ab4c23db866-150907213211-lva1-app6891/85/Meade_presentation_T21p1_VLSI_2014-30-320.jpg)
Meade_presentation_T21p1_VLSI_2014
- 1. Symposia on VLSI Technology and Circuits Integration of Silicon Photonics in Bulk CMOS Roy Meade, Jason S. Orcutt1,†, Karan Mehta1, Ofer Tehar- Zahav3,*, Daniel Miller3,*, Michael Georgas1, Ben Moss1, Chen Sun1, Yu-Hsin Chen1, Jeffrey Shainline2,**, Mark Wade2, Reha Bafrali, Zvi Sternberg3,*, Galina Machavariani3, Gurtej Sandhu, Milos Popović2, Rajeev Ram1, Vladimir Stojanović1,4 Micron Technology, Inc. Process R&D, Boise, ID, USA 1 Dept. of Electrical Engineering, Massachusetts Institute of Technology, Cambridge, MA 2 Department of Electrical Engineering, University of Colorado at Boulder, Boulder, CO, USA 3 Micron Semiconductor Israel, Kiryat-Gat, Israel 4 University of California, Berkeley, Berkeley, CA, USA This work was supported in part by DARPA under contract HR0011-11-9-0009. The views expressed are those of the author and do not reflect the official policy or position of the Department of Defense or the U.S. Government. Approved for Public Release, Distribution Unlimited
- 2. Approved for Public Release, Distribution UnlimitedT21.1 Acknowledgements • Micron Technology: Emanuele Baracchi, Miri Baruch, Erez Conforti, Paul Daley, Eyal Friedman, Harel Frish, Dana Haran, Lilach Makrabi, Efraim Megged, Maxim Rabinovitch, Matt Ross, Yoel Shetrit • MIT: Michael Watts, Jonathan Leu, Hanqing Li, Erman Timurdogan, Stevan Urosevic, Josh Wang • UC Boulder: Kareem Nammari • UC Berkeley: Krste Asanović, Yunsup Lee, Miquel Planas • DARPA: Jag Shah Slide 1
- 3. Approved for Public Release, Distribution UnlimitedT21.1 Bandwidth/Power Challenges • Host-to-Memory challenges – “… future many-core processors will require the introduction of optical interconnect.” Ref[1] • DDR4 successor? – DDR5? … no JEDEC Task Group – Hybrid Memory Cube – In-Package-Memory (e.g. WIO, HBM, etc.) • Photonic Interconnect? – Power and Bandwidth? – Cost? Bulk CMOS! Slide 2 REF[1]: Ian Young, "Optical I/O Technology for Tera-Scale Computing", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 1, JANUARY 2010
- 4. Approved for Public Release, Distribution UnlimitedT21.1 Example Silicon Photonics Programs Slide 3 5 Gbps eye
- 5. Approved for Public Release, Distribution UnlimitedT21.1 Photonics in Bulk CMOS Slide 4 Array Periphery DDR3-1333 Technology 2 Gb die cost ~90¢ Key constraints: Bulk Substrate Low Cost No exotic mat’l Meade et al. OIC 2013
- 6. Approved for Public Release, Distribution UnlimitedT21.1 Monolithic Silicon Photonics and CMOS Features: • 5 Gb/s link • CMOS – 5M transistors • 2.8 pJ/b (CMOS only) Slide 5
- 7. Approved for Public Release, Distribution UnlimitedT21.1 SiPh Development Environment • “Periphery” bulk CMOS of NOR process – FEOL: Medium Voltage Transistors (Vdd = 1.8 V) – BEOL: 3 Metal Layers – Libraries • SPICE/Compact Models • Standard Cell library • Silicon Photonics additions – Integrated PDK and Design Rule Manual – SiPh Design Rule Check (DRC) – SiPh Optical Proximity Correction rules Slide 6 No Shift in CMOS!
- 8. Approved for Public Release, Distribution UnlimitedT21.1 Cadence Virtuoso Photonic Paramertized Cell • Deployed on 8 tape-outs, 4 separate processes Slide 7
- 9. Approved for Public Release, Distribution UnlimitedT21.1 Optical Proximity Correction • Optical proximity correction routines for CMOS adapted for SiPh structures • As-fab’d SEM structures confirm routines Slide 8 Mask Drawn
- 10. Approved for Public Release, Distribution UnlimitedT21.1 Silicon Photonic Building Blocks Slide 9 On-Chip Off-Chip Source: MIT PhotodetectorWDM Filter Source: MIT/Micron Vertical Coupler Source: MIT/Micron Modulator Source: MIT Laser Source: Intel Package Source: Intel
- 11. Approved for Public Release, Distribution UnlimitedT21.1 Photonic Devices • Passive Devices – Waveguides – Grating Couplers – Etc. • Active Devices – Modulators – Photodetectors – Etc. Slide 10
- 12. Approved for Public Release, Distribution UnlimitedT21.1 Polysilicon as Waveguiding Material Slide 11 Alternatives? Bulk CMOS Higher WG Attenuation Polysilicon WG’s
- 13. Approved for Public Release, Distribution UnlimitedT21.1 Bulk CMOS/Polysilicon Loss Mechanisms • Evanescent coupling to substrate – Proximity of additional modes • High attenuation in polysilicon waveguides – “Simple” polysilicon waveguides 9-15 dB/cm Ref[1] – Integrated polysilcion waveguides > 60 dB/cm Slide 12 Ref[1]: L. Liao, et al, “Optical Transmission Losses in Polycrystalline Silicon Strip Waveguides: Effects of Waveguide Dimensions, Thermal Treatment, Hydrogen Passivation, and Wavelength”, Journal of Electronic Materials, Vol. 29, No. 12, 2000
- 14. Approved for Public Release, Distribution UnlimitedT21.1 Dual Trench Isolation – Step #1-2 Slide 13 Hard Mask and Polish-Stop Formation + STI Mask Level Lithography Trench Etch for Both Shallow and Deep Trench Isolation
- 15. Approved for Public Release, Distribution UnlimitedT21.1 Dual Trench Isolation – Step #3-4 Slide 14 DTI Mask Level Lithography Extra Etch for Deep Trench Isolation (Photonic Region Only)
- 16. Approved for Public Release, Distribution UnlimitedT21.1 Dual Trench Isolation – Step #5-6 Slide 15 Oxide Trench Fill for Both Shallow and Deep Trenches Oxide CMP to Stop on Nitride Polish Stop
- 17. Approved for Public Release, Distribution UnlimitedT21.1 SEM Cross Section of Deep Trench Isolation Slide 16 • DTI deployed • Allows for Wafer Level Test (WLT) • HVM compatible DTI adjacent to STI Narrow Pitch DTI
- 18. Approved for Public Release, Distribution UnlimitedT21.1 Planar View (GDS/SEM) SiPh Waveguides Slide 17 3 dB Coupler Serpentine WG
- 19. Approved for Public Release, Distribution UnlimitedT21.1 Bulk CMOS/Polysilicon Loss Mechanisms • Evanescent coupling to substrate – Proximity of additional modes • High attenuation in polysilicon waveguides – “Short Flow” polysilicon waveguides 9-15 dB/cm Ref[1] – Integrated polysilicon waveguides > 60 dB/cm Slide 18 Ref[1]: L. Liao, et al, “Optical Transmission Losses in Polycrystalline Silicon Strip Waveguides: Effects of Waveguide Dimensions, Thermal Treatment, Hydrogen Passivation, and Wavelength”, Journal of Electronic Materials, Vol. 29, No. 12, 2000
- 20. Approved for Public Release, Distribution UnlimitedT21.1 Polysilicon WG Formation Slide 19
- 21. Approved for Public Release, Distribution UnlimitedT21.1 Polysilicon X-Ray Diffraction Slide 20 Amorphous Si + Anneal Poly-Si + Anneal Poly-Si + Implant + Anneal 2θ, ()
- 22. Approved for Public Release, Distribution UnlimitedT21.1 Confinement Factor Scaling Slide 21 Attenuation,(dB/cm) 35 30 25 20 15 10 Waveguide Width, (nm) 0 500 1000 1500 2000
- 23. Approved for Public Release, Distribution UnlimitedT21.1 Factors Affecting Polysilicon WG Loss • Line Width Roughness – Side wall scattering • Silicon Nitride absorption – PECVD Silicon Nitride loss >20 dB/cm Ref[1] – PECVD Silicon Nitride Slab mode (this work) ~ 20 dB/cm Slide 22 Ref[1]: D. Sparacin, et al, "Low Loss Amorphous Silicon Channel Waveguides for Integrated Photonics", 3rd IEEE International Conference on Group IV Photonics, 2006
- 24. Approved for Public Release, Distribution UnlimitedT21.1 2 µm Wide Waveguide Attenuation (EOL) Slide 23 Type LPCVD PECVD 1 2 3 4 5 6 7 16 178 9 10 11 12 13 14 15 Wafer Number
- 25. Approved for Public Release, Distribution UnlimitedT21.1 Blanket Polysilicon Attenuation • Instrument: Metricon – ~ 1.8 dB/cm blanket – < 10 dB/cm integrated? Slide 24 1.83 dB/cm Exponential Fit Line @ λ = 1.55 μm Probe Position (cm) ScatteredLight(a.u.) wafer under test scattered light probe prism
- 26. Approved for Public Release, Distribution UnlimitedT21.1 Grating Fiber-to-Chip Couplers Slide 25 Orcutt et al., Opt. Express 2012. Wade et al., CLEO 2014. Luxtera: Gunn et al., IEEE Micro 2005. Symmetric grating in standard IBM 45nm SOI CMOS (Colorado/MIT/Berkeley) Angled Output to Fiber Input U. Colorado: M. Fan et al., CLEO 2007. Asymmetric, 2-level gratings enable directed light radiation
- 27. Approved for Public Release, Distribution UnlimitedT21.1 Partial Polysilicon Etch for Grating Couplers Slide 26
- 28. Approved for Public Release, Distribution UnlimitedT21.1 Photonic Devices • Passive Devices – Waveguides – Grating Couplers – Etc. • Active Devices – Modulators – Photodetectors – Etc. Slide 27
- 29. Approved for Public Release, Distribution UnlimitedT21.1 Bulk CMOS Compatible Modulators Slide 28 5 Gbps Tx Eye Diagram (x5, x15) J.M. Shainline, et al, "Depletion-mode polysilicon optical modulators in a bulk CMOS process", Optics Letters, Vol. 38, Issue 15, pp. 2729-2731 (2013)
- 30. Approved for Public Release, Distribution UnlimitedT21.1 Bulk CMOS Compatible Photodetector Slide 29 Ref[1]: K.K. Mehta, et al, “Polycrystalline silicon ring resonator photodiodes in a bulk CMOS process”, Optics Letters, Vol. 39, Issue 4, pp. 1061-1064 (2014) Ref: C. Sun, et al, “A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS”, VLSI Circuits, 2014 . Digest of Technical Papers, 2014 Symposium on. 2014 Ref[1]
- 31. Approved for Public Release, Distribution UnlimitedT21.1 Silicon-Germanium Absorption (Relaxed) Slide 30 1 10 100 1000 1000 1100 1200 1300 1400 1500 1600 AbsorptionCoefficient(1/cm) Wavelength (nm) Ref: “Properties of Silicon Germanium and SiGe-Carbon” AMIS Dataseries parameterization of Herman 1958 100% (Ge) 0% (Ge) 10% 20% 30% 50% 75%
- 32. Approved for Public Release, Distribution UnlimitedT21.1 Silicon-Germanium Vertical Photodetector Slide 31 P+ N+ i
- 33. Approved for Public Release, Distribution UnlimitedT21.1 Selective Epitaxial Growth Slide 32 Ox c-Si Poly-Si
- 34. Approved for Public Release, Distribution UnlimitedT21.1 SiGe – Selective Epitaxial Growth Slide 33 Ref: Douglas J Paul, "Silicon-Germanium Strained Layer Materials in Microelectronics", Advanced Materials 11(3), 191-204 (1999) • 30% and 45% SiGe grown • Both films relax • Dark current acceptable c-SiSiGe (45%)
- 35. Approved for Public Release, Distribution UnlimitedT21.1 45% SiGe 1st Photoresponse Data • 5 µm width • 100 µm length • 0.03 A/W at 1280nm • < 1 µA dark current Slide 34 -3 -2 -1 0 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 Voltage (V) Current(A) 1 mW (in waveguide) λ=1240nm Dark 45% SiGe PolySi p+ p+ n+ Sin+ Si n Si Bias Responsivity 0 V 0.070 0.5 V 0.072 1.0 V 0.074 3.0 V 0.081
- 36. Approved for Public Release, Distribution UnlimitedT21.1 Conclusion • 1st Monolithic Bulk CMOS + SiPh process! – CMOS fully functional (5M transistors) – Functional Active and Passive Photonic Devices • SiGe Photodetector Demonstrated • Working photonic link on bulk CMOS – 5 Gbps @ ~3 pJ/b (CMOS only) – Wavelength Division Multiplexing compatible • Fully Polysilicon Transceiver Platform Demonstrated! – 1st non-epitaxial silicon photonic process Slide 35