microelectronics-6ed-ch8-ppt-2025-spring

Microelectronic Circuits II
Differential and Multistage Amplifiers
Chia-Ming Tsai
NYCU
Department of Electrical Engineering

Outlines
• MOS Differential Pair
• BJT Differential Pair
• Common-Mode Rejection
• DC Offset
• Differential Amplifier With A Current-Mirror Load
• Multistage Amplifiers

What To Learn
• The essence of the operation of the MOS / BJT differential
amplifiers :
– Amplify differential signals
– Reject common-mode noise or interference
• The analysis and design of MOS and BJT differential amplifiers.
• Differential-amplifier circuits of varying complexity, using passive
resistive loads, current-source loads, and cascodes.
• Multi-stage amplifiers composed of two or more stages in
cascade.
– Two-stage CMOS op amp
– Four-stage bipolar op amp

Introduction
• The differential-pair or differential-amplifier configuration is the
most widely used building block in analog integrated-circuit
design.
– For instance, the input stage of every op amp is a differential
amplifier.
– Also, the BJT differential amplifier is the basis of a very-high-
speed logic-circuit family, called emitter-coupled logic (ECL).
• Initially invented in the 1940s for use with vacuum tubes, the
basic differential-amplifier configuration was subsequently
implemented with discrete bipolar transistors.
• However, it was the advent of integrated circuits (ICs) that has
made the differential pair extremely popular in both bipolar and
MOS technologies.

Single-Ended Amplifiers
• Pros : simple, low-power, low-cost …
• Cons : very sensitive to supply noise and environmental noise

Differential Amplifiers
• Advantage : better immunity to supply noise and environmental
noise

Single-Ended vs. Differential Signaling
• A single-ended signal is defined as one that is measured with respect to a
fixed potential.
• A differential signal is defined as one that is measured between two nodes.
• Common-mode level : the center potential in difference signaling.
Single-ended signal Differential signal

Single-Ended vs. Differential Signaling
• Reduction of coupled noise by using differential operation (clock noise
cancellation)
• Differential signaling : increase the maximum achievable voltage swings.
The peak to peak swing is equal to twice that of a single-ended signal.
– Example :
• Single-ended :
• Differential :
t
Vo 
sin
1

t
V
V
t
V
t
V o
o
o
o 

 sin
2
sin
1
sin
1 



 




The MOS Differential Pair
2
,
voltage)
mode
-
(common 2
1
2
1
I
i
i
V
V
V
V
v
v D
D
GS
CM
S
CM
G
G 






• Assume Q1 and Q2 are perfectly-matched and operated in saturation region.
• An ideal current source with Rout =  is assumed.
 
 
L
W
k
I
V
V
L
W
k
V
V
L
W
k
I
V
V
V
n
OV
OV
n
t
GS
n
t
GS
OV
/
,
2
1
2
1
2
,
voltage
overdrive
Let '
2
'
2
'


















Common-mode operation

VCM = 0 V VCM = 1 V
VCM = -0.2 V

Input Common-Mode Range
• It’s the range of VCM over which
the differential pair operates
properly.
• The highest VCM is limited by the
requirement that Q1 and Q2
remain in saturation.
• The lowest VCM is determined by
the need for a sufficient voltage
VCS across current source I for it
to operate properly.
t
D
DD
t
D
CM
D
DD
D
D
D
V
R
I
V
V
V
V
R
I
V
V
V
V









2
2
max
2
1
OV
t
CS
SS
GS
CS
SS
CM
CS
SS
GS
CM
V
V
V
V
V
V
V
V
V
V
V
V













min
)
(

• If vid is increased beyond vidmax, iD1
remains equal to I.
• The range of differential-mode operation:
the current I can be steered from one
transistor to the other by varying vid in the
range :
Operation with a Differential Input Voltage
2
1 GS
GS
id v
v
v 

 
 
OV
t
OV
t
S
GS
id
OV
t
n
t
GS
t
GS
'
n
D
t
S
V
V
V
V
v
v
v
V
V
L
W
k
I
V
v
I
V
v
L
W
k
i
V
v
2
2
2
/
/
2
2
1
off)
cut
(Q
1
max
'
1
2
1
1
2




















 OV
t
GS V
V
V 2
1 

OV
id
OV V
v
V 2
2 


• Differential input voltage :
• If the current I is fully switched to Q1 and
Q2 is cutoff. (@A)
Bias point
A

Large-Signal Operation
 
 2
2
'
2
2
1
'
1
2
1
2
1
(I)
t
GS
n
D
t
GS
n
D
V
v
L
W
k
i
V
v
L
W
k
i



  
 
t
GS
n
D
t
GS
n
D
V
v
L
W
k
i
V
v
L
W
k
i




2
'
2
1
'
1
2
1
2
1
(II)
(1)
...
2
1
(III)
'
2
1
2
1
2
1
id
n
D
D
id
G
G
GS
GS
v
L
W
k
i
i
v
v
v
v
v






 
 
L
W
k
I
v
v
I
L
W
k
I
i
L
W
k
I
v
v
I
L
W
k
I
i
n
id
id
n
D
n
id
id
n
D
'
2
'
2
'
2
'
1
/
2
/
1
2
2
/
2
/
1
2
2
(V)


















1
2
2
'
2
1
2
1
2
1
2
(2)
...
(IV)
D
D
id
n
D
D
D
D
i
I
i
v
L
W
k
I
i
i
I
i
i







Comparison of Linear Range
m
id
OV
id
D
m
id
OV
id
D
OV
id
g
v
I
V
I
v
I
i
g
v
I
V
I
v
I
i
V
v


















































2
2
2
2
,
2
2
2
2
2
If 2
1
OV
OV
D
m
D
D
id
V
I
V
i
g
I
i
i
v 




 1
2
1
2
,
2
0
As
• At the bias (quiescent) point :
• For small-signal operation (linear region) :
• The linearity can be increased by increasing the overdrive voltage VOV
(use smaller W/L), but at the expense of reducing gm (gain).
2
2
2
1
2
'
2
/
1
2
2
2
/
1
2
2
point)
bias
(at
2
1
2

























































OV
id
OV
id
D
OV
id
OV
id
D
OV
n
V
v
V
I
v
I
i
V
v
V
I
v
I
i
V
L
W
k
I
Bias point

Small-Signal Operation : Differential Gain
• The common-mode voltage : VCM
– It is needed to set the dc voltage of the MOSFET gates.
– Typically VCM is at the middle value of the power supply.
• The differential input signal : vid
• This would be the case, for instance, if the differential amplifier were fed from the
output of another differential-amplifier stage.

Differential Gain
• From the symmetry of the circuit and the balanced manner in which vid is applied, the
signal voltage at the joint source connection must be zero, acting as a sort of virtual
ground.
• Assume vid/2 << VOV (The small-signal approximation can be applied.)
• One advantage of taking the output differentially is an increase in gain by a factor of 2
(6dB).
Differential gain :
For ro = .
Virtual
ground

Differential Gain
An alternative view of the small-signal differential
operation of the differential pair
Differential half circuit

Effect of the MOSFET’s ro
• By the virtual ground assumption, using the differential half circuit
• The differential gain is the same as that of a single-stage CS amplifier.
     v
r
R
g
v
v
v
v
r
R
g
v
v
r
R
g
v id
o
D
m
o
o
o
id
o
D
m
o
id
o
D
m
o ||
2
||
2
|| 1
2
2
1 






o
D
Deff r
R
R ||


BJT Differential Pair
Input Data = 1 Input Data = 0

Input Common-Mode Range
• The upper end of VCM is determined
by Q1 and Q2 leaving the active
mode and entering saturation.
Thus,
• The lower end of the VCM range is
determined by the need to provide a
certain minimum voltage VCS across
the current source I to ensure its
proper operation. Thus,

Transfer characteristics of the BJT differential pair assuming α  1.
• The linear region of the emitter coupled pair is less than 4VT, which is much smaller
than that for the MOS pair, .
OV
V
2

Improved Linearity by Emitter Degeneration
• The linear range of the emitter coupled pair can be extended by using
degeneration resistor Re, but at the expense of smaller gain (gmeff).
This technique can also be applied to MOS differential pair.

• Assume the current source is ideal, (output resistance is infinite)
• Input differential resistance
e
m
m
meff
id
meff
e
e
id
c
e
e
id
e
e
id
m
e
id
e
c
e
id
e
T
E
T
e
e
R
g
g
g
v
g
R
r
v
i
R
r
v
i
R
v
g
r
v
i
i
r
v
i
I
V
I
V
r
R














1
2
2
2
2
2
:
With
2
2
2
2
/
:
Without



e
e
e
b
id
id
e
id
m
e
id
e
c
e
b
id
id
e
id
e
b
e
R
r
R
r
i
v
R
R
v
g
r
v
i
i
r
r
i
v
R
r
v
i
i
R
1)
(
2
2
)
2
1)(2
(
:
With
2
2
2
1)2
(
1
2
/
1
:
Without



























An Alternative Viewpoint

The Differential Half-Circuit
• The differential signal
vid is applied in a
complementary (push-
pull or balanced)
manner.
• From symmetry, it
follows that the signal
voltage at the emitters
will be zero (virtual
ground).
• Note that the finite
output resistance REE
of the current source
will have no effect on
the operation.
Differential half-circuit

Differential Amp. with Current Source Load
• To obtain higher gain, the passive resistances (RD) can be replaced with
current sources.
)
||
( 3
1
1 o
o
m
d r
r
g
A 

Cascode Configuration
2
id
m
v
g

2
id
C
m
v
R
g

 o
R
2
id
m
v
g
2
id
v

Cascode Differential Amplifier
• Gain can be increased via cascode configuration.
1
3 3 1
5 5 7
( )
( )
( )
od
d m on op
id
on m o o
op m o o
v
A g R R
v
R g r r
R g r r
 



   
cmd
d
cmd
d
d
d
cmd
d
d
cm
cm
id
d
icm
cmd
id
A
d
d
icm
A
cm
cm
id
d
icm
cm
id
d
icm
cm
o
o
o
id
icm
d
cm
d
cm
id
icm
o
o
id
icm
id
icm
A
A
A
A
A
A
A
A
A
A
A
v
A
v
A
v
A
A
v
A
A
v
A
v
A
v
A
v
A
v
v
v
v
v
A
A
A
A
v
v
A
A
A
A
v
v
A
A
A
A
v
v
v
v
v
v
v
v
d
cmd
log
20
CMRR
or
CMRR
by
defined
is
(CMRR)
ratio
rejection
mode
-
common
The
0
have
we
amplifier,
al
differenti
matched
a
For
2
2
2
2
2
1
1
1
1
have
we
ion,
superposit
By
2
2
dB
1
2
1
2
1
2
1
2
1
2
2
1
1
2
1
2
2
1
1
22
21
12
11
2
1
22
21
12
11
2
1
2
1














































































































Common-Mode Rejection Ratio (CMRR)

Common-Mode Rejection Ratio (CMRR)
R
g
R
v
v
v
v
SS
m
D
icm
o
icm
o
2
1
2
1




R
R
v
v
v
v
SS
D
icm
o
icm
o
2
2
1




• Let Vicm represents a disturbance
of interference signal that is
coupled to both input terminals.
• CM half circuit :
• Usually,
• If the output of the differential pair is taken single-endedly :
• If the output of the differential pair is taken differentially :
(poor)
2
1
|
|
2
|
|
,
,
,
, SS
m
SE
cm
SE
d
SE
D
m
SE
d
SS
D
SE
cm R
g
A
A
CMRR
R
g
A
R
R
A 



(perfect)
|
|
0 1
2
1
2









cmd
d
D
m
id
o
o
d
icm
o
o
cmd
A
A
CMRR
R
g
v
v
v
A
v
v
v
A
m
SS g
R 1

CM half circuit

Effect of RD Mismatch on CMRR
 
D
D
SS
m
cmd
d
D
m
d
SS
D
icm
o
o
cmd
icm
SS
D
o
o
icm
SS
D
D
o
icm
SS
D
o
SS
icm
d
d
SS
icm
d
d
icm
s
SS
m
SS
s
d
d
SS
d
d
s
R
R
R
g
A
A
R
g
A
R
R
v
v
v
A
v
R
R
v
v
v
R
R
R
v
v
R
R
v
R
v
i
i
R
v
i
i
v
v
R
g
R
v
i
i
R
i
i
v










































2
CMRR
,
2
2
2
2
2
,
1
If
1
2
1
2
2
1
2
1
2
1
2
1
2
1
RD RD+RD
gm gm
Neglect ro effect

Effect of gm Mismatch on CMRR
 
 
m
m
SS
m
cmd
d
D
m
d
SS
m
D
m
cmd
icm
SS
m
D
m
D
d
D
d
o
o
m
m
m
m
m
m
SS
m
icm
m
d
SS
m
icm
m
d
SS
icm
d
d
icm
s
SS
m
m
m
d
d
gs
gs
SS
s
d
d
SS
d
d
s
g
g
R
g
A
A
R
g
A
R
g
R
g
A
v
R
g
R
g
R
i
R
i
v
v
g
g
g
g
g
g
R
g
v
g
i
R
g
v
g
i
R
v
i
i
v
v
R
g
g
g
i
i
v
v
R
v
i
i
R
i
i
v
















































2
CMRR
,
2
2
2
e
wher
2
2
,
1
If
1
2
1
2
2
1
2
1
2
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
 RD RD
gm1 gm2
Neglect ro effect

Example 8.4
   
  (Good)
m
89
.
0
5
47
.
4
V
47
.
4
k
36
.
22
M
1
m
2
mA/V
2
2
.
0
2
.
0
m
2
2
.
for
source
current
cascode
a
Use
:
2
Case
large)
(Very
m
40
5
200
V,
200
M
1
10
2
.
for
source
current
simple
a
Use
:
1
Case
M
1
02
.
0
2
10
2
CMRR
mA/V
1
2
.
0
1
.
0
m
2
)
2
/
(
2
2
CMOS
m
0.18
for
m
V/
5
4.
rs
transisto
all
for
V
2
.
0
3.
A
200
2.
2%.
is
Q
of
ratios
/
between
mismatch
The
1.
:
ts
Requiremen
dB.
100
of
CMRR
a
achieve
to
have
we
amplifier,
al
differenti
MOS
a
For
2
,
,
4
-
1
5
1
1
1
1
1,2

















































 










A
A
A
A
o
o
o
o
I
m
SS
OV
I
m
A
A
A
A
A
o
SS
SS
SS
m
m
m
SS
m
OV
OV
D
m
A
OV
V
V
L
V
I
V
r
r
r
r
g
R
V
I
g
I
V
V
L
V
L
V
I
V
r
R
I
R
R
g
g
g
R
g
V
I
V
I
g
V
V
I
L
W

CMRR for The BJT Case
R
r
R
v
v
v
v
EE
e
C
icm
o
icm
o
2
2
1





R
R
v
v
v
v
EE
C
icm
o
icm
o
2
2
1




• Let vicm represents a disturbance of
interference signal that is coupled
to both input terminals.
• CM half circuit :
• Usually,
• If the output of the differential pair is taken single-endedly
• If the output of the differential pair is taken differentially
EE
m
SE
cm
SE
d
SE
C
m
SE
d
SS
C
SE
cm R
g
A
A
CMRR
R
g
A
R
R
A 



,
,
,
,
2
1
|
|
2
|
|









cmd
d
C
m
id
o
o
d
icm
o
o
cmd
A
A
CMRR
R
g
v
v
v
A
v
v
v
A |
|
0 1
2
1
2
CM half-circuit
r
R e
EE 
 and
1


CMRR for The BJT Case
• Any mismatch between the two sides of the differential amplifier will result in vod
acquiring a component proportional to vicm.
• For example, a mismatch RC between the two collector resistances results in
• Since α  1, re << 2REE, it can be approximated and written in the form
• The common-mode rejection ratio can now be found as
• Thus, to obtain a high CMRR, we design the current source to have a large output
resistance REE and strive for close matching of the collector resistances.
C
m
d R
g
A 

Input Offset Voltage of the MOS Differential Pair
• Consider the basic MOS differential amplifier with both inputs grounded,
practical circuits exhibit mismatches that result in a DC output voltage Vo.
• Output offset voltage : Vo (@ Vi1 = Vi2 )
• Input offset voltage : VOS = Vo/Ad (Vo divided by the differential gain of the
amplifier Ad )
• If we apply a voltage (–VOS) between the input terminals of the differential
amplifier, then the output voltage will be reduced to zero.

Input Offset Voltage of MOS Differential Pair
• Three factors contribute to the input offset voltage of the
MOS differential pair
– Mismatch in load resistances RD
– Mismatch in (W/L) ratios (or transconductance parameters kn,p)
– Mismatch in threshold voltages Vt

Input Offset Voltage (1)
• Consider mismatch in load resistance RD
• Consider a differential pair in which the two transistors are operating at
VOV = 0.2 V, and each drain resistance is accurate to within 1%. We have







 










































 








 

















D
OV
D
m
D
V
o
OS
D
D
D
o
OV
OV
m
D
D
DD
D
D
D
DD
D
D
D
D
D
D
D
R
R
V
R
g
R
I
A
V
V
R
I
V
V
V
V
I
V
I
g
R
R
I
V
V
R
R
I
V
V
R
R
R
R
R
R
2
2
2
2
2
2
2
2
2
2
1
1
2
D
2
1
2
1
mV
V
R
R
OS
D
D
2
02
.
0
1
.
0
02
.
0 1 






• Consider the effect of a mismatch in (W/L) ratios :
)
/
(
)
/
(
2
/
)
/
(
)
/
(
2
2
)
/
(
2
)
/
(
2
2
)
/
(
2
)
/
(
2
2
2
1
2
1
2
2
1
D
2
1
2
1
L
W
L
W
V
V
I
I
g
I
V
L
W
L
W
I
I
I
I
V
I
V
I
g
L
W
L
W
I
I
I
L
W
L
W
I
I
I
L
W
L
W
L
W
L
W
L
W
L
W
OV
OV
m
OS
OV
OV
m





























 









 









































• Consider the effect of a mismatch Vt in threshold voltages :
 
 
 
 
 
 
t
m
OS
t
m
t
t
GS
t
GS
t
t
GS
n
t
GS
t
t
GS
n
t
t
GS
n
t
GS
t
t
GS
n
t
GS
t
t
GS
n
t
t
GS
n
t
t
t
t
t
t
t
GS
t
V
g
I
V
V
g
V
V
V
I
V
V
V
V
V
L
W
k
I
I
I
V
V
V
V
V
L
W
k
V
V
V
L
W
k
I
V
V
V
V
V
L
W
k
V
V
V
V
V
L
W
k
V
V
V
L
W
k
I
V
V
V
V
V
V
V
V
V
















































 
































 



















3
2
'
2
1
2
'
2
'
2
2
'
2
2
'
2
'
1
2
1
2
2
2
2
1
1
2
1
2
2
1
1
2
1
2
1
2
1
2
2
1
2
2
Let
.
2
Assume

• The total input offset voltage can be derived as
Total Input Offset Voltage
 2
2
2
2
3
2
2
2
1
/
)
/
(
2
2
t
OV
D
D
OV
OS
OS
OS
os
V
L
W
L
W
V
R
R
V
V
V
V
V







 








 





VOS for The BJT Case
OS
V



o
V
 
1
B 2
B

Input Offset Currents for BJT Case
• Input bias current
• Input offset current

Differential Amplifier with a Current-Mirror Load
• Taking the output differentially has three major advantages:
1. It decreases the common-mode gain and thus increases the CMRR.
2. It decreases the input offset voltage.
3. It increases the differential gain by a factor of 2 (6 dB).
• At least the first stage in an IC amplifier such as an op amp is
differential-in, differential-out.
• Nevertheless, it is usually required at some point to convert the
signal from differential to single-ended; for instance, to connect it to
an off-chip load.

Differential-to-Single-Ended Conversion
• Note that the current signal in Q1 is not utilized, and as a result, the
gain achieved is 6 dB lower than the differential-output case.
Small-signal model
D
m
id
o
V R
g
v
v
A
2
1



Current-Mirror-Loaded MOS Differential Pair
current)
output
(zero
0
:
grounded
inputs
When
3





O
SG
DD
A
O
I
V
V
V
V
IO = 0
A

Current-Mirror-Loaded MOS Differential Pair
• For small-signal common-mode
input signals, iD4 cancels iD2.
• For small-signal differential input
signals, iD4 matches iD2.
0

s
v
icm
s v
v 
(Good)
0
0
&
0




cm
O
O
A
v
i
(Good)
gain
al
differenti
Double
2

 i
iO

Differential Gain
Output equivalent circuit
for differential input
signals.
Gmd : Differential short-
circuit transconductance
Ro : Output resistance
• It can be shown that
Rod = output resistance of differential amp
Rom = output resistance of current mirror
• The open-circuit differential voltage gain
can be found as
• Let gm1,2 = gm and ro2,4 = ro.
where A0 is the intrinsic gain.
om
od
o
o
o
o
o
m
md
R
R
r
r
R
r
g
G
||
||
)
(neglect
4
2
3
,
1
2
,
1



 
om
od
m
o
md
id
o
d R
R
g
R
G
v
v
A ||
2
,
1



0
2
1
2
1
A
r
g
A o
m
d 


Derivation of Gmd
3
1
1
m
o
g
R 
0
2 
o
R
0
0
2
1


d
d
v
v






4
3
2
,
1
for
m
m
m
m
id
m
o
g
g
g
g
v
g
i

Derivation of Ro






1
for
2
2
2
2
1
2
2
o
m
m
m
o
o
r
g
g
g
r
R
L
R
4
02 || o
x
r
r
v


BJT Differential Pair with a Current-Mirror
Load
o
o
o r
r
r 
 4
2

Differential Gain: BJT vs. MOS
• Pros:
– The gain is much larger because gmro for the BJT is more than an order
of magnitude greater than gmro of a MOSFET.
• Cons:
– Low differential input resistance for BJT amplifiers:
– For multistage amplifiers, the overall voltage gain will be drastically
reduced by the low Rid of the subsequent BJT stage.
2
id
R 3
id
R

Systematic Input Offset Voltage
• This circuit suffers from a systematic offset voltage due to the error in the
current transfer ratio of the current-mirror load caused by the finite  of Q3,4.


finite
to
due
imbalance
Bias
2
1 2
1










 I
I
1
I 2
I
2
I
2
2
I


Common-Mode Gain and CMRR
Gmcm is the common-mode
short-circuit transconductance
o
mcm
cm R
G
A 
4
2 || o
o
o r
r
R 

Derivation of Gmcm
a b
)
,
(for 2
,
1
2
,
1 o
o
o
m
m
m r
r
g
g 

KCL @ a,b,S
KCL @ D2

Derivation of Gmcm
• Since gmro >> 1, gmRSS >> 1, and Rim << ro .
• Two separate reasons for the nonzero Gmcm
– Am  1
– Rim  0 ( It leads to i1  i2.)






0
1
if
0
:
im
m
mcm
R
A
G

Derivation of Gmcm
• For the simple MOS mirror, we have
• The common-mode gain can be found as
• |Acm| is small and can be reduced by using a current source with a large RSS.
)
||
(
1
2
1
1
2
2
1
1
2
1
)
1
(
2
)
1
(
2
1
1
1
1
1
/
1
1
||
1
.
1
and
1
Assume
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
o
o
m
SS
o
m
o
m
o
m
SS
m
o
im
m
SS
mcm
o
m
o
m
m
m
o
m
im
o
m
r
r
g
R
r
g
r
g
r
g
R
A
r
R
A
R
G
r
g
r
g
A
g
r
g
R
r
g
ε




















































SS
m
cm
o
o
o
o
o
o
m
o
o
SS
o
mcm
cm
R
g
A
r
r
r
r
r
r
g
r
r
R
R
G
A
3
4
3
2
3
3
4
2
2
1
For
)
||
(
||
2
1











im
R i
i
o
i
i
o
m
i
i
A 

CMRR
• The CMRR will be large and it can be increased by raising the RSS.
 
 
 
 
normally)
n
larger tha
(Much
||
2
For
||
2
)
||
(
2
1
have
we
Now
3
2
,
1
4
,
3
2
,
1
3
3
2
,
1
2
,
1
3
3
2
,
1
SE
om
od
m
CMRR
SS
m
om
o
od
o
o
o
o
m
SS
m
mcm
m
cm
d
o
o
m
o
SS
o
mcm
cm
o
m
d
CMRR
R
R
g
R
g
CMRR
R
r
R
r
r
r
r
g
R
g
G
g
A
A
CMRR
r
r
g
R
R
R
G
A
R
g
A
SE



























Multistage Amplifiers
• To illustrate the circuit structure and the method of
analysis of multistage amplifiers, we will present two
examples:
1. A two-stage CMOS op amp
2. A four-stage bipolar op amp

A Two-Stage CMOS Op Amp
• The circuit utilizes two power supplies,
which can range from ±0.9 V for the
0.18-μm technology down to ±0.5 V for
the 65-nm technology.
• The current mirror formed by Q8 and
Q5 supplies the differential pair Q1−Q2
with bias current. The W/L ratio of Q5
is selected to yield the desired bias
current I.
• The input differential pair is loaded
with the current mirror Q3,4.
• The second stage consists of Q6,
which is a CS amplifier with a current-
source load Q7.
• A capacitor CC is included in the
negative-feedback path of the second
stage for improving the stability. (By
using the Miller effect)
• Voltage gain of the first stage :
• Voltage gain of the second stage :
• DC open-loop gain of the op amp : A1A2
Stage-1 Stage-2

A Two-Stage CMOS Op Amp
• The op amp is not suitable for driving low-impedance loads due to its high
Rout = (ro6||ro7).
• This circuit is very popular and is used frequently in VLSI circuits, where the
op amp needs to drive only a small capacitive load, for example, in
switched-capacitor circuits.
• Also, when this op amp is utilized, negative feedback is applied, which
results in reducing Rout.
• The simplicity of the circuit results in an op amp of reasonably good quality
realized in a very small chip area.

Input Offset Voltage
• The device mismatches inevitably present in the input stage give rise to an
input offset voltage. Because device mismatches are random, the resulting
offset voltage is referred to as random offset.
• Another type of input offset voltage that can be present even if all
appropriate devices are perfectly matched is the systematic offset. It can be
minimized by careful design.
• Compared to the BJT op amps, the input offset problem is usually much
more pronounced in CMOS op amps because their gain-per-stage is rather
low.

Zero Systematic Offset
• The condition for achieving zero systematic offset is I6 = I7 .
3
4
6 GS
GS
GS V
V
V 

6
I
7
I
2
I 2
I

A Bipolar Op Amp
• The bipolar op amp consists of
four stages.
• The 2nd stage performs the
differential to single-ended
conversion, which results in a
loss of gain by a factor of 2.
• The 3rd stage provides some
voltage gain and the essential
function of dc level shifting.
• The output stage consists of
emitter follower.
Input
stage
2nd
stage
3rd
stage
Output
stage

Analysis Using Current Gains
Each factor is either the current gain of a
transistor or the ratio of a current divider.
(differential)
(differential)
2
1
,
1 R
R
R diff
o 


microelectronics-6ed-ch8-ppt-2025-spring

More Related Content

Similar to microelectronics-6ed-ch8-ppt-2025-spring (20)

Recently uploaded (20)

microelectronics-6ed-ch8-ppt-2025-spring