Microwatt: Open Tiny Core, Big Possibilities
- 1. Microwatt
- 2. What is Microwatt? • Microwatt is an open-source, soft-core processor implementing the Power ISA 3.0, developed by the OpenPOWER Foundation community—originally started by IBM. • Written in VHDL. • Simple, readable, and educational design. • Supports Operating Systems like Linux, Zephyr, and OpenSBI. • Includes basic peripherals like UART and SPI. • Designed to be synthesized on FPGAs. • Developed as part of the OpenPOWER initiative to promote open hardware.
- 3. Instruction Set Architecture (ISA) 32 General Purpose Registers. Implements a 64-bit architecture. Supports both 32-bit and 64-bit instructions (as defined by Power ISA 3.0) Integer Instructions. Floating-Point Support: Limited. Supervisor/User Mode: Yes. Endianness: Big-endian and little-endian support. MMU: Optional (supports Linux booting with MMU).
- 4. Micro architecture • Basic 5-stage pipeline: Fetch → Decode → Execute → Memory → Writeback • In-order execution (no out-of-order or speculative execution) Pipeline: • Uses static or simple branch handling Branch Prediction: No branch prediction • Instruction Cache (I-Cache): Optional (typically 4KB or 8KB) • Data Cache (D-Cache): Optional • L2 / Last-Level Cache: Not implemented in basic Microwatt Caches: TLB / MMU: Present in some versions FPGA Portability: Designed to be synthesizable and compact for FPGAs
- 5. Interface Wishbone Bus: Yes — for peripherals and memory- mapped I/O GPIO Support: Through Wishbone- attached peripherals
- 7. Core Implementation (Five Stage Pipeline) • fetch1 • icache (uses predecoder, cache_ram and plrufn blocks) • decode1 • decode2 • register_file • cr_file • execute1 (contains arithmetic blocks like rotator,logical,multiply,divider,bit_sorter,etc) • fpu(Optional) • loadstore1 • mmu (optional) • dcache (uses predecoder, cache_ram and plrufn blocks) • writeback • code_debug
- 8. Configurable Parameters The core entity provides generics that enable configuration of optional features and cache parameters: • HAS_FPU, HAS_BTC, EX1_BYPASS – Control FPU inclusion, branch target cache, and bypass logic. • ICACHE_NUM_LINES, DCACHE_NUM_WAYS, etc. – Configure instruction and data cache geometry. • ALT_RESET_ADDRESS – Useful for DRAM initialization firmware.
- 9. Core Implementation fetch1 (Instruction Fetch Stage) • Acesses program counter (PC) for the instruction address. • Signals pipeline to halt if necessary (e.g., waiting on a branch decision) • Drives the pc into icache to fetch the instruction • Controlled by signals from execute1, writeback, and debug. icache (Instruction Cache) • Fetches instruction from instruction memory (if available in cache) or forwards the request to the Wishbone bus. • Sends instruction to decode1. • Interfaces with Wishbone (iwbm_ signals) for memory access.
- 10. Core Implementation decode1 and decode2 (Instruction Decode Stages) • decode1: Decodes instruction fields, identifies operands • decode2: Expands decoding, handles immediate values, and control signals. • Drives operand read addresses to register_file. • Passes decoded instruction information to the execution stages. register_file • Holds CPU registers and provides operand values. • Sends register values to execute1 and loadstore1.
- 11. Core Implementation cr_file (Control Register File) • Stores condition codes, status, and control information. • Interacts with decode and writeback for system-level instructions (e.g., CSR). execute1 • Main ALU stage—performs arithmetic, logical, branch, and control ops. • Drives branch results to fetch1. • Forwards data to writeback. loadstore1 • Memory stage for load/store operations. • Interfaces with dcache, mmu.
- 12. Core Implementation dcache (Data Cache) • Handles memory access for load/store. • Communicates with mmu for address translation. • Interfaces with Wishbone (dwbm_ signals). mmu (Memory Management Unit) • Translates virtual to physical addresses for data accesses. • Between loadstore1, dcache, and Wishbone bus. • Signals TLB misses or page faults to control flow.
- 13. Core Implementation writeback • Final stage that writes results back to the register_file. • Also interacts with debug interface and control/status logic. debug • JTAG or external debug interface. • Can halt, single-step, or inspect internal signals. • Monitors PC, registers. • Can inject traps or halt signals.
- 14. SoC Components • core • syscon - System Controller • wishbone_bram_wrapper - Block RAM Memory (BRAM) • dmi_dtm - Debug Transport Module • wishbone_debug_master - Wishbone Debug Bridge • pp_soc_uart (UART0, UART1) – UART Peripheral for • spi_flash_ctrl - SPI Flash Memory Controller • xics_icp and xics_ics - External Interrupt Controller for Power ISA • gpio - General Purpose I/O Controller
- 15. SoC Components Core • Entity: work.core • Connects to Wishbone • Receives interrupts • Communicates via DMI System Controller • Entity: work.syscon • Provides SoC configuration/status registers. • Includes SoC version, reset control, clock config, etc.
- 16. SoC Components wishbone_bram_wrapper - Block RAM Memory • Entity: work.wishbone_bram_wrapper • Instantiates internal BRAM as a memory-mapped Wishbone slave. • Only if MEMORY_SIZE != 0 • If MEMORY_SIZE = 0, a dummy memory interface is generated that always ACKs with all 1s. dmi_dtm - Debug Transport Module • Entity: work.dmi_dtm • JTAG interface bridge to DMI bus. • Converts JTAG signals to DMI protocol • Inputs: JTAG TAP (implied), clock, reset • Outputs: DMI transaction signals (dmi_addr, dmi_req, dmi_wr)
- 17. SoC Components wishbone_debug_master - Wishbone Debug Bridge • Entity: work.wishbone_debug_master • Converts DMI requests into Wishbone transactions. • Connected to Wishbone master port, used for debug access to any mapped peripherals. pp_soc_uart (UART0, UART1) • Entities: work.pp_soc_uart • Serial communication. UART0 typically used for console/debug. spi_flash_ctrl - SPI Flash Memory Controller • Entity: work.spi_flash_ctrl • External SPI flash memory access via Wishbone.
- 18. SoC Components xics_icp and xics_ics - External Interrupt Controller for Power ISA • Entities: work.xics_icp, work.xics_ics • Implements IBM-style external interrupt controller • Peripherals generates interrupts for service and are handled by XICS • xics_ics(Interrupt Controller Source) receives interrupt assertions from devices (like UART, GPIO, Ethernet, etc.) and prioritizes them. • xics_icp (Interrupt Controller Presentaion) Interfaces with the CPU core, presenting the interrupt vector for handling. gpio - General Purpose I/O Controller • Entity: work.gpio • Simple bidirectional GPIO with interrupt generation.
- 19. Code flow Power-Up Clock Active Reset Asserted → Reset Propagated Active Core Fetches from BRAM (via Wishbone) Peripherals Idle → Await Core Access Interrupts Wired → ICS → ICP → Core Debug Master via DMI → Access Core & Fabric SoC Ready for Full Operation
- 20. Code flow Power-Up and Reset • The FPGA powers on, and all logic is initialized to default states. • A reset signal (soc_reset, etc.) is asserted to ensure all components start cleanly. • This reset is propagated to all components: core, BRAM, wishbone fabric, peripherals, interrupt controller, DMI, etc. Clock and Reset Distribution • system_clk is distributed across all modules. • rst_* signals (like rst_bram, rst_wbdb, rst_dtm) are derived from soc_reset and connected to corresponding components.
- 21. Code flow Core Initialization • Core entity is instantiated. • Core fetches its first instruction typically from BRAM, using the wishbone bus. • It initializes internal structures like: • Instruction cache (iCache) • Data cache (dCache) • General-purpose registers • Program Counter (PC) BRAM (Boot Memory) Ready • The wishbone_bram_wrapper provides instruction and/or data memory. • If MEMORY_SIZE /= 0, then BRAM is instantiated and initialized from RAM_INIT_FILE. • The core accesses BRAM via Wishbone to begin code execution.
- 22. Code flow Wishbone Interconnect Ready • A Wishbone bus fabric connects: • Core (as master) • Peripherals (as slaves): • pp_soc_uart (UART0/UART1) • spi_flash_ctrl • gpio • xics_icp • syscon • wishbone_bram_wrapper • Wishbone arbitration ensures only one master accesses a slave at a time. Peripherals Idle / Ready • Each peripheral is connected to Wishbone and is waiting for requests from the core. • UARTs, GPIO, SPI Flash are passive until written to or read from.
- 23. Code flow Interrupt Setup • The int_level_in signal vector collects interrupt signals from peripherals • These are passed into XICS_ICS (interrupt controller source), which filters and forwards them to XICS_ICP. • XICS_ICP signals the core when an interrupt is pending. Debug Infrastructure • The dmi_dtm (Debug Transport Module) receives debug commands via JTAG. • It communicates with the wishbone_debug_master, which can: • Read/write core memory or registers • Control peripheral state • This is key for software debugging and bring-up. Simulation Exit (Optional) • If SIM is true and a special DMI write is made to address "11111111", simulation exits.
- 24. Recap Power-up: Initializing the SoC, including the core and its interconnects. Reset Sequence: The reset controller initializes all components, ensuring the system starts in a known state. Core Initialization: The processor core (Microwatt) begins execution, initializing caches, register files, and control registers. Peripheral Setup: The peripheral blocks (UART, SPI, GPIO, BRAM, Interrupt Controllers) are configured via the system control (syscon) unit. Instruction Fetch: The processor fetches instructions from memory (using ICache) and decodes them. Execution: The processor executes instructions (including memory operations, FPU operations, and branching), interacting with memory and peripherals. Task Completion: The final task (e.g., computation or I/O operation) is completed, and the result is either written back to memory or output via peripherals.