On how to efficiently implement Deep Learning algorithms on PYNQ platform
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The document discusses efficient implementations of deep learning algorithms on the PYNQ platform, focusing on techniques like binarized neural networks and quantized neural networks. It presents a novel polymorphic register file solution to optimize memory access and improve hardware design productivity, exemplified through matrix multiplication case studies. Experimental results indicate a significant speedup in execution time on specific Xilinx hardware.
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Context Definition
[1] "Efficient Processing of Deep Neural Networks: A Tutorial and Survey"
Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel Emer](https://image.slidesharecdn.com/deepynqngc18-180526050131/85/On-how-to-efficiently-implement-Deep-Learning-algorithms-on-PYNQ-platform-2-320.jpg)
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What we can do
• Binarized Neural Networks (BNNs)
BNN-PYNQ [1]
• Quantized Neural Networks (QNNs)
QNN-MO-PYNQ [1]
• MobileNets [2]
[1] FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Leong, Magnus Jahre, Kees Vissers
[2] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications
Andrew G. Howard, Menglong Zhu, Bo Chen, Dmitry Kalenichenko, Weijun Wang, Tobias Weyand, Marco Andreetto, Hartwig Adam](https://image.slidesharecdn.com/deepynqngc18-180526050131/85/On-how-to-efficiently-implement-Deep-Learning-algorithms-on-PYNQ-platform-11-320.jpg)
On how to efficiently implement Deep Learning algorithms on PYNQ platform
- 1. On how to efficiently implement Deep Learning algorithms on PYNQ platform Luca Stornaiuolo Dipartimento di Elettronica Informazione e Bioingegneria (DEIB) luca.stornaiuolo@polimi.it Donatella Sciuto, Marco D. Santambrogio 05/25/2018 Xilinx San Francisco, CA
- 2. 2 Context Definition [1] "Efficient Processing of Deep Neural Networks: A Tutorial and Survey" Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel Emer
- 5. 5 Context Definition Model New Data Prediction Inference Smart Embedded Systems
- 6. 6 Context Definition Model New Data Prediction Inference Smart Embedded Systems
- 7. 7 Context Definition Model New Data Prediction Inference Smart Embedded Systems
- 8. 8 Context Definition Model New Data Prediction Inference Smart Embedded Systems Resource-constrained environment
- 11. 11 What we can do • Binarized Neural Networks (BNNs) BNN-PYNQ [1] • Quantized Neural Networks (QNNs) QNN-MO-PYNQ [1] • MobileNets [2] [1] FINN: A Framework for Fast, Scalable Binarized Neural Network Inference Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Leong, Magnus Jahre, Kees Vissers [2] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications Andrew G. Howard, Menglong Zhu, Bo Chen, Dmitry Kalenichenko, Weijun Wang, Tobias Weyand, Marco Andreetto, Hartwig Adam
- 15. 15 Proposed Solution A novel implementation of the Polymorphic Register File for Vivado HLS • raises the level of abstraction for efficient parallel accesses to on-chip memory; • improve productivity within hardware design flow; • introduces masked methods to avoid overwrites
- 16. 16 Case Study Matrix Multiplication (BxC and CxB) B C
- 17. 17 Case Study Matrix Multiplication (BxC and CxB) B C
- 18. 18 Case Study Matrix Multiplication (BxC and CxB) Naïve solutions without PRF: • Send data twice • Duplicate data • Complete partitioning B C
- 19. 19 Case Study Matrix Multiplication (BxC and CxB) Naïve solutions without PRF: • Send data twice (data transfer overhead) • Duplicate data (high BRAM utilization) • Complete partitioning (high registers utilization) B C
- 20. 20 Case Study Matrix Multiplication (BxC and CxB) Naïve solutions without PRF: • Send data twice (data transfer overhead) • Duplicate data (high BRAM utilization) • Complete partitioning (high registers utilization) B C PRF
- 21. 21 Case Study HLS Block Partitioning HLS PRF
- 22. 22 Case Study HLS Block Partitioning HLS PRF
- 23. 23 Experimental Results On a Xilinx Virtex-7 VC707 with clock frequency equal to 100MHz and the PRF execution time achieves a speedup of 5x
- 24. 24 Experimental Results On a Xilinx Virtex-7 VC707 with clock frequency equal to 100MHz and the PRF execution time achieves a speedup of 5x
- 25. 25 Other Schemes
- 29. Luca Stornaiuolo Dipartimento di Elettronica Informazione e Bioingegneria (DEIB) luca.stornaiuolo@polimi.it Donatella Sciuto, Marco D. Santambrogio 05/25/2018 On how to efficiently implement Deep Learning algorithms on PYNQ platform https://necst.it/ https://www.slideshare.net/necstlab