Operating system 35 paging
- 1. Operating System 35 Paging Prof Neeraj Bhargava Vaibhav Khanna Department of Computer Science School of Engineering and Systems Sciences Maharshi Dayanand Saraswati University Ajmer
- 2. Paging • Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available – Avoids external fragmentation – Avoids problem of varying sized memory chunks • Divide physical memory into fixed-sized blocks called frames – Size is power of 2, between 512 bytes and 16 Mbytes • Divide logical memory into blocks of same size called pages • Keep track of all free frames • To run a program of size N pages, need to find N free frames and load program • Set up a page table to translate logical to physical addresses • Backing store likewise split into pages • Still have Internal fragmentation
- 3. Address Translation Scheme • Address generated by CPU is divided into: – Page number (p) – used as an index into a page table which contains base address of each page in physical memory – Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit – For given logical address space 2m and page size 2n page number page offset p d m -n n
- 5. Paging Model of Logical and Physical Memory
- 6. Paging Example n=2 and m=4 32-byte memory and 4-byte pages
- 7. Paging (Cont.) • Calculating internal fragmentation – Page size = 2,048 bytes – Process size = 72,766 bytes – 35 pages + 1,086 bytes – Internal fragmentation of 2,048 - 1,086 = 962 bytes – Worst case fragmentation = 1 frame – 1 byte – On average fragmentation = 1 / 2 frame size – So small frame sizes desirable? – But each page table entry takes memory to track – Page sizes growing over time • Solaris supports two page sizes – 8 KB and 4 MB • Process view and physical memory now very different • By implementation process can only access its own memory
- 8. Free Frames Before allocation After allocation
- 9. Implementation of Page Table • Page table is kept in main memory • Page-table base register (PTBR) points to the page table • Page-table length register (PTLR) indicates size of the page table • In this scheme every data/instruction access requires two memory accesses – One for the page table and one for the data / instruction • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)
- 10. Implementation of Page Table (Cont.) • Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process – Otherwise need to flush at every context switch • TLBs typically small (64 to 1,024 entries) • On a TLB miss, value is loaded into the TLB for faster access next time – Replacement policies must be considered – Some entries can be wired down for permanent fast access
- 11. Associative Memory • Associative memory – parallel search • Address translation (p, d) – If p is in associative register, get frame # out – Otherwise get frame # from page table in memory Page # Frame #
- 12. Paging Hardware With TLB
- 13. Effective Access Time • Associative Lookup = time unit – Can be < 10% of memory access time • Hit ratio = – Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers • Consider = 80%, = 20ns for TLB search, 100ns for memory access • Effective Access Time (EAT) EAT = (1 + ) + (2 + )(1 – ) = 2 + – • Consider = 80%, = 20ns for TLB search, 100ns for memory access – EAT = 0.80 x 100 + 0.20 x 200 = 120ns • Consider more realistic hit ratio -> = 99%, = 20ns for TLB search, 100ns for memory access – EAT = 0.99 x 100 + 0.01 x 200 = 101ns
- 14. Memory Protection • Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed – Can also add more bits to indicate page execute-only, and so on • Valid-invalid bit attached to each entry in the page table: – “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page – “invalid” indicates that the page is not in the process’ logical address space – Or use page-table length register (PTLR) • Any violations result in a trap to the kernel
- 15. Valid (v) or Invalid (i) Bit In A Page Table
- 16. Assignment • Explain in detail the concept of paging