VLSI lab manual Part B, VTU 7the sem KIT-tiptur

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VLSI Lab Manual
FOR VII SEMESTER E&C ENGG., AS PER VTU SYLLABUS
Department of Electronics and Communication Engineering
KALPATARU INSTITUTE OF TECHNOLOGY
TIPTUR-572202
45nm Size Comparison
A nail = 20 million nm
A human hair = 90,000nm
Ragweed pollen = 20,000nm
Bacteria = 2,000nm
Intel 45nm transistor = 45nm
Rhinovirus = 20nm
Silicon atom = 0.24nm

VLSI LAB VII Semester
Department of Electronics & Communication, K.I.T, Tiptur 36
PROCEDURES FOR ANALOG DESIGN
Custom IC Design Flow
Circuit simulation
Schematic entry
Layout
Layout versus schematic
Design rule check
Parasitic RC extraction
Back annotation
GDS-II to foundry
Specifications

INITIAL PROCEDURES:
1. After logging in, right click and open terminal.
2. Move inside the respective directory using the cd command –
cd Cadence_tools/cadence_database
3. Get into the c shell by typing the command –
csh
4. Run the shell script by typing the command –
source cshrc
5. Move inside the respective directory using the cd command –
cd cadence_ms_labs_614
6. Invoke the analog design tool by using the command –
virtuoso -64
After the virtuoso console opens up, maximize it. The linux terminal can be minimized.
7. In the virtuoso console, create your own library by following the steps –
File → New → Library

8. In the “New Library” window that opens up, fill in your library name (e.g.:
Design2), and then click on the option –
Attach to an existing technology library
9. A selection box named “Attach Library to Technology Library” will open.
Select “gpdk180” and click on OK.

1.STEPS FOR DESIGN ENTRY:
1. In the virtuoso console, select the following –
File → New → Cellview
2. In the “New File” form that opens, browse for your library name, and in front
of the Cell,fill in the name of the schematic that is going to be entered (e.g.:
inverter). Later, click on OK.
3. A new design window opens, in which the schematic has to be entered.

4. After the schematic entry, a symbol for the schematic has to be
created in the schematic editor window, by selecting the following –
Create → Cellview → From Cellview
During these steps, one more editor window will open up for the symbol
entry. The symbol generation procedures will be elaborated while
describing the experiments.
5. After symbol creation, both the editor windows can be closed. Now for
the test circuit,a new Cellview has to be created in the virtuoso console.
Again, the detailed procedures for the test circuit are elaborated while
discussing the respective experiments.
2. STEPS FOR SIMULATION AND LAYOUT:
The test circuit has to be simulated by launching ADE-L in the schematic editor
window, and then by choosing the respective analyses in ADE. The three main
analyses that are performed are transient, dc and ac. With output plotted in Y-axis,
the details of these analyses are summarized below –
Type of analysis X-axis Observation
Transient Time Waveform
DC Input V. Transfer
characteristicsAC Frequency Bandwidth
After the circuit verification, the layout for the schematic has to be prepared using
Layout-XL, and the same has to be physically verified. The detailed procedures
are explained with the experiments.
NOTES
1. Abbreviations:
av assura verification
ADE Analog Design Environment DRC Design Rule Check
ELW Error Layer Window gpdk general process design kit
LSW Layer Selection Window LVS Layout Versus Schematic
RCX RC extraction VLW View Layer Window
2. Cadence tools used:
Virtuoso schematic editor Virtuoso ADE - for analyses andplots
Spectre - for circuit simulation
Virtuoso layout suite
Assura – DRC, LVS, RCX

EXPERIMENT 9
INVERTER
Aim: To simulate the schematic of the CMOS inverter, and then to perform the
physical verification for the layout of the same.
Procedure: In three steps Design entry, Simulation and Layout.
I. DESIGN ENTRY: The three initial steps before simulation are: schematic
entry, symbol entry and test circuit entry. The procedures are as detailed
below –
1. In the schematic editor window, for the addition of instances, press “ i ”.
This will open the “Add Instance” window. In that window, browse for the
library gpdk180, select the cell pmos and then select the view symbol. Click
on close.
Library name Cell name Properties
gpdk180 pmos W=5µ, L=180n
gpdk180 nmos W=2µ, L=180n

2. The properties of the selected instance are displayed in the “Add Instance”
window. There is no need to modify any properties for this particular
experiment. Click on Hide.
3. The pmos symbol will move along with the cursor. Place it in the top mid-
position, left-click and then press Esc.

4. Similarly place nmos device, and then press Esc.
5. Now, press “ w ” for placing wire, click on the respective nodes and connect
them through wire. Place the input and output wires as well. Complete the
substrate connections also.
6. After pressing Esc, press “ p ” for adding pins to the schematic diagram. In the
“AddPin” window, enter the name of the pin (e.g.: in), and ensure its direction
as input. Pin Direction
in Input
out Output
vdd vss Input

7. Click on Hide, and place the pin at the input. Later press Esc. Complete the
schematic by placing the instances “vdd” and “gnd”, which are in the
analogLib library.
8. Similarly, place the output pin with name “out” and direction output.
9. Finally, click on “check & save” icon and observe the errors in the virtuoso
console. In the schematic window, the errors will be highlighted with yellow
boxes. Move those boxes, correct the errors, and click on “check & save”.
Correct all the errors that are reported.

10. After the schematic entry is finished, a symbol for the design has to
be created. Forthis purpose, click on Create and follow the procedure
- Create → Cellview → From Cellview
The name comes by default, along with the other options. Click on OK.
11. Another window opens, which shows the input and output pin
configurations. Click on OK.

Department of Electronics & Communication, K.I.T, Tiptur
46
12. A symbol editor window opens up with the default symbol.
13. The default symbol can be edited by press “t” on partName for renaming
and delete instanceName, and click on “check & save”. Correct all the errors
that are reported.
14. After the schematic and symbol entries, both the editor windows can be
closed. Now for creating a test circuit, create a new cellview from the
virtuoso console, and give the name as “inverter_test”.

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15. When the editor window opens, press “i”, browse for your library and select
the inverter symbol which was created earlier. Place it in the middle of the
screen.
To ensure that the symbol is loaded correctly, you can click on the symbol
and then press “Shift E”. The schematic editor will move one level down,
and the inverter’s circuit entered earlier will be displayed on the screen. To
come back to the symbol, press “Ctrl E”; the symbol will be displayed back.
Press Esc to unselect the symbol.
16. Place wires at the input and output, and place an output pin as well.
These wires are needed during simulation, to plot the voltage waveforms.

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17. Input sources.
18. Press “i”, browse analogLib library and select “vpulse” and its symbol.
19. In the property window, enter Voltage1 as 0 and
Voltage2 as 1.8. Similarly enter Periodas 20n and
Pulse width as 10n, without the space in between.
No need to enter the units; they appear
automatically. Place the “vpulse” at the input wire.
Connect “gnd” at the other end.
analoglib Vpulse
Vin=
V1=0,V2=1.8,T(Period)=20n, Ton(Pulse width)=10ns
analoglib Vdc Vdc=1.8

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20. Similarly, browse for the instance “vdc”, and enter its DC voltage as 1.8.
21. Place “vdc” at the front, and connect “vdd” and “gnd” accordingly. Finally
“check & save”. The test circuit is complete now, and ready to be
simulated.

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Note: The library gpdk180 contains the technology dependent components
(180nm), and the library
analogLib contains the technology independent components.
Whenever a component needs to be selected, place the cursor on the component
and click on it. The selected component’s boundary turns into magenta color.
Now the properties of the component can be verified by pressing “q”, after which
the property window opens.
To zoom a particular portion of the screen, right click, hold, and move the mouse.
A yellow colored boundary will be drawn on the screen. When the finger is
released, the highlighted portion gets zoomed. To come back to the original
screen, press “f”. Alternatively, “Ctrl Z” and “Shift Z” can be used, to zoom in and
zoom out.
After the symbol is entered, Shift and E can be used together to move one level
down, to view the schematic diagram. Later, Ctrl and E can be used together to
move one level up, to thesymbol.
The hot key functions that are used during design entry are summarized as follows
–
Hot key Function
i Instance
w Wire
p Pin
m Stretch
q Property
r Rotate
u Undo
c Copy
f Fit to screen
Esc Exit

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II. SIMULATION:
1. In the test circuit’s editor window, click on Launch → ADE L. A new window
will open.
2. Click on Analyses → Choose. A new window will open, in which select
“tran”. Fill the stop time as 100n, and select liberal. Later, click on Apply.
Analysis Values
Transient Stop time = 100ns
Dc Start time =0, stop time =1.8.

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3. Now select “dc” on the Choosing
Analyses window, and click on
Save DC Operating Point. Click on
the Component Parameter. A
Select Component option will pop
up.
4. Double click on Select Component. The ADE window gets minimized, and
the schematic is shown. Click on the component “vpulse”. In the new
window that opens up, click on the top most parameter dc and then click
on OK.

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5. Ensure that the component
name and parameter name are
updated. Now in the Sweep
range, enter 0 and 1.8 in the
Start and Stop options
respectively. Later, click on
Apply.
6. In the ADE window, ensure that the Analyses fields are updated for tran and
dc.

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7. Now to select the stimulus and response points, in the ADE window, click
on Outputs → To be plotted → Select on Schematic. In the schematic
window, click on input and output wires. These wires will become dotted
lines when selected. Later, press Esc.
8. In the ADE window, check that the Outputs fields are updated. Now click
on Simulation → Netlist and Run. The waveform window will open and
the simulation results aredisplayed. Transient response is displayed on the
left side and DC response on the right.
Click on the transient response waveform and then click on the fourth icon
at the top (Strip chart mode). The input and output waveforms are displayed
separately. You can “right click” on each waveform, and then edit the
properties of the display such as color and appearance. Similarly, the
transfer characteristics can be observed at the right hand side.

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III. LAYOUT:
1. For preparing the layout of the inverter, all the other windows can be
closed, except for the virtuoso console. In the console, open the
schematic of the inverter and click on Launch → Layout XL. In the
Startup Option, click on OK.
2. In the New File option, the tool selects the view as layout by default. Click
on OK.

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3. The tool opens the LSW and the Layout suite.
4. Maximize the layout suite and click on Connectivity → Generate → All
from Source.
Generate Layout window will open, with default attributes. Click on OK.

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5. The layout suite displays a cyan colored box in the first quadrant, which is
the Photo-Resist boundary. In addition, in the fourth quadrant, the default
layouts of pmos and nmos transistors are displayed, along with four blue
squares, which are the nodes - vdd, gnd, input & output.
6. Press “Shift F / Ctrl F” to see all the layers within the default layout. Hold
the “right click” and move the mouse to zoom a selected portion, and
observe the layout carefully. The color details are – Orange border: n-well,
Red border: p-diffusion’s boundary, Yellow border: n-diffusion’s boundary,
Green: diffusion, Rose: polysilicon, Yellow square: contact cut, Blue:
metal1.

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7. Click on the pmos device and drag it into the PR boundary. The layout can
be moved either vertically or horizontally, not diagonally. During this
movement, the tool keeps displaying the connections of the terminals with
the nodes. After placing the pmos device, place the nmos device below it. If
the space is insufficient, the PR boundary can be enlarged, through the top
and the right edges. For this purpose, press “s” and click on the edge of the
PR boundary. (“s” is for stretch, in the layout suite). The selected edge will
turn into magenta color. Now release the finger and move the mouse till the
desired area, and click again. Later, press Esc.
8. After placing the devices, zoom the space in between the transistors. In the
LSW, selectPoly. Now in the layout suite, press “p”, place the mouse at the
middle of the gate’s lower contact of pmos device, and click once. (“p” is for
path, in the layout suite). Release the finger and move the mouse
downwards. The poly path will move along with the mouse. Move the mouse
until the gate area of the nmos device gets overlapped. Bring the cursor
exactly to the middle of the path and double click. The poly path between
the gates gets realized. The area can be zoomed further, and the devices
can be moved, for the exact overlapping of the poly layers.

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9. In the LSW, select Metal1. Using the same procedure, draw the paths for
“vdd” at the top and “gnd” at the bottom. Later, using the same metal path,
connect the source of pmos device to “vdd” and that of nmos device to
“gnd”. Finally, connect both the drains for the output path.
10.Now move to the fourth quadrant where the four blue squares are
displayed. Click on one of them; it will turn into magenta color. Press “q”,
and then click on Connectivity, to see its properties. If it is vdd, drag it and
place it on the upper metal path. Later, place the gnd on the lower path;
similarly, place the output pin. Now, place the input pin in front of the poly
and connect through a poly path.
11.Now, for connecting the input metal pin to the poly path, a via needs to be

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placed. Hence, in the layout suite click Create → Via. In the Via Definition
pull-down menu, select the via M1_POLY1. Click on Hide, and place the
via on the input pin. Press Esc.
12.Similarly, for the substrate connections, select the via M1_NWELL and place
it touching the n-well, and connect
it to “vdd” through a metal path.
Later, place the via M1_PSUB on
the “vss” path, for the substrate
connection of nmos device; the
Black background itself indicates
the p-substrate. (p-device resides
on n-well and n-device resides
directly on p-substrate).

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Labelling by pressing “L” on vias.

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13. As the layout is now
complete, its verification can be
performed. In the layout suite, click
on Assura → Run DRC. Give the
run name as “inverter” and verify the
output. If there are errors, the tool will
highlight those areas in White color.
The errors will be displayed in the
ELW, and the location of each error
can be known, by selecting the error
in ELW, and then clicking on the
arrow mark available in ELW.
Correct those errors and rerun DRC.
14.After the DRC check, click on Assura → Run LVS, and verify the output.
Correct the errors.

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15.After the LVS check, click on Assura → Run RCX. Click OK on the form
that appears.
16.After the RCX is run, the output is saved in your library as av_extracted. In
the virtuoso console, open the “inverter” file with view as av_extracted, and
observe the output. The layout can be enlarged and the parasitic
components can be observed. Each components value can be checked, by
selecting the component and pressing “q”.

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If the parasitic component values are beyond the limits, then the layout can be
optimized in the layout suite, for the reduction of the parasitic component values; later
on, the layout can be back-annotated with the existing parasitic components, and
simulation can be performed, for verifying the output.

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EXPERIMENT 10
COMMON SOURCE & COMMON DRAIN AMPLIFIERS
Aim: To simulate the schematic diagrams of the common source and common
drain amplifiers, and then to perform the physical verification for the layouts of the
same.
Circuit diagrams:
a) Common source amplifier
Vdd
Vbias
Vout
Vin
Vss
b) Common drain amplifier
Vdd
Vin
Vout
Vbias
Vss
A common-drain (CD) amplifier, also known as a
source follower, is one of three basic single-stage
field effect transistor (FET) amplifier topologies,
typically used as a voltage buffer. In this circuit the
gate terminal of the transistor serves as the input,
the source is the output, and the drain is common to
both (input and output), hence its name. The
analogous bipolar junction transistor circuit is the
common-collector amplifier. In addition, this circuit
is used to transform impedances.
The common-source (CS) amplifier may be viewed
as a transconductance amplifier or as a voltage
amplifier. As a transconductance amplifier, the input
voltage is seen as modulating the current going to
the load. As a voltage amplifier, input voltage
modulates the amount of current flowing through the
transistor, changing the voltage across the output
resistance according to Ohm's law. The easiest way
to tell if a transistor is common source is to examine
where the signal enters, and leaves. The remaining
terminal is what is known as "common". In this
example, the signal enters the gate, and exits the
drain. The only terminal remaining is the source.
This is a common-source transistor circuit.

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Procedure:
a) COMMON SOURCE AMPLIFIER:
1. For the schematic entry, select pmos device from gpdk180 library, and edit
the properties as Length = 1 micron and Width = 50 microns. (type “u” for
micron). Similarly, place thenmos device with Length = 1 micron and Width
= 20 microns. Place the wires for connection.
gpdk180 pmos W=50µ, L=1µ
gpdk180 nmos W=20µ, L=1µ

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2. Place “vdd” and “vss”. Later, place the input pins for Vbias and Vin, and
output pin for Vout. Click on “check & save” and correct the errors, if any.
3. Create the symbol for the schematic; the default symbol itself can be used.

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4. Close the editor windows, and create a new schematic in the virtuoso
console, for the test circuit. In the test circuit, retrieve the symbol from
your library, and then place “vsin”from the analogLib library for the input
signal, with the attributes entered as :
analoglib Vsin
Vin=
AC Magnitude=1, Amplitude=5m, Frequency=1k,
Offset voltage=0, DC voltage=0.
analoglib
Vdc,
Vdd=2.5, Vss=-2.5, Vbias= -2.5.
(Don’t enter the units).
The AC magnitude is used for ac analysis, and the Amplitude is used for
transient analysis. Place a wire in between vsin and vin.
5. After saving, launch ADE-L and enter the analyses requirements, as per
the procedures given in the previous experiment. For transient analysis, as
the input signal is of period 1ms, enter the Stop Time as 10m. For dc
analysis, Select Component “vsin”, select dc, and enter the Sweep Range
as Start -2.5 and Stop 2.5. (Units will appear automatically). As this
particular experiment is on amplifiers, ac analysis is also required for
finding the bandwidth. Hence, after tran and dc, click on ac, and enter the
Sweep Range of Frequency as 100 Hz till 1GHz. Select the Sweep Type
as Logarithmic and enter the Points per Decade as 20.
Analysis Values
Transient Stop time = 10m
Dc Start time = -2.5, stop time = 2.5.
Ac Start time= 100, stop time= 1G,points per decade = 20.

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ADE-L window having three analysis setup.

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6. Finally, select the wires on the schematic for plotting the outputs, and click
on the PLAY icon in the ADE window, for netlist & run. The output will
appear, and the waveforms can be edited in different colors, for better
viewing.
In the Transient Response, for measuring the amplitude, press “d”. Now two
delta cursors are made available on the screen, one with red pointer and the
other with green pointer. Move one cursor to the positive peak of the
waveform and the other cursor to the negative peak. The values (time &
amplitude) corresponding to the cursor positions are displayed at the
bottom, red one first and green one next. The difference in y-values gives
the peak-to-peak amplitude. (The input amplitude in this case is 10 mVpp,
as the amplitude given was 5mV). The dx | dy is also displayed at the right
side, and the dy value represents the amplitude.
For measuring the bandwidth, move the trace cursor in the AC Response
to the point which corresponds to 0.707 Vmax, and the display indicates
the frequency, which is the bandwidth corresponding to the -3dB gain.
The DC Response can be observed for the quiescent operation of the
amplifier.
7. After the completion of the simulation, close all the windows except the
virtuoso console. In the console, open the schematic file of the amplifier and
launch the layout suite. Proceed with the steps as mentioned in the previous
experiment, and place the respective paths, pins and the vias. For change
of direction of any path, single click at the center, and then change direction.

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8. As the PMOS device is of 50 microns length, and as substrate connections
of the device are required at every 10 microns (as per the design rules), get
a ruler on the screen by pressing “K”. Click the mouse adjacent to the top
of the device, and move the cursor till the lower end of the device. Click
again to place the ruler. Now, place the via M1_NWELL at every 10 micron
distance. Connect all of these vias to vdd by means of the metal path.

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9. Similarly, place the via M1_PSUB near the NMOS
device, and connect it to vss. Place one more via at
another 10 micron distance.
10. Press “Shift K” to delete all the rulers. Save the layout, and run the
DRC, LVS and RCX tests.
Alternative layout design:

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b) COMMON DRAIN AMPLIFIER:
1. The procedures remain similar to the previous experiment. Enter the
schematic diagram with the upper NMOS device dimensions as Length =
1 micron & Width = 50 microns, and the lower NMOS device dimensions
as Length = 1 micron & Width = 10 microns.
It is not mandatory that the “vdd” and “vss” symbols from the analogLib
library have to be used directly. They can be declared as pins, and their
voltages can be directly specified in the test circuit. This alternative method
is followed in this experiment, as shown in the circuit diagram below.
Complete the other connections as per the circuit diagram, and click on
“check & save” and correct the errors, if any.

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2. During the symbol generation, the vdd pin can be placed as the top pin and
the vss pin canbe placed as the bottom pin.
3. The symbol that is generated can be used directly. Click on “check & save”.
4. The test circuit is similar to the common source amplifier except that “vdc”
can be directly connected to the vdd and vss pins, and their voltages can
be edited respectively.
analoglib Vsin
Vin=
analoglib
Vdc,
Vdd=2.5, Vss= -2.5, Vbias= 2.5.

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the procedures given in the previous experiment.
Analysis Values
Ac Start time= 100, stop time= 1G,points per decade = 20.

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6. Finally, select the wires on the schematic for plotting the outputs, and click
on the PLAY icon in the ADE window, for netlist & run. The output will
appear, and the waveforms can be edited in different colors, for better
viewing.
7. As the next step, complete the layout and perform the physical
verification. The assura verification_extracted layout is as shown
below –

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EXPERIMENT 11
DIFFERENTIAL AMPLIFIER
A differential amplifier is a type of electronic amplifier that amplifies the difference
between two input voltages but suppresses any voltage common to the two inputs.
Aim: To simulate the schematic diagram of the differential amplifier, and then to
perform the physical verification for the layout of the same.
Procedure:
1. Perform the schematic entry as per the following specs: All of the transistors
will have the length = 1 micron; the PMOS load transistors with width = 15
microns; the NMOS input transistors with width = 3 microns; and finally, the
NMOS biasing transistors with width =4.5 microns. While placing the PMOS
transistors, the “Sideways” option can be used, for having their position as
shown in the schematic diagram.
gpdk180 nmos Model name(NM0, NM1); W=3µ, L=1µ
gpdk180 nmos Model name(NM2, NM3); W=4.5µ,L=1µ
gpdk180 pmos Model name(PM0, PM1); W=15µ, L=1µ

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2. Create a symbol for the schematic diagram, and place the input V2 as the left
pin.
3. Complete the test circuit by placing the current source, the input signal
and the power supplies. Initially, V1 can be used as the input, and V2
can be grounded at that time. The current source is available as “idc”
in the analogLib library; set its DC current as 30 µA. Connect its
positive end to vdd and negative end to the Idc input.
analoglib Vsin
V1=
analoglib
Vdc,
Vdd=2.5, Vss= -2.5
analoglib Idc Idc= 30µ
analoglib gnd V2

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the procedures given in the previous experiment.
5. For simulation, the transient and dc analyses details remain the same as
that of theprevious experiment.
Non-inverting amplifier: (V1 as input)
Analysis Values
Ac Start time= 100, stop time= 1G, points per decade = 20.

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Inverting amplifier: (V2 as input)
6. After the simulation, complete the layout and perform the physical
verification. The assura verification_extracted layout is shown below –
.

EXPERIMENT 12
OPERATIONAL AMPLIFIER
The op-amp is one type of differential amplifier. The amplifier's differential inputs
consist of a non-inverting input (+) with voltage V+ and an inverting input (–) with
voltage V−; ideally the op-amp amplifies only the difference in voltage between the
two, which is called the differential input voltage.
Aim: To simulate the schematic diagram of the operational amplifier, and then to
perform the physical verification for the layout of the same.
Procedure:
1. Fallow the table specifications
Design Lib Diff_amplifier Symbol
Design Lib cs_amplifier Symbol
Pin Names Direction
Idc, Vinv, Vnoninv Input
Vo Output
vdd vss Input

2. Create a symbol for the op-amp, as shown. Take Idc pin at the top, and widen
the gap between the input pins.
analoglib Vsin
Vinv=
AC Magnitude=1, Amplitude= 5µ, Frequency= 1k,
analoglib
Vdc, gnd
Vdd=2.5, Vss= -2.5, Vnoninv= gnd
analoglib Idc DC Current=30µ
analoglib gnd Vnoninv
3. Run the simulation with the same details as that of the previous
experiment.Then fallow the table specifications for simulation
Analysis Values
Ac Start time= 100, stop time= 1G, points per decade = 20.

4. After the simulation, complete the layout and perform the physical verification.

VLSI LAB(10ECL77) VII Semester
2016
84
EXPERIMENT 13
R-2R DAC
A resistor ladder is an electrical circuit made of repeating units of resistors. An R-2R
Ladder is a simple and inexpensive way to perform digital-to-analog conversion, using
repetitive arrangements of precision resistor networks in a ladder-like configuration.
A basic R-2R resistor ladder network is shown below. Bit Dn-1 MSB (most significant
bit) to Bit D0 LSB (least significant bit) are driven from digital logic gates. Ideally, the
bits are switched between 0 volts (logic 0) and Vref (logic 1). The R-2R network causes
the digital bits to be weighted in their contribution to the output voltage Vout.
For a digital value VAL, of a R-2R DAC of N bits of 0 V/Vref, the output voltage Vout is:
Vout = Vref × VAL / 2N
In the example shown, N = 4 and hence 2N = 16. With Vref = 1.8 V (typical CMOS
logic 1 voltage), Vout will vary between 0000, VAL = 0 and 1111, VAL = 15.
Minimum (single step) VAL = 1, we have
Vout = 1.8 × 1 / 16 = 0.11 volts
Maximum output (1111) VAL = 14, we have
Vout = 1.8 × 14 / 24 = 1.57 volts
Aim: To simulate the schematic diagram of the R-2R digital-to-analog converter, and
then to perform the physical verification for the layout of the same.
Procedure:
1. Retrieve the op-amp symbol from library, and complete the schematic
diagram for the R-2R DAC, as shown. Connect the op-amp as the buffer
amplifier with fallowing specifications.
gpdk180 Polyres R=2k
gpdk180 Polyres R=1k
analoglib Idc Idc=30µ
Pin Names Direction
D0 D1 D2 D3 Input
Vout Output
vdd vss Input
Pin Names Direction
D0 D1 D2 D3 Input
Vout Output
vdd vss Input

2016
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2. Create a symbol for the same, as shown below specifications.Use the
symbol to create the test circuit, with the input signals connected. Select
“vpulse” from analogLib library, with Voltage 1 as 0 and Voltage 2 as 2.
Place four instances of the same to the four inputs, and then edit the
properties of each instance, as follows
Pin Names Direction
D0 D1 D2 D3 Input
Vout Output
vdd vss Input
Input Period Pulse
width
Input Period Pulse
widthD0 10n 5n D1 20n 10n
D2 40n 20n D3 80n 40n
analoglib Vpulse
For V0: v1=0, v2=2, T(Period)=10n , Ton(Pulse width)=5n.
analoglib Vdc Vdd=2.5, Vss=-2.5
Polyres 2kΩ
Polyres 1kΩ

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3. Perform the simulation only for the transient analysis with the Stop time
as 100 ns.

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4. Waveform with D=1111,Vdac=Vmax, D=0000,Vdac=Vmin,

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5. After the simulation, complete the layout and perform the physical
verification.

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EXPERIMENT 14
SAR Based ADC
A successive approximation ADC is a type of analog-to-digital converter that
converts a continuous analog waveform into a discrete digital representation via a
binary search through all possible quantization levels before finally converging upon
a digital output for each conversion. The successive approximation Analog to digital
converter circuit typically consists of four chief subcircuits:
1. A sample and hold circuit to acquire the input voltage (Vin).
2. An analog voltage comparator that compares Vin to the output of the
internal DAC and outputs the result of the comparison to the successive
approximation register (SAR).
3. A successive approximation register subcircuit designed to supply an
approximate digital code of Vin to the internal DAC.
4. An internal reference DAC that, for comparison with VREF, supplies
the comparator with an analog voltage equal to the digital code output of the
SARin.
Aim: To simulate the schematic diagram of the SAR Based ADC, and then to perform
the physical verification for the layout of the same.

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Design Information:
The SAR Based ADC used in this tutorial is a mixed-signal circuit that includes both a
schematic database and verilog code. The analog components include a vsin signal
source, a sample and hold circuit(S/H), a comparator and a R-2R DAC all based on
the schematic. The successive approximation register (SAR) and clock generator are
RTLlevel verilog modules.
• Perform the simulation only for the transient analysis with the Stop time as 30
us.

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VIVA
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Because we can't get full voltage swing with only NMOS or PMOS .We have to use
both of them together for that purpose.
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
nmos passes a good 0 and a degraded 1 , whereas pmos passes a good 1 and bad
0. for pass transistor, both voltage levels need to be passed and hence both nmos and
pmos need to be used.
What are set up time & hold time constraints? What do they signify?
Setup time: Time before the active clock edge of the flip-flop, the input should be
stable. If the signal changes state during this interval, the output of that flip-flop cannot
be predictable (called metastable).
Hold Time: The after the active clock edge of the flip-flop, the input should be stable.
If the signal changes during this interval, the output of that flip-flop cannot be
predictable (called metastable).
Explain Clock Skew?
clock skew is the time difference between the arrival of active clock edge to different
flip-flops’ of the same chip.
Why is not NAND gate preferred over NOR gate for fabrication?
NAND is a better gate for design than NOR because at the transistor level the mobility
of electrons is normally three times that of holes compared to NOR and thus the NAND
is a faster gate. Additionally, the gate-leakage in NAND structures is much lower.
What is Body Effect?
In general multiple MOS devices are made on a common substrate. As a result, the
substrate voltage of all devices is normally equal. However while connecting the
devices serially this may result in an increase in source-to-substrate voltage as we
proceed vertically along the series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1.
Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
we try to reverse bias not the channel and the substrate but we try to maintain the
drain, source junctions reverse biased with respect to the substrate so that we don’t
loose our current into the substrate.
What is the fundamental difference between a MOSFET and BJT ?
In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-
channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes.
BJT is a current controlled device and MOSFET is a voltage controlled device
In CMOS technology, in digital design, why do we design the size of pmos to be
higher than the nmos. What determines the size of pmos wrt nmos. Though this
is a simple question try to list all the reasons possible?
In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons,
the carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS
technology, nmos helps in pulling down the output to ground PMOS helps in pulling

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up the output to Vdd. If the sizes of PMOS and NMOS are the same, then PMOS takes
long time to charge up the output node. If we have a larger PMOS than there will be
more carriers to charge the node quickly and overcome the slow nature of PMOS .
Basically we do all this to get equal rise and fall times for the output node.
Why PMOS and NMOS are sized equally in a Transmission Gates?
In Transmission Gate, PMOS and NMOS aid each other rather competing with each
other. That's the reason why we need not size them like in CMOS. In CMOS design
we have NMOS and PMOS competing which is the reason we try to size them
proportional to their mobility.
What happens when the PMOS and NMOS are interchanged with one another in
an inverter?
If the source & drain also connected properly...it acts as a buffer. But suppose input is
logic 1 O/P will be degraded 1 Similarly degraded 0
Why are pMOS transistor networks generally used to produce high signals,
while nMOS networks are used to product low signals?
This is because threshold voltage effect. A nMOS device cannot drive a full 1 or high
and pMOS can’t drive full '0' or low. The maximum voltage level in nMOS and minimum
voltage level in pMOS are limited by threshold voltage. Both nMOS and pMOS do not
give rail to rail swing.
What’s the difference between Testing & Verification?
Testing is the process of identifying defects in a product. Verification is the process of
ensuring that the product complies with its specification. Validation is the process of
ensuring that the product meets the users' needs. Although linked, these are obviously
separate. A product may be defect free but not what was specified or needed; it may
have defects and be not as specified, but may still meet user need; it may meet
specification, but have defects and not meet the users' need.
What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How
do you avoid Latch Up?
A latch up is the inadvertent creation of a low-impedance path between the power
supply rails of an electronic component, triggering a parasitic structure(The parasitic
structure is usually equivalent to a thyristor or SCR), which then acts as a short circuit,
disrupting proper functioning of the part. Depending on the circuits involved, the
amount of current flow produced by this mechanism can be large enough to result in
permanent destruction of the device due to electrical over stress - EOS
What is slack?
The slack is the time delay difference from the expected delay(1/clock) to the actual
delay in a particular path. Slack may be +ve or -ve.
What is DRC ?What is LVS ?
Design Rule Checking or Check(s) (DRC) is the area of Electronic Design Automation
that determines whether the physical layout of a particular chip layout satisfies a series
of recommended parameters called Design Rules.
The Layout Versus Schematic (LVS) is the class of electronic design automation
(EDA) verification software that determines whether a particular integrated circuit
layout corresponds to the original schematic or circuit diagram of the design.

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What are the differences between SIMULATION and SYNTHESIS ?
Simulation <= verify your design.
synthesis <= Check for your timing
Simulation is used to verify the functionality of the circuit.. a)Functional Simulation:
study of ckt's operation independent of timing parameters and gate delays. b) Timing
Simulation :study including estimated delays, verify setup, hold and other timing
requirements of devices like flip flops are met.
Synthesis: One of the foremost in back end steps where by synthesizing is nothing but
converting VHDL or VERILOG description to a set of primitives(equations as in CPLD)
or components(as in FPGA'S)to fit into the target technology. Basically the synthesis
tools convert the design description into equations or components.
FPGA vs ASIC
Definitions FPGA: A Field-Programmable Gate Array (FPGA) is a semiconductor
device containing programmable logic components called "logic blocks", and
programmable interconnects. Logic blocks can be programmed to perform the function
of basic logic gates such as AND, and XOR, or more complex combinational functions
such as decoders or mathematical functions.
ASIC: An application-specific integrated circuit (ASIC) is an integrated circuit designed
for a particular use, rather than intended for general-purpose use. Processors, RAM,
ROM, etc are examples of ASICs.
Speed ASIC rules out FPGA in terms of speed. As ASIC are designed for a specific
application they can be optimized to maximum, hence we can have high speed in ASIC
designs. ASIC can have high speed clocks.
Cost FPGAs are cost effective for small applications. But when it comes to complex
and large volume designs (like 32-bit processors) ASIC products are cheaper.
Size/Area FPGA are contains lots of LUTs, and routing channels which are connected
via bit streams(program). As they are made for general purpose and because of re-
usability. They are in-general larger designs than corresponding ASIC design. For
example, LUT gives you both registered and non-register output, but if we require only
non-registered output, then it’s a waste of having an extra circuitry. In this way ASIC
will be smaller in size.
Power FPGA designs consume more power than ASIC designs. As explained above
the unwanted circuitry results wastage of power. FPGA won’t allow us to have better
power optimization. When it comes to ASIC designs we can optimize them to the
fullest.
Time to Market
FPGA designs will still take less time, as the design cycle is small when compared to
that of ASIC designs. No need of layouts, masks or other back-end processes. It’s
very simple: Specifications -- HDL + simulations -- Synthesis -- Place and Route (along
with static-analysis) -- Dump code onto FPGA and Verify. When it comes to ASIC we
have to do floor planning and also advanced verification. The FPGA design flow
eliminates the complex and time-consuming floor planning, place and route, timing

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analysis, and mask / re-spin stages of the project since the design logic is already
synthesized to be placed onto an already verified, characterized FPGA device.
ASIC and FPGA design flow diagram:
BOOKS REFERRED
Design, Layout,stimulation,R.jacaob Baker, Harry W Li, David E Boyci, CMOS
Circuit, PHI edn , 2005.
CMOS Mixed Signal Circuit Design(Vol II of CMOS: Circuit design, Layout and
simulation ), R. Jacob. Baker, CMOS-IEEE press and wiley interscience 2002.
Design of analog CMOS integrated circuits, B Razavi, First Edition, Mcgraw Hill
2001
CMOS analog circuit design, P E Allen and D R Holberg , Second Edition , oxford
university press 2002.

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Physical Verification
Assura DRC
Running a DRC
1.Open the Inverter layout form the CIW or library manger if you have closed that.
Press shift – f in the layout window to display all the levels.
2.Select Assura - Run DRC from layout window.
The DRC form appears. The Library and Cellname are taken from the current design
window, but rule file may be missing. Select the Technology as gpdk180. This
automatically loads the rule file. Your DRC form should appear like this
1. Click OK to start DRC.
2. A Progress form will appears. You can click on the watch log file to see the log file.
3. When DRC finishes, a dialog box appears asking you if you want to view your DRC
results, and then click Yes to view the results of this run.
4. If there any DRC error exists in the design View Layer Window (VLW) and Error
Layer Window (ELW) appears. Also the errors highlight in the design itself.
5. Click View – Summary in the ELW to find the details of errors.

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6. You can refer to rule file also for more information, correct all the DRC errors and
Re – run the DRC.
7. If there are no errors in the layout then a dialog box appears with No DRC errors
found written in it, click on close to terminate the DRC run.
Assura LVS
In this section we will perform the LVS check that will compare the schematic netlist
and the layout netlist.
Running LVS
1. Select Assura – Run LVS from the layout window.
The Assura Run LVS form appears. It will automatically load both the schematic and
layout view of the cell.
2. Change the following in the form and click OK.
3. The LVS begins and a Progress form appears.
4. If the schematic and layout matches completely, you will get the form displaying
Schematic and Layout Match.
5. If the schematic and layout do not matches, a form informs that the LVS completed
successfully and asks if you want to see the results of this run.
6. Click Yes in the form LVS debug form appears, and you are directed into LVS

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debug environment.
7. In the LVS debug form you can find the details of mismatches and you need to
correct all those mismatches and Re – run the LVS till you will be able to match
the schematic with layout.
Assura RCX
In this section we will extract the RC values from the layout and perform analog circuit
simulation on the designs extracted with RCX.
Before using RCX to extract parasitic devices for simulation, the layout should match
with schematic completely to ensure that all parasites will be backannoted to the
correct schematic nets.
Running RCX
1. From the layout window execute Assura – Run RCX.
2. Change the following in the Assura parasitic extraction form. Select output type
under
Setup tab of the form.
3. In the Extraction tab of the form, choose Extraction type, Cap Coupling Mode and
specify the Reference node for extraction.

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4. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and Enter Ground
Nets as gnd!
5. Click OK in the Assura parasitic extraction form when done.
The RCX progress form appears, in the progress form click Watch log file to see the
output log file.
5. When RCX completes, a dialog box appears, informs you that Assura RCX run
Completed successfully.
6. You can open the av_extracted view from the library manager and view the
parasitic.

VLSI lab manual Part B, VTU 7the sem KIT-tiptur

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VLSI lab manual Part B, VTU 7the sem KIT-tiptur