Pentium Real Mode.ppt

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Pentium Real Mode
VJTI

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Pentium Real Mode
• Features
• Software model
• MMU addressing mechanism
• Addressing modes and instructions
• Architecture
• Interrupts
• IO addressing

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Pentium Real Mode features
• Operates like a very high
performance 8086
• PCDOS or MSDOS operating system
works in real mode.
• Can access first 1M bytes of
memory(00000 – FFFFF)
• IP is 16 bit.
• Provides two additional segment
registers FS and GS.

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Pentium Real Mode features
• Default mode.
• Provides vector table.
• No protection among segments.
• Segments can be overlapped.
• The size of each segment is 64K bytes.
• Provides 6 active segments.
• 16 bit and 32 bit operands and addressing
allowed.
• Executes 8086, 80286,80386, 80486 and
Pentium instructions except protected
mode instruction.

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Pentium Data types
Byte
0
7
Byte
Low Byte
High Byte
0
7
8
15
Address n
Address n+1
Word
Byte 0
Byte1
Byte2
Byte3
0
7
8
15
16
23
24
31
Address n
Address n+1
Address n+2
Address n+3
Double word
n is even for aligned
n is divisible by 4
for aligned double word

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Pentium Data types
• Bytes, words and double words are
fundamental data types.
• Byte is present in any bank of memory or
IO.
• Byte has unique address.
• A word is formed by using two bytes.
• Each byte in the word has its own address.
Two addresses are acquired by each word.
The address of word is the lower address.
• Hence the number of words to be accessed
by microprocessor is reduced by 2.

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Pentium Data types
• A double word is two contiguous
word starting at any byte address.
• Each byte of a double word has
address.
• Hence each double word acquires
four addresses.
• The lower byte has least address
while higher byte has most address.
• The address of lower byte is the
address of double word.
• The number of double words is
reduced by 4.

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Pentium Aligned and misaligned
words
• Aligned Word.
• Address is always even.
• Lower byte is at lower
address (even) of the
word.
• Higher byte is at higher
address(odd) of the
word.
• Accesses one word within
one bus cycle.
• Bandwidth is very high.
• Lower byte is present on
lower data bus and higher
byte is present on higher
data bus.
• Swapping is not required.
• Misaligned word.
• Address is always odd.
• Lower byte is at lower
address (odd) of the
word.
• Higher byte is at higher
address(even) of the
word.
• Accesses one word in two
bus cycles.
• Bandwidth is reduced.
• Lower byte is present on
higher data bus and
higher byte is present on
lower data bus.
• Swapping is required.

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Pentium Aligned and misaligned
Double words
• Aligned double word.
• Address is evenly divisible
by 4. 1/4th aligned double
word.
• Byte 0 is present on D0-
D7,byte 1 is present on
D8-D15,byte2 is present
on D16 –D23 and byte3 is
present on D24 – D31
data lines.
• Accesses one double
word within one bus
cycle.
• Swapping is not required.
• Misaligned double word.
• Address is not evenly
divisible by 4. 3/4th
misaligned double word.
• Byte 0 is not present on
D0-D7,byte 1 is not
present on D8-D15,byte2
is not present on D16 –
D23 and byte3 is not
present on D24 – D31
data lines.
• Two bus cycles are
required.
• Swapping is required.

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Data Types - Signed
• Handles 8bit ,16 bit, 32 bit signed
numbers.
• Signed numbers are always
represented in 2’s compliment form.
• MSB indicates sign bit

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Data Type BCD
• Handles packed BCD numbers.
• Handles unpacked BCD numbers.
• Unpacked BCD is a byte. Lower nibble is
used to represent value of the BCD (0-9).
Upper nibble must be zero for multiplication
and division and any value for addition and
subtraction. The range of each unpacked
BCD is 0 to 9.
• Packed BCD is a byte. Lower nibble is lower
digit and upper nibble is higher digit. The
range is 00 to 99

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Data Type String
• Contiguous sequence of bytes,words or
double words.
• A string may contain from zero bytes to
232-1 bytes.
• Bit string is contiguous sequence of bits.
A bit string may begin at any bit position
of any byte and may contain up to 232 –1
bits.

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Data Types bit & pointer
• Bit field is contiguous sequence of bits. A
bit field may begin at any bit position of any
byte and may contain up to 32 bits.
• Near Pointer is a 32 bit logical address. Near
pointer is an offset within a segment
• Far Pointer is a 48 bit logical address. It has
two components viz. 16 bit segment selector
and 32 bit offset.

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Pentium software model
• Application programming model
• System programming model
• Software compatibility
• Instruction Set.

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Pentium software model - Real
IP 16 bit
CS 16 bit
DS 16 bit
SS 16 bit
ES 16 bit
FS 16 bit
GS 16 bit
MODULE
CODE
MODULE
DATA
STACK
DATA
STRUCT1
DATA
STRUCT2
DATA
STRUCT3

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IP & Segment Registers
• Instruction pointer is 16 bit (Real mode).
• IP is always used in conjunction with CS to
access instructions.
• Never used as operand register.
• Holds offset address of an instruction.
• Code segment register is used to hold
segment address of an instruction.
• IP value is changed by branch instruction
• CS value is changed by only intersegment
branch instruction, interrupts and
exception.

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Segment registers
• Stack segment register holds segment address
of stack memory.
• All stack operations use SS to locate stack.
• DS, ES, FS, GS are four data segment registers.
• Used to access different data structures.
• Hold segment addresses of data structures.

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General Purpose Registers
AL
AH
AX
EAX
0
7
8
15
16
31
BL
BH
CH CL
BX
EBX
DH DL
CX
ECX
DX
EDX

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General purpose registers
• Used as general purpose registers to store
operands of arithmetic and logical operations.
• Can be used to store result.
• Can be used in data transfer operations.
• Can be used in byte(H &L). 16 bit (X) and 32 bit(E)
operations.
• EAX and EDX are used in multiply and divide
instructions, result correction, load/store flags.
• EAX and EDX are used in IO operations.
• EAX is used in string operations.
• AL and EBX are used in translate operations.
• ECX is used in loop, repeat, rotate and shift
operations.

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General Purpose registers
SP
BP
SI
DI
ESP
EBP
ESI
EDI
0
15
16
31

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General Purpose Register
• ESP is used in conjunction with SS to
access stack in LIFO mode.
• All these registers are used in arithmetic
and logical operations.
• Used to store operands and results.
• All 8 general purpose registers can be
used in offset address calculations.
• All 8 general purpose registers can be
used as base registers.
• All 8 except ESP registers can be used as
Index registers.

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Status Register
• Provides three types of flags viz. status
flags,control flags and machine flags.
• System flags are not available in real
mode.
• Control flags Interrupt Enable,Direction
flag and Trap are available.
• Status flags are Overflow, Sign, Zero, AC,
P and C.

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MMU Real mode
• Provides 1 Mbytes + 64K byte memory
space for an 8086 program.
• Offset address is added into segment
address as shown below
• XXXX0
• +YYYY
• ZZZZZ
• The resulting address has 21 bits.
• There is possibility of carry when the base
address is added to the effective address.
• In 8086 carry bit is truncated. But in
80386,486,Pemtium the carry bit is stored
in bit position 20.

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MMU Real Mode
• 32 bit effective address can be generated
but the value of 32 bit address may not
exceed 65535 without causing an
exception.
• For fully compatibility with 80286 real
mode pseudo protection faults(INT12 or
13) will occur if an effective address is
generated outside the range 0 through
65,535.
• Total number of segments is 16.

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MMU Real Mode
• In default mode, the operand size
and addressing is 16 bit.
• Operand size Prefix and Address size
prefix is required for 32 bit operand
and 32 bit address respectively.

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Pentium stack
• Saves either words or double words not byte.
• Operates in LIFO mode.
• Saves words from higher address to lower
address.
• Reads words from lower address to higher
address.
• SP is always used in conjunction with SS to point
stack.
• Current stack location is called TOP of the stack.
• PUSH, POP,CALL RET, INT use LIFO stack.
• For word operation it increments/decrements SP
by 2. For double word operation it
increments/decrements SP by 4. For high
performance SP should point aligned location.

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Pentium stack
• Base pointer can be used to pass parameters
to the subroutine via stack.
• Base pointer uses stack in random mode.
(Stack frame)
• SP is not affected due to parameter passing.
• Always RAM.
• Can use SP or ESP. But physical address
should not be greater than FFFFFH.

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Stack operation(16BIT)
Stack Top
1
2
3
4
5
6
SP-2
SP-4
SP-6
SP-8
SP-A
SP-C

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Stack operation(32BIT)
Stack Top
1
2
3
4
5
6
SP-4
SP-8
SP-C
SP-10
SP-14
SP-18

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Pentium Instruction format
• The length of instruction varies from 1byte to 14 bytes.
• There are over 100000 variations of machine language
instructions.
• Two types – 16 bit and 32 bit.
• Format consists of Prefixes, opcode, addressing mode,
scaled index, displacement and immediate bytes.
• 16 bit instruction format is used to execute 8086 and 80286
programs.
• 32 bit format is used to execute 80386 and Pentium
programs.
• Operands are located in register, instruction, memory or
IO.
• Many instructions have two or more addressing modes.

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Address size
0-1 byte
Prefix
Operand size
0-1 byte
prefix
Opcode
1-2 bytes
Essential
Addressing
Mode 0-1 byte
Scaled index
0-1byte
Optional
Optional
Displacement
0-4 bytes
Optional
Immediate
0-4 bytes
Optional
Other prefixes may be added

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• Prefixes – These are optional bytes.
• One or more bytes preceding an
instruction that modify the operation
of the instruction.
• Types of prefixes –
• Segment override prefix- overrides
default segment register selection.

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Default Segment register
selection
Memory Segment
register
Selection rule
Instruction CS Automatic with
instruction fetch IP is
used
Stack SS LIFO uses SP. Random
uses BP
Local Data DS All Data memory
accesses except
destination string
Destination
string
ES Destination string

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Segment override prefix
• This prefix byte is used to change the
segment register of data memory except
destination string and stack memory in
random mode.
• Other default segment registers are not
affected like instruction fetch, LIFO stack,
destination string.
• All six segment registers can be used to
access data memory.

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Prefixes
• Address size prefix(67H) switches between
32 bit and 16 bit address generation.
• Operand size prefix(66H)switches between
32bit and 16 bit operands.
• Repeat prefix is used in string operation.
Repeat next instruction until CX becomes
zero.

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Instruction format
• Opcode – Selects the operation
• One or two bytes.
• Opcode table- Higher nibble of opcode byte
selects row of the table while lower nibble
selects column of the table.
• If the first byte of opcode is OFH then
second opcode byte is used to select row
and column of the opcode table.
• Three bits of opcode may be present in
addressing mode byte.

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Opcode
• Format of one byte opcode:
D W
Opcode bits
D =0 R/M is destination and REG is source.
D=1 R/M is source and REG is destination.
R/M and REG are bits of addressing mode byte.
If addressing mode byte is not present then D bit is opcode bit.
W bit is used to select byte,word or double word.
In 16 bit operand size mode, W=0 for byte W=1 for word
In 32 bit operand size mode, W =0 for byte W=1 for double word.

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Opcode for segment register
2bit Sreg2 present in opcode byte while Sreg3 is present in
Opcode field of addressing mode byte.
2 bit Sreg2 format:-
Sreg2 2bit Segment register selected
00 ES
01 CS
10 SS
11 DS

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Opcode for segment register
2bit Sreg2 present in opcode byte while Sreg3 is present in
Opcode field of addressing mode byte.
3 bit Sreg3 format:-
Sreg3 3bit Segment register selected
000 ES
001 CS
010 SS
011 DS
100 FS
101 GS

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Addressing mode byte
• Addressing mode byte indicates type of
addressing mode.
• Indicates location of operands.
• Indicates the way of effective address
computation.
• Indicates source and destination operands.
• Optional.
• Normally not present in implied addressing
mode with special register.
• For Single operand instruction, three bit
field REG is used as opcode field.

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Format
1)Single or No operand:
OPCODE R/M
MOD
2) Two operand:
R/M
REG
MOD

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Format
• MOD (2bit) field indicates whether the
operand is located in register or memory.
• MOD = 11 -> Register, MOD  11-> Memory
• MOD = 00 -> No displacement
• MOD = 01-> 8BIT signed displacement(2’s
complement).
• MOD =10-> 16 BIT unsigned
displacement(16 bit addressing mode).
• 32 BIT unsigned displacement ( 32 bit
addressing mode).

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Format
• REG – Three bit field indicates either
source or destination register
depending upon D bit of opcode in
two operand operation.
• REG indicates name of register.
• Name of register depends upon W bit
of opcode.
• In single or no operand instruction,
REG functions as opcode field.

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REG format
16 bit operand size mode:
REG or
R/M(MOD =11)
W =0 (byte) W=1 (Word)
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

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REG format
32 Bit operand size:
REG or
R/M(MOD =11)
W =0 (byte) W=1 (DWord)
000 AL EAX
001 CL ECX
010 DL EDX
011 BL EBX
100 AH ESP
101 CH EBP
110 DH ESI
111 BH EDI

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R/M Format
• R/M(Register/Memory) is a 3 bit field.
• When MOD = 11 R/M -> Register else R/M ->
Memory.
• When MOD = 11 R/M indicates either source
or destination register, depending upon D
bit of opcode in two operand instruction.
• When MOD = 11 R/M indicates name of
register.
• When MOD = 00, 01 or 10 R/M indicates
effective address computation.

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R/M format
16 bit addressing mode:
R/M MOD =00 MOD =01 MOD =10
000 DS:[BX+SI] DS:[BX+SI+disp8
]
DS:[BX+SI+disp16]
001 DS:[BX+DI] DS:[BX+DI+disp8
]
DS:[BX+DI+disp16
]
010 SS:[BP+SI] SS:[BP+SI+disp8] SS:[BP+SI+disp16]
011 SS:[BP+DI] SS:[BP+DI+disp8
]
SS:[BP+DI+disp16]
100 DS:[SI] DS:[SI+disp8] DS:[SI+disp16]
101 DS:[DI] DS:[DI+disp8] DS:[DI+disp16]
110 DS:[direct] SS:[BP+disp8] SS:[BP+disp16]
111 DS:[BX] DS:[BX+disp ] DS:[BX+disp ]

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R/M format
32 bit addressing mode:
R/M MOD =00 MOD =01 MOD =10
000 DS:[EAX] DS:[EAX+disp8] DS:[EAX+disp32]
001 DS:[ECX] DS:[ECX+disp8] DS:[ECX+disp32
]
010 SS:[EDX] SS:[EDX+disp8] SS:[EDX+disp32]
011 SS:[EBX] SS:[EBX+disp8] SS:[EBX+disp32]
100
scale
d
DS:[base+(
scaleinde
x)]
DS:[{base+(scal
e 
index)}+disp8]
DS:[{base+(scal
e 
index)}+disp32]
101 DS:[direct] SS:[EBP+disp8] SS:[EBP+disp32]
110 DS:[ESI] DS:[ESI+disp8] DS:[ESI+disp32]
111 DS:[EDI] DS:[EDI+disp8] DS:[EDI+disp32]


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Scaled index byte
• Required in scaled indexed addressing
mode.
• Applicable in 32 bit addressing mode.
• R/M = 100 and MOD = 00,01,10.
• Effective address is {base+scale*index}.
• Base value is stored in any 32 bit register.
• Index value is stored in any 32 bit register
except ESP.

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Scale Index Base format
S S
Index Base
SS -> Scale or multiplication factor
SS=00 -> 1
SS=01->  2
SS=10 -> 4
SS=11-> 8

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Base Effective address
000 DS:[EAX+(SCALE  INDEX)]
001 DS:[ECX+(SCALE  INDEX)]
010 DS:[EDX+(SCALE  INDEX)]
011 DS:[EBX+(SCALE  INDEX)]
100 SS:[ESP+(SCALE  INDEX)]
101 DS:[d32+(SCALE  INDEX)] No base
register is selected.
110 DS:[ESI+(SCALE  INDEX)]
111 DS:[EDI+(SCALE  INDEX)]
Format for base field (MOD =00):

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000 DS:[EAX+(SCALE  INDEX)+ disp8]
001 DS:[ECX+(SCALE  INDEX)+ disp8]
010 DS:[EDX+(SCALE  INDEX)+ disp8]
011 DS:[EBX+(SCALE  INDEX)+ disp8]
100 SS:[ESP+(SCALE  INDEX)+ disp8]
101 SS:[EBP+(SCALE  INDEX)+ disp8]
110 DS:[ESI+(SCALE  INDEX)+ disp8]
111 DS:[EDI+(SCALE  INDEX)+ disp8]

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000 DS:[EAX+(SCALE INDEX)+ disp32]
001 DS:[ECX+(SCALE  INDEX)+ disp32]
010 DS:[EDX+(SCALE  INDEX)+ disp32]
011 DS:[EBX+(SCALE  INDEX)+ disp32]
100 SS:[ESP+(SCALE  INDEX)+ disp32]
101 SS:[EBP+(SCALE  INDEX)+ disp32]
110 DS:[ESI+(SCALE  INDEX)+ disp32]
111 DS:[EDI+(SCALE  INDEX)+ disp32]

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INDEX INDEX REGISTER
000 EAX
001 ECX
010 EDX
011 EBX
100 NO INDEX REGISTER 
101 EBP
110 ESI
111 EDI
If Index =100 then SS must be 00 else effective address is
•undefined

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Displacement
• Optional byte.
• If mod =00 or 11, then no displacement.
• If mod =01, the displacement is 8 bit signed. The 8 bit
signed displacement is either +ve or –ve(2’s compliment)
• If mod =10 and 16 bit addressing mode, then the
displacement is unsigned 16 bit(two bytes). This
displacement is always +ve. 1st byte is lower byte.
• If mod =10 and 32 bit addressing mode, then the
displacement is unsigned 32 bit(4bytes). This displacement
is always +ve. 1st byte is lower byte.
• In direct addressing (e.g. r/m =110 and mod =00 and 16 bit
addressing ), the displacement is 16 bit and treated as
offset address. In 32 bit addressing (r/m =100,mod
=00,base =101, the 32 bit displacement is added into scale
indexed.

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Immediate Data
• Present in immediate addressing mode.
• Either byte, word or double word
depending upon w bit and operand size
prefix.
• Can be loaded into register or memory

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Instruction format
• One mnemonic may have two or
more opcodes.
• Two types of instructions viz. single
operand and two operand.
• In two operand either destination or
source must be present in
register(except string instructions).
• The size of source operand must be
same as that of destination operand.

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Addressing modes
• Way of locating operands.
• Operands are located in register,
instruction data memory, stack
memory and IO.
• Indicates the way of effective
address computation.

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Addressing modes
• Three types addressing modes – Data, memory
and IO.
• Data addressing modes- Used to process
operands.
• Used by arithmetic, logical and data transfer
instructions.
• All registers except IP, data memory and stack
memory are used.
• Classified into the following categories- Register,
immediate and memory addressing modes.
• Length of instruction varies from 1 byte to 14
bytes.

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Register addressing modes
• In one operand instruction, operand is
located in register.
• Used in arithmetic,logical and data
transfer operations.
• The operand is 1byte,2bytes or 4 bytes.
• In two operand instruction, both operands
are located in registers.
• The mod = 11 .
• Two types of formats – one operand and
two operands.

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One operand
• Opcode is 1 byte or 2 bytes.
• Length of instruction varies from 1 byte to 3 bytes.
• Two types short and long instructions.
• Short instruction contains only opcode.
• Long instruction contains addressing mode byte.
• In Addressing mode byte OPCODE field is used
instead of REG field.
• The R/M field indicates register(Long).
• Opcode byte indicates register(short).

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Two operand
• D bit of opcode indicates source and
destination.
• The length of instruction from 2 byte or 3 byte.
• Addressing mode byte is always present.
• R/M indicates source or destination register.
• REG field indicates destination or source
register.
• Segment register and data registers are
distinguished by opcodes.
• Segment register opcode has no w bit.

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Registers
Operand size
Register
Byte Word Dword
Accumulator AL,AH AX EAX
Base BL,BH BX EBX
Count CL,CH CX ECX
Data DL,DH DX EDX
Stack pointer SP ESP
Base Pointer BP EBP
Source index SI ESI
Destination
Index
DI EDI
Code Segment CS
Data segment DS
Stack
Segment
SS
E segment ES
F segment FS
G segment GS

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Immediate addressing modes
• Operand (source)is specified by instruction itself.
• Operands(source) are stored in program or code
memory.
• Operand is fetched into instruction byte queue.
• Destination operand is either register or memory.
• Destination register has two forms viz. short and long.
• Short has no addressing mode byte while long has
addressing mode byte.
• Opcode is one or two byte.
• Data is 1 byte, 2 bytes or 4 bytes.
• Addressing mode byte is present for memory.
• The address of destination memory is determined by
memory addressing modes.

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Memory addressing modes
• Operand is located in data or stack memory.
• In two operand instruction at least one operand
must be present in register.
• D and W bits are used in two operand instruction.
• Addressing mode is always present.
• Mod = 00,01,10.
• Effective address depends upon Mod and R/M
values.
• Register is indicated by REG field and Memory
location is indicated by R/M field.
• Divided into following categories:- direct, register
indirect, based relative, indexed, based plus
indexed, based relative plus indexed, scaled
indexed and based plus scaled indexed, based

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Direct addressing mode
• Offset address of memory(data memory in default
mode) is indicated by instruction itself.
• In 16 bit addressing mode, mod = 00 and R/M =
110.
• In 32 bit addressing mode, mod =00 and R/M =
101.
• In 16 bit addressing mode, offset address is 16 bit
while in 32 bit addressing mode, offset address is
32 bit.
• REG field indicates source or destination register.
• Opcode(1-2 bytes)+addressing mode byte+offset
address(2 or 4 bytes).
• Stack memory can be accessed in random mode.

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Register Indirect addressing modes
• The offset address of data or stack memory is
stored in a register.
• Stack memory can be accessed in random and
LIFO modes.
• In LIFO mode, the SP or ESP is used in
conjunction with SS.
• In 16 bit addressing mode, BX, SI, DI and BP can
be used as a pointer. It is used to access single
data structure and one dimensional.
• In 32 bit addressing mode, EAX, EBX, ECX, EDX,
ESI and EDI can be used as pointers.
• Mod =00 R/M is 100,101(16 bit) and Mod =00 R/M is
000,001,010,011,110,111(32 bit).
• Opcode( 1 or 2 bytes) + addressing mode byte.

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Based relative addressing modes
• Base register is used to hold base address of data
structure.
• Displacement selects element within data structure.
• Effective address is contents of Base register +
displacement( 8 bit, 16 bit or 32 bit).
• Base register value is fixed and displacement is changed
to access new element.
• Mod = 01 or 10.
• In 16 bit addressing mode, BX, BP, SI and DI registers are
used as base register.
• In 32 bit addressing mode, EAX, EBX, ECX, EDX, EBP, ESI
and EDI registers can be used (without SIB byte)
• Can be used to implement linked list and one dimensional
array(multiple).
• Opcode(1-2 bytes)+addressing mode byte+disp(1.2.4
bytes)

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Based relative addressing modes
Element 0
Element 1
Element 2
Element 3
Element 4
------------
Element n-1
BASE register
Displacement
Displacement
Displacement
Displacement
Displacement

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Indexed register addressing
• In indexed register, the displacement value is used
as a pointer of array(i.e. displacement is fixed.)
• Contents of index register can be changed to point
new element.
• Used to implement one dimensional array.
• In 16 bit addressing mode, BX, BP, SI and DI
registers can be used as index registers.
• In 32 bit addressing mode, EAX, EBX, EDX, ECX,
EBP, ESI and EDI registers can be used as index
registers.
• Displacement is 1 byte, 2bytes or 4 bytes.
• Opcode(1-2bytes)+ addressing mode byte+
disp(1,2,4 bytes).
• Mod =01 or 10.

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Indexed addressing modes
Element 0
Element 1
Element 2
Element 3
Element 4
------------
Element n-1
DISP.
Index register
Index register
Index register
Index register
Index register

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Based + Indexed
• The effective address is contents of base register
and Index register.
• Used to access single, two dimensional array.
• In 16 bit addressing mode, BX+SI, BX+DI, BP+SI,
BP+DI registers are used.
• In 32 bit addressing mode, it is implemented using
scaled indexed.(with SIB byte).
• Mod =00, R/M =000, 001, 010, 011.
• Row is pointed by base register and column is
pointed by index register.
• Opcode (1-2 bytes) + addressing mode byte.

pbborole 75
Based + Indexed
BASE
BASE
BASE
BASE
MATRIX

pbborole 76
Based relative +indexed
• Used to access multiple two dimensional arrays.
• The displacement indicates starting address of
data structure or two dimensional array.
• Displacement is fixed and base register is used to
point row and index register is used to point
column of the matrix.
• Mod = 01 or 10 and R/M is 000, 001, 010, 011.
• In 16 bit addressing mode, BX+SI, BX+DI, BP+SI,
BP+DI registers are used.
• In 32 bit, it is implemented by using scaled
index(with SIB byte.
• Opcode(1-2 bytes)+addressing mode +disp(1,2
bytes or4 bytes).

pbborole 77
Based relative+ Indexed
BASE
BASE
BASE
BASE
MATRIX 1
DISP
1

pbborole 78
Scaled Indexed direct
• 32 bit addressing mode only with R/M = 100.
• Contents of Index register are multiplied by
scale factor(1, 2, 4, 8).
• SIB byte is required.
• In scaled indexed direct, scaled indexed
value is added into 32 bit direct offset
address.(mod =00) and base value of SIB
byte =101.
• Base register is not present.
• Opcode(1-2 bytes)+addressing mode
byte+SIB byte+Direct address(4bytes).

pbborole 79
Based +scaled index
• 32 bit addressing mode only.
• Contents of Index register are multiplied by scale
factor(1, 2, 4, 8).
• Mod =00 and R/M =100.
• The effective address is [base]+[scale  Index].
• Base registers are EAX, EBX, ECX, EDX, ESI, EDI,
ESP.
• Index registers are EAX, EBX, ECX, EDX, ESI, EDI,
EBP.
• Used to implement single two dimensional array.
• Opcode(1-2 bytes) + addressing mode byte+ SIB
byte.

pbborole 80
Based relative +scaled index
• 32 bit addressing mode only.
• Contents of Index register are multiplied by scale factor(1,
2, 4, 8).
• Mod =01 or 10 and R/M =100.
• The effective address is [base]+[scaleIndex]+disp.
• Displacement is either 1byte or 4 bytes.
• Base registers are EAX, EBX, ECX, EDX, ESI, EDI, ESP.
• Index registers are EAX, EBX, ECX, EDX, ESI, EDI, EBP.
• Used to implement multiple two dimensional arrays.
• Opcode(1-2 bytes) + addressing mode byte+ SIB
byte+disp(1 or 4 bytes).

pbborole 90
Stack memory(LIFO) addressing
modes
• In LIFO mode, the Pentium provides only one
addressing mode for stack operand( source or
destination) viz. Register Indirect.
• The other operand is register, data memory or
immediate.
• In this mode, the offset address of stack is stored
in SP or ESP.
• The segment address is always stored in SS.
• Used by PUSH and POP instructions.
• If operand is 16 bit, then decrements SP by 2. If
operand is 32 bit, then decrements SP by 4.

pbborole 93
Branch or code addressing mode
• Used by branch instructions only.
• Used to modify contents of IP and CS.
• Not used in arithmetic, logical and data
transfer operations.
• Two types of instructions viz. Unconditional
and conditional.
• Two types of addressing modes viz.
Intrasegment and Intersegment.
• The address of new program is located in
register, data memory, stack memory and
instruction.

pbborole 94
Intrasegment
• The value of IP is changed
• The value of CS is not changed.
• Branch within a segment.
• Branch in flat model.
• Types – Relative, register indirect,
memory indirect.
• Applicable to all branch instructions.
• Called near control transfer.

pbborole 95
Relative addressing
• Also called PC relative.
• Program is relocatable.
• Displacement value is added into IP or EIP.
• IP or EIP value is corrected before adding
displacement because some instructions after
branch are prefetched. As a result IP is
incremented.
• Displacement calculation is done by assembler
itself.
• Two types of labels are used viz. short and near.
• In short, the displacement is 8 bit signed.
• In Near, the displacement is 16bit unsigned(if
operand size is 16 bit) or 32 bit signed( if operand
size is 32 bit).

pbborole 96
Relative addressing modes
• The signed displacement is represented in
2’s complement form.
• The range of 8 bit signed displacement is –
128 to + 127 bytes.
• The range of 16 bit signed displacement is
32k bytes.
• The range of 32 bit signed displacement is
2G bytes.
• For forward jump, the displacement is +ve.
• For backward jump, the displacement is –
ve.
• Displacement = Address of jump location
 Address of next instruction.

pbborole 97
Register indirect
• The offset address of jump location is
stored in register[16 bit or 32 bit].
• Offset address is loaded into IP/EIP directly.
• Not applicable to conditional branch.
• Program is not relocatable.
• The length of instruction is short.
• Mod =11.

pbborole 98
Memory Indirect
• The offset address is stored in data memory
or stack memory (random).
• The offset address is loaded into IP/EIP.
• Program is not relocatable.
• The length of instruction is short.
• The mod = 00,01,10.
• 16 bit or 32 bit addressing is used to locate
memory location.

pbborole 99
Intersegment
• Uses segmentation model.
• Contents of CS and IP/EIP are
modified.
• Offset address is loaded into IP/EIP
and segment address is loaded into
CS.
• Branch between segments.
• Called far control transfer.
• Types – direct or indirect.

pbborole 100
Direct and indirect
• The offset address is 16 bit or 32 bit.
• In direct, the offset address is 2nd and 3rd
bytes and the segment address is 4th and 5th
bytes (16bit offset).
• In direct, the offset address is 2nd ,3rd ,4th
and 5th bytes and segment address is 6th
and 7th bytes.
• In indirect, the offset address(16 bit or 32
bit) and segment address are stored in data
memory or stack memory.
• Mod = 00,01,10 , Mod =11 is invalid.

pbborole 101
IO addressing Modes
• Used to access IO ports.
• Destination or source register is AL, AX or EAX.
• Two types – Direct or Indirect.
• Direct – The address of IO port is 8 bit. The
address of IO port is specified by instruction itself.
• In direct mode, it can access 256 – 8bit IO
ports,128 –16 bit IO ports and 64 bit IO ports.
• In indirect addressing mode, the address of IO
port is stored in DX.
• In indirect addressing mode, it can access 64K- 8
bit IO ports, 32K – 16 bit IO ports and 16K – 32 bit
IO ports.

Pentium Real Mode.ppt

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