Performance Terminology and models computer architecture
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The document outlines a computer architecture course (EE3213), covering topics such as processor performance, microprocessor trends, memory capacity, and performance terminology. It discusses instruction set architecture (ISA) classifications, the effectiveness of RISC versus CISC designs, and the principles of pipelining within processor design. Key examples include calculating cycles per instruction (CPI) and addressing modes in different architectures.
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Performance Terminology and models computer architecture
- 11. The Bottom Line: Performance and Cost
- 14. Make the Common Case Fast
- 19. Cost vs. Price
- 20. Cost vs. Price
- 21. Cost vs. Price
- 22. Cost vs. Price
- 23. Evolution of Instruction Sets
- 24. Design Space of ISA
- 26. Stack Machines
- 27. The Case Against Stacks
- 29. Complex instruction set computer: CISC
- 32. Pipelining
- 34. Pipelined Laundry Start work ASAP
- 36. 5 Steps of the DLX Datapath
- 37. 5 Steps of the DLX Datapath
- 38. 5 Steps of the DLX Datapath STALL
- 39. 5 Steps of the DLX Datapath STALL
- 40. Example: STALL