Project presentations model VLSI Domain
- 1. GenAI-2024-2025-B6 Fir filter using cadence for 16 bit 2024 - 2025 Filter using Cadence tools is a comprehensive process that typically involves several stages, from initial specifications to simulation and optimization. GenAI-2024-2025-B6-00X
- 2. GenAI-2024-2025-B2 MUTHUKUMAR.P IV ECE B SNS College of Technology Filter Design Engineer MUGUNDHAKUMA R.S IV ECE B SNS College of Technology RTL Design Engineer MOHANDAS.C.S IV ECE B SNS College of Technology Verification Engineer MOHAMMED FAZAL.N IV ECE B SNS College of Technology Physical Design Engineer BHUVANESHWARI. M DT Mentor KANMANI.R Technology Mentor Student Team Faculty Team Information 16bit cadence fir GenAI-2024-2025-B2-00X RAJA.S Project Guide
- 3. GenAI-2024-2025-B2 Requirement / Problem statement The filter must support real-time processing, meeting timing, power, and area constraints suitable for ASIC/FPGA deployment, using Cadence tools to process digital signals with high accuracy. Scope The FIR filter's scope extends from theoretical research to practical deployment in advanced digital systems. Key factors & features Hardware Optimization,16-bit Fixed-Point Arithmetic,Optimization Features,Simulation and Verification. Target Audience Domain Designing a 16-bit FIR filter using Cadence tools involves creating an efficient digital signal processor with fixed-point precision. electronics, DSP algorithms, and hardware design optimization. GenAI | AI By leveraging GenAI in conjunction with Cadence tools, FIR filter design becomes faster,more efficient,ensuring accuracy and adherence to stringent performance requirements. Description A 16-bit FIR filter designed using Cadence tools implements digital signal processing with fixed-point precision. The filter processes signals using multiply-accumulate (MAC) operations and shift registers, ensuring accurate frequency response. Cadence tools like Genus,Xcelium,and Innovus are used for synthesis, verification, and physical design, optimizing for performance, area, and power. Project Overview 16bit cadence fir GenAI-2024-2025-B2-00X
- 4. GenAI-2024-2025-B2 Project Features / Journeys • Supports different filter types (low-pass, high-pass, band-pass, band-stop) with specified cutoff frequencies and filter orders. • Introduces pipelining to improve throughput and reduce critical path delays in high-order filters. • Develop Verilog/VHDL for shift registers, MAC units, and overall filter architecture in Cadence Genus. • Use MATLAB or Python to compute and quantize 16-bit coefficients for the FIR filter. • This journey ensures a systematic approach, from specification to deployment, while leveraging Cadence tools for an optimized and robust FIR filter design. Project Features 16bit cadence fir GenAI-2024-2025-B2-00X
- 5. GenAI-2024-2025-B2 Technology Stack 16bit cadence fir GenAI-2024-2025-B2-00X Presentation Layer • MATLAB or an FPGA setup Source Code Project code repository is available at Link Note: Artefacts locations are provided as clickable hyperlink available as “Link” Methodology Design the filter coefficients,fixed point representation,circuit implementation in cadence. Application Layer • Visualization Data Layer • Datapath Products, Tools & Utilities Cadence virtuose for circuit design,MAT LAB for design and optimization. Infrastructure Use a workstation with Cadence software installed.If deploying on FPGA, use development kits like Xilinx Zynq or Intel Cyclone. API Provide details of APIs used with source URL
- 6. GenAI-2024-2025-B2 Wireframe | UI 16bit cadence fir GenAI-2024-2025-B2-00X Wireframe | UI
- 7. GenAI-2024-2025-B2 Application Screenshots 16bit cadence fir GenAI-2024-2025-B6-00X Application Screenshots Provide journey / stories / use case wise screenshots of your application, live demo is available as Video as part of the project artefacts
- 8. GenAI-2024-2025-B2 Project / Product Roadmap 16bit cadence fir GenAI-2024-2025-B2-00X Short Term Mid Term Long Term • Ensure the filter is designed for the target 16-bit resolution, which may affect precision and implementation. • Simulate the filter's frequency response to verify that the filter meets the desired specifications in terms of cutoff frequency, attenuation, and other key parameters. • Improve Quantization Error Management: At this stage, focus on minimizing quantization noise and rounding errors introduced by representing the filter coefficients and signal in 16 bits. • Ensure that the FIR filter design can adapt to emerging technologies, such as newer hardware platforms, improved signal processing techniques, or new software tools. • Stay informed about advancements in hardware (e.g., FPGAs, ASICs). Project / Product Roadmap | Milestones | Features
- 9. GenAI-2024-2025-B2 Artefacts 16bit cadence fir GenAI-2024-2025-B2-00X Project Portal Project Portal / website is available at Link Source Code Project code repository is available at Link Note: All links are provided as clickable hyperlink available as “Link” Technical Document / Specification Project technical document / specification are available at Link Presentation Project presentation (this document) is available at Link Requirement Document / Specification Project requirement document / specification is available at Link Wireframe | UI Project wireframe / UI designs are available at Link Application Application is available at Link DT Playbook Project DT Playbook is available at Link Overview Video Project overview video is available at Link Video provides project overview, presentations, journey wise Wireframe, UI, application demo as required and as applicable.
- 10. GenAI-2024-2025-B2 Thanks 16bit cadence fir GenAI-2024-2025-B2-00X Thanks