Revathi Resume L& T
- 1. RESUME REVATHI.M 536,VSV Nagar, Singarapettai ( Post), Uthangarai (TK), : revathi.m333@gmail.com Krishnagiri (DT), : 088072-66774 TamilNadu-635307. Career Vision: To work in a challenging environment demanding all my skills and efforts to explore and adapt myself in different fields and realize my potential where I get the opportunity for continuous learning. Career Summary: SEP 2015 Working as a Assistant Professor in Electronics and Communication Department- Shreenivasa Engineering College. Duration of 6 months - till date. From SEP 2013- DEC 2014, Worked as Software Trainee in CADD Centre Services. Responsibilities Handled: Trained students in EDA tools and also conducted practical sessions at CADD centre Duration of 1 year and 4 months. Testing and Designing of circuits using ORCAD 9.1. Strong Expertise on in EDA Tools: Mentor Graphics Pyxis & Cadence Spectre Handled Workshop on Mentor Graphics - Pyxis & Eldo Exposure on FPGA Design tools such as Xilinx Electronics and Circuit design lab incharge Have involved in develop VHDL Coding and Test bench for designing a router in NOC Software skill set: Simulation Software : Cadence 6.1.5 version (Spectre, Virtuoso), Microwind, Tanner EDA v13.0 Synthesis Tool : Synopsys VCS and Design Compiler (90nm technology) FPGA Tool : Xilinx ISE 9.1i FPGAs : Xilinx SPARTAN 3E Layout Editor : Cadence 6.1.5 version (Virtuoso) Pre Layout Simulator : Mentor Graphics (Pyxis) Post Layout Simulator : Mentor Graphics (Eldo) DRC/LVS Tool : Caliber Board Design Tool : Orcad Programming Language: VHDL & Verilog coding
- 2. Projects Overview: 1. Design of Adaptive Link and Elastic Buffer for Low Power Network On Chip Architecture Team Size & Duration: 2 & 4 months Software Used: Modelsim 5.5e, Synopsys Design Compiler Description: The Virtual Channel with 1024 bits is implemented through Modelsim 5.5e and Synopsys design compiler at 90nm technology. Through this design, the net switching power is about 190mW. The proposed approach is specifically focused on reducing the power dissipated by router. 2. Design of Dual and Swing Restored Complementary Pass Transistor Logic for Low Power Ripple Carry Array Multiplier Team Size & Duration: 4 & 6 months Software Used: Cadence Virtuoso at 180 nm technology Description: An alternative internal logic structure for designing Ripple Carry Array Multiplier is introduced. The usage of the DPL in RCAM definitely leads to reduction in number of transistor and static power consumption. Academic Profile: 2013-2015 M.E. -VLSI DESIGN with 9.62 CGPA (First Class with Distinction) KSR college of engineering, Anna University, Chennai. 2009-2013 B.E. – ELECTRONICS AND COMMUNICATION ENGG.with 8.24 CGPA. (First Class) Vel Tech Multitech Dr. RR & Dr.SR engineering college, Anna University,Chennai. 2009 HSC with 92.66% Sri Vidyamandir matriculation higher secondary school, Uthangarai. 2007 SSLC with 90.36% Christ matriculation school, Singarapettai. Academic Project Guided: Design of CMOS PWM Transceiver Using Self-Referenced Edge Detection Design of Low Power Adiabatic logic circuit for Comparator Achievements: Received Prize in Second International Conference on EEECOS-2015. B1 Grade in British Council Preliminary Level Exam (University of Cambridge). Achieved Certificate of Merit award (University Topper in PG).
- 3. Extra-curricular activities: Member of IEEE 2013-2016. Acted as a Placement and Training Coordinator. Co-Curricular Activities: Participated in one day workshop on VLSI Design using Cadence tool suite in Kongu Nadu College of Engineering, Namakkal Attended two days workshop on Advanced Topics in VLSI Circuit Design in IIT, Roorkee Participated in Cadence Design Contest 2013 in Bangalore Attended a Seminar on Topic Free Software, Freedom and Education in IIT, Chennai Personal Profile: Father’s Name : K.Manivannan Mother’s Name : M.Kalyani Date of Birth : 05.03.1992 Gender : Female Marital Status : Single Languages Known : English (R W S), Tamil (R W S) I hereby declare that all the information and facts stated above are true and correct to the best of my knowledge and belief and I will take the entire responsibility if any discrepancy is found. Reference: Dr. K.Paramasivam, M.E.,Ph.D., Head of the Department, ECE Karpagam College of Engineering, Coimbatore kp_sivam@yahoo.com, 9942989881 PLACE: Singarapettai DATE : 29.03.2016 M.REVATHI