Thermal and mechanical stress modelling of smart power switches under active loading ANSYS
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The document discusses thermal and mechanical stress modeling of smart power switches, highlighting that 65% of reliability issues stem from thermo-mechanical loads. It covers various failure mechanisms due to induced thermal loads, such as temperature delamination and metal degradation, while emphasizing the necessity of experimental validation and multi-physics simulations. Key challenges include structural complexity, material matrix, and computational efforts in predictive modeling.
Thermal and mechanical stress modelling of smart power switches under active loading ANSYS
- 1. Thermal and mechanical stress modelling of smart power switches under active loading Bala Karunamurthy, KAI, Villach. ACUM’14. Vienna
- 3. 65 % of reliability issues are due to Thermo-mechanical loads (M Glavanovics, KAI: ESSDRC 2004) Stressed and Unstressed DMOS
- 4. Thermally induced loads cause failures Electric pulses generate temperature Delamination, cracks, voids, excessive plastic deformation, metal crawling etc. Metal Extrusion & Cracks (T Smorodin, Infineon: ESSDRC 2007) (W Kanert, Infineon: Journal of Microelectronics Reliability 2012) Metal Degradation
- 5. Si Ingot Slicing Deposition/Etching Chip Dicing Die Attach Moulding Chris Welham, Coventor Inc. Images: APCMag
- 6. How can we test a design/product? Testing Vs Service conditions Fundamental understanding 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 A B C D CTF Design 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 A B C D CTF Design -40 to +150 C 0 to +80 C Prof Peter Borgesen
- 7. Stress induced voiding (SIV) – process of diffusion and concentration of vacancies to form voids Flux, in atoms per unit area per time, Mobility ; Where, Driving Force Flux , kT D M r F H kT Q eDD 0 N i i Hi i kT Q r VeD kTAC J 1 0 . FMCAJ
- 8. Where does the stress come from? E1, ν1, α1 E2, ν2, α2 1. INTRINSIC: Film nucleation and coalescence 2. EXTRINSIC: CTE mismatch E2, ν2, α2 E1, ν1, α1 Heat
- 9. Wafer Fabrication Die Attach Moulding Temperature cycling 0 100 200 300 400 500 600 700 800 900 1000 1 2 3 4 5 6 7 8 9 10 Temperature(C) Process Steps 1 2 3 4 Activate and deactivate element Use ANSYS “Birth & Kill” Feature
- 10. The 5 Challenges 1. Structural complexity 2. Material Matrix 3. Multi-scale & Multi-physics 4. Computational Effort 5. Experimental Validation (B Karunamurthy, KAI: Journal of Microelectronics) (S Eiser, KAI)
- 11. Elastic, Elastic-Plastic, viscoelastic and visco- plastic behaviour Interface strength Temperature dependent Strain-rate dependency Micro tensile experiments Nanoindendation 4-point bending Wafer curvature measurement Lap shear and HCF/LCF Testing ANSYS Input: BKIN, MKIN, Chaboche, Anand, Prony series etc. or USER MAT What we need? Methods used
- 12. (V Kosel, KAI: 2011) (G Kravchenko, 2011) El.Therm Simulations 0 50 100 150 200 250 300 350 400 450 1 2 3 4 5 6 Power Time (s)
- 13. σxy σyz σxz ¼ of Chip- package Die, Die attach & Lead frame In-plane (σxy) and out-of-plane (σxz and σyz) on a chip
- 14. 70 um Silicon Mould Compound Sub Model Silicon Silicon Mould Compound Lead Frame Just one surface: Half-a-million elements! Nested Sub-Modelling Homogenization Technique Micro Model 1 2 3
- 15. (B Karunamurthy, KAI: Techconnect, Washington 2013) Stress peak regions correspond to failure sites Fracture mechanics simulations Crack and simulated stress state
- 17. Acknowledgements: Funding bodies: (FFG, Project no. 831163) and the Carinthian Economic Promotion Fund (KWF, Contract KWF-15212274134186). KAI & Infineon Technologies AG.
- 18. © CADFEM 2014 Produkte, Service und Wissen aus einer Hand Denn Simulation ist mehr als Software CADFEM (Austria) GmbH Wagenseilgasse 14 1120 Wien Tel. +43 (0)1 587 70 73 – 0 E-Mail. info@cadfem.at Web. http://www.cadfem.at • http://blog.cadfem.at
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