Unit 3 mpmc

UNIT III I/O INTERFACING
Memory Interfacing and I/O interfacing -
Parallel communication interface – Serial
communication interface – D/A and A/D
Interface - Timer – Keyboard /display
controller – Interrupt controller – DMA
controller – Programming and applications
Case studies: Traffic Light control, LED display ,
LCD display, Keyboard display interface and
Alarm Controller.
5/25/2021
Kongunadu College of Engineering and
Technology(Autonomous)
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MEMORY INTERFACING AND
I/OINTERFACING
Memory Interfacing
• While executing a program, the microprocessor
needs to access memory frequently to read
instruction code and data stored in memory; the
interfacing circuit enables that access.
• the microprocessor initiates a set of signals when it
wants to read from and write into memory.
• The primary function of memory interfacing is that
the microprocessor should be able to read from and
write into a given register of a memory chip.
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I/O Interfacing
• The Input/Output devices such as keyboards and
displays are the communication channels to the
outside world.
• Latches and buffers are used for I/O interfacing.
• They once hardwired, perform only one function
(either as input device if it is buffer and as output
device if it is a latch). Thus limiting their capabilities.
• To improve the overall system performance the Intel
has designed various programmable I/O devices.
• Along with the I/O functions, they can perform many
other functions such as time delays, counting and
interrupt.
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• The programmable peripheral device is a
combination of many devices on a single chip.
• The advantage of programmable device is that
they can be set up to perform specific
functions by writing a code in its internal
register.
• As this code controls the function of the
programmable device, it is called control word
and the register in which it is stored internally
is called control register.
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Some of the peripheral devices developed by
Intel for 8085/8086/8088 based system are:
• 8255 - Parallel Communication Interface
• 8251 - Serial Communication Interface
• 8254 - Programmable Timer
• 8279 - Keyboard / Display Controller
• 8257 - DMA Controller
• 8259 - Programmable Interrupt Controller
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The microprocessor can communicate with external
world or other systems using two types of
communication interfaces. They are:
• Serial Communication Interface
• Parallel Communication Interface.
Serial Communication Interface
• The serial communication interface gets a byte of data
from the microprocessor and sends it bit by bit to the
other system serially or it receives data bit by bit
serially from the external system, then it converts the
data into bytes and sends to the microprocessor.
Parallel Communication Interface
• A parallel communication interface gets a byte from
the microprocessor and sends all the bits in that byte
simultaneously (parallel) to the external system and
vice-versa.
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PARALLEL COMMUNICATION INTERFACE
(8255 A - Programmable Peripheral Interface)
• The 8255A (PPI) interfaces peripheral I/O devices to the
microcomputer system bus.
• It is programmable by the system software.
• Peripheral devices: Printers, keyboards, displays, floppy
disk controllers, CRT controllers, machine tools, D-to-A and
A-to-D converters, etc are connected to the
microprocessor through the 8255A port pins.
• It has a 3-state bi-directional 8-bit buffer which interfaces
the 8255A to the system data bus.
• It has 24 programmable I/O Pins.
• It reduces the external logic normally needed to interface
peripheral devices.
• It is also called as Parallel Communication Interface.
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• It can be operated in two basic modes:
Bit Set/Reset Mode
I/O Mode
• I/O mode is further divided into 3 modes:
Simple I/O mode (Mode 0)
Strobed I/O mode (Mode 1)
Bidirectional Data Transfer mode (Mode 2)
• It has two 8 bit ports: Port A, Port B, and two 4 bit
ports: CUPPER and CLOWER.
• Available in 40-Pin DIP and 44-Pin PLCC.
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Pin diagram of 8255A
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Block Diagram of 8255A
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The 8255 consists of Four sections namely
• Data Bus Buffer
• Read/Write Control Logic
• Group A Control
• Group B Control
Data Bus Buffer
• This is a tri-state, bi-directional data bus used to
interface the internal data bus of 8255A to the
system data bus of 8086.
• Using IN or OUT instructions, CPU can read or write
the data from/to the data bus buffer.
• It can also be used to transfer control words and
status information between CPU and 8255A.
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Read/Write Control Logic
I/O Port Addresses
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Group A Control and Group B Control
• To execute peripheral data transfer, three 8-bit ports are
provided in 8255A i.e. ports A, B and C. For the purpose of
programming 8255A, these ports are grouped as follows.
• Group A : Port A and Most Significant Bits (MSB) of
Port C (PC4 – PC7)
• Group B : Port B and Least Significant Bits (LSB) of
Port C (PC0 – PC3)
• Port A: One 8-bit data output latch/buffer and one 8-bit
input latch buffer.
• Port B: One 8-bit data input/output latch/buffer.
• Port C: One 8-bit data output latch/buffer and one 8-bit
data input buffer. This port can be divided into two 4-bit
ports and it can be used for the control signal outputs and
status signal inputs in conjunction with ports A and B.
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Operating Modes
• Bit Set/Reset (BSR) mode
• I/O Mode
• D7 bit of control word decides the type of
mode. If it is “1”, I/O mode is selected. If it is
“0”, BSR mode is selected.
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I/Omode
• The I/O mode is divided into three modes Mode 0, Mode
1 and Mode 2 as given below.
• Mode 0 – Basic I/O Mode
• Mode 1 – Strobed I/O Mode
• Mode 2 – Bi-directional data transfer mode
• Bits (D0 – D2) of the control word define modes of ports
belonging to Group B. Bits D3 – D6 define modes of Group
A ports.
• Bit D7 must be 1 to indicate that the byte is being written
for I/O mode.
• The ports acts as input when D0, D1, D3 and D4 are set to 1.
The ports acts as output when D0, D1, D3 and D4 are set to
0.
• 8255A would be interfaced to the 8085/8086 using I/O
mapped I/O mode.
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Mode 0 – Basic I/Omode
• The features of Mode 0 are :
• Two 8-bit ports (Port A, Port B) and two 4-bit ports (Port CU, Port CL).
Any port can be input or output.
• Outputs are latched.
• Inputs are not latched.
• 16 different Input/Output configurations are possible in this mode. A
typical example is shown in fig.
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Mode 1 - Strobed Input/Output
• In this mode, handshake signals are exchanged
between the microprocessor and peripherals prior to
data transfer.
• The features of mode 1 are :
• Two Groups (Group A and Group B).
• Each group contains one 8-bit data port and one 4-bit
control/data port. The 8-bit data port can be either
input or output
• The 4-bit port is used for control and status of the 8-bit
data port.
• If Port A is in mode 1 (input), then PC3, PC4, PC5 are
used as control signals. If Port B is in mode 1 (input),
then PC0, PC1, PC2 are used as control signals.
• Both inputs and outputs are latched.
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Mode 1 : Input Configuration
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• STB (Strobe Input) – A “low” signal on this pin indicates
that the peripheral
device has transmitted a byte of data. The 8255A in
response to STB , generates IBF and INTR.
• IBF (Input Buffer Full) – A “high” signal issued by
8255A is an acknowledge to indicate that the input
latch has received the data byte. This is reset when the
CPU reads the data.
• INTR (Interrupt Request) – This is an output signal,
used to interrupt the CPU. This will be in active state
when STB , IBF and INTE (internal Flip-Flop) are all at
logic 1. This will be reset by the falling edge of RD
signal.
• INTE (Interrupt Enable) – This is an Internal Flip-Flop
used to enable or disable the generation of INTR signal.
There are two Flip-Flops INTEA and INTEB are set/reset
using the BSR mode.
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Mode 1 : Output Configuration
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• OBF (Output Buffer Full) – A “low” output signal indicates
that the CPU writes data in to the output latch of the
8255A. This signal also indicates to an output peripheral
that new data are ready to be read. It goes high again after
the 8255A receives an ACK from the peripheral.
• ACK (Acknowledge) – This is an input signal issued by the
peripheral. A “low” signal on this pin indicates that the
peripheral receives the data from 8255A ports.
• INTR(Interrupt Request) – This is an output signal. It is
used to interrupt the CPU to request the next data byte for
output. The INTR will be in active state when OBF , ACK and
INTE are in logic 1 and it will be reset by the falling edge of
WR .
• INTE (Interrupt Enable) – This is an internal flip-flop used
to enable or disable the generation of INTR signal. There
are two flip-flops INTEA and INTEB are set/reset using the
BSR mode.
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Mode 2 – Bi-directional Data Transfer Mode
• This mode provides a means for communicating
with a peripheral device or structure on a single
8-bit bus for both transmitting and receiving data
(bidirectional bus I/O).
• The features of Mode 2 are :
• Used in Group A only.
• Port A only acts as bi-directional bus port
• Port C (PC3-PC7) is used for handshaking purpose.
• Both inputs and outputs are latched.
• Interrupt generation and enable/disable
functions are also available.
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• INTR (Interrupt Request):A high on this output can be used to
interrupt the CPU for input or output operations.
• OBF (Output Buffer Full):
• This signal will go LOW to indicate that the CPU has written data
out to Port A.
• ACK (Acknowledge):
• A LOW on this input enables the tri-state output buffer of Port A to
send out the data.
• Otherwise, the output buffer will be in the high impedance state.
• STB (Strobe Input):
• A LOW on this input loads data into the input latch.
• IBF (Input Buffer Full F/F):
• A HIGH on this output indicates that data has been loaded into the
input latch.
• Control word format for input and output configuration is given
below:
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Mode 2 Input/Output Configuration
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BSR (Bit Set/Reset) Mode
• This mode is applicable only for Port C. A control word with
bit D7 = 0 is recognized as BSR control word. This control
word can set or reset a single bit in the Port C. The control
word format is given below.
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SERIAL COMMUNICATION INTERFACE
• The primary difference between parallel I/O and
serial I/O is the number of lines used for data
transfer
• the parallel I/O uses the entire data bus and serial
I/O uses one data line.
• In serial I/O transmission the microprocessor
selects the peripheral through chip select ( CS ) and
uses the control signals read to receive data and
write to transmit data.
Serial data transmission is classified as
• Simplex
• Half duplex
• Full duplex
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Simplex
• The data are transmitted in only one direction. There
is no possibility of data transfer in the other
direction.
• Example : Transmission from a computer to the
printer.
Half duplex
• The data are transmitted in both directions, but not
simultaneously.
• Example : Walky – Talky
Full duplex
• The data are transmitted in both directions
simultaneously.
• Example : Telephone
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• The data in the serial communication may be sent in
two formats:
• Asynchronous
• Synchronous
Synchronous Transmission
• In synchronous transmission, a receiver and
transmitter work in same speed and could be
synchronized. Both will use a common clock and
start at the same time
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Asynchronous transmission
• The asynchronous transmission is character-
oriented. Each character carries the information
of the Start and Stop bits.
• When no data are being transmitted, a receiver
stays high at logic 1, called Mark and logic 0 is
called Space.
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Baud rate
• The rate at which bits are transmitted is called
baud rate.
• Baud rate = bits / second
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DIGITAL TO ANALOG (D/A) INTERFACE
• The digital to analog converters (DAC) convert
binary numbers into their analog equivalent
voltages or currents. Several techniques are
employed for digital to analog conversion.
i)Weighted resistor network
ii)R-2R ladder network
iii)Current output D/A converter
• The DAC find applications in areas like digitally
controlled gains, motor speed control,
programmable gain amplifiers, digital voltmeters,
panel meters, etc.
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• In a compact disk audio player for example a 14-
or16-bit DAC is used to convert the binary data
read off the disk by a laser to an analog audio
signal.
• Resolution: It is a change in analog output for
one LSB change in digital input.
• (1/2n )*Vref
• 1/256*5 V=39.06 mV (since n=8 for 8-bit DAC)
• Settling time: It is the time required for the DAC
to settle for a full scale code change.
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DAC 0800 8-bit Digital to Analog converter
• DAC 0800 is a monolithic 8-bit DAC
manufactured by National semiconductor.
• It has settling time around 100ms.
• It can operate on a range of power supply
voltage i.e. from 4.5V to +18V. Usually the supply
V+ is 5V or +12V. The V- pin can be kept at a
minimum of –12V.
• Resolution of the DAC is 39.06mV
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Interfacing of DAC0800 with 8086
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ANALOG TODIGITAL INTERFACE
• The digital equipment cannot directly accept the
analog signals such as voltage or current. These
signals are need to be converted into digital form by
using suitable device called Analog to Digital
converter (ADC).
• An ADC is essential in a microprocessor based
system as the microprocessor can only handle digital
data, though the real-world signals are in analog
form.
• An important specification for an ADC is its
conversion time. This is simply the time it takes the
converter to produce a valid output binary code for
an applied input voltage. The high speed converter
has a short conversion time.
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• The start of conversion signal is a pulse of a specific
duration. The process of analog to digital conversion
is a slow process, and the microprocessor has to
wait for the digital data till the conversion is over.
• After the conversion is over, the ADC sends end of
conversion (EOC) signal to inform the
microprocessor that the conversion is over and the
result is ready at the output buffer of the ADC.
• the digital output of the ADC are carried out by the
CPU using 8255 I/O ports.
• Mostly, 8255 is used for interfacing the ADC with a
microprocessor.
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• The time taken by the ADC from SOC to the EOC
signal is called as the conversion delay of the ADC.
• Parallel converter or flash converter, successive
approximation and dual slope integration techniques
are the most popular techniques used in the
integrated ADC chips.
The ADC interfacing consists of the following steps.
• Ensure the stability of analog input, applied to the
ADC.
• Issue start of conversion (SOC) pulse to ADC.
• Read end of conversion (EOC) signal to mark the
end of conversion process.
• Read digital data output of the ADC as equivalent
digital output.
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ADC 0808/0809
• The analog to digital converter chips 0808 and
0809 are 8-bit CMOS, successive approximation
converters. Successive approximation technique
is one of the fast techniques.
• The conversion delay is 100 ms at a clock
frequency of 640 kHz, which is quite low as
compared to other converters.
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Pin diagram of ADC 0808/0809
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Timing diagram of ADC 0808/0809
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TIMER
Features of 8254
• 8254 is a Timer/Counter
• It is designed to solve the common timing control problems in
microcomputer system design.
• Compatible with all Intel and most other microprocessors It can be
operated at count rates upto 10 MHz
• Six programmable counter modes and all modes are software
programmable. Three independent 16-bit counters
• Each counter has a separate clock input, count enable (gate) input
lines and output line.
• Binary or BCD counting
• The 8254 uses HMOS technology and comes in a 24-pin plastic
package.
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Applications of 8254
• It is used to generate accurate time delays, It
can be used for
• Real time clock
• Event-counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller
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Pin Diagram of 8254
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Block Diagram of 8254
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Data Bus Buffer
• This 3-state, bi-directional, 8-bit buffer is used to interface
the 8254 to the system bus.
Read/Write Logic
• The Read/Write logic accepts inputs from the system bus
and generates control signals for the other functional
blocks of the 8254.
• A1 and A0 select one of the three counters or the control
word register to be read from/written into.
• A “low” on the RD input tells the 8254 that the CPU is
reading one of the counters.
• A “low” on the WR input tells the 8254 that the CPU is
writing either a Control Word or an initial count.
• Both RD and WR are qualified by CS ; RD and WR are
ignored unless the 8254 has been selected by holding CS
low.
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Control Word Register
• The control word register is selected by the Read/Write logic
when A1, A0=11.
• If the CPU then does a write operation to the 8254, the data is
stored in the control word register and is interpreted as a
control word used to define the operation of the counters.
• The control word register can only be written to; status
information is available with the Read-Back command.
Counter 0, Counter 1, Counter 2
• Each is a 16 bit down counter.
• The counters are fully independent. Each counter may operate
in a different mode.
• Each counter has a separate clock input, count enable (gate)
input lines and output line.
• The control word register is not a part of the counter itself, but
its contents determine how the counter operates.
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Operational Modes of 8254
• The 8254 can operate in six operating modes.
They are
• Mode 0: Interrupt On Terminal Count
• Mode 1: Hardware Retrigger able One-Shot
• Mode 2: Rate Generator
• Mode 3: Square Wave Mode
• Mode 4: Software Triggered Strobe
• Mode 5: Hardware Triggered Strobe
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Gate settings of a counter
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Programming the 8254
Write Operations
• For each counter, the control word must be written before the initial
count is written.
• The initial count must follow the count format specified in the control
word (least significant byte only, most significant byte only, or least
significant byte and then most significant byte).
• Since the control word register and the three counters have separate
addresses (selected by the A1,A0 inputs), and each control word
specifies the counter it applies to (SC0,SC1 bits), no special instruction
sequence is required.
Read Operations
• It is often desirable to read the value of a counter without disturbing
the count in progress. This is easily done in the 8254.
• There are three possible methods for reading the counters:
Simple read operation,
Counter latch command, and
Read-Back command.
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Control Word Format of 8254
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KEYBOARD/DISPLAY CONTROLLER
• Intel 8279 is an LSI device.
• It simultaneously drives the display of a system
and interfaces a keyboard with the
microprocessor.
• The keyboard display interface scans the
keyboard to identify if any key has been pressed
and sends the code of the pressed key to the
microprocessor.
• It also transmits the data received from
microprocessor to the display device.
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Features of 8279
• 8279 has 3 input modes for keyboard interface
Scanned keyboard mode
Scanned sensor matrix mode
Strobed input mode
• 8279 has 2 output modes for display interface
Left entry
Right entry
• It has two key depression modes
2 key lockout mode
N key rollover mode
• It has built-in hardware to provide key bounce. It provides 8 byte FIFO
RAM to store key codes.
• It provides multiplexed display interface with blanking and inhibit
options.
• It provides 16 byte display RAM to store display codes for 16 digits,
allowing to interface 16 digits.
• Simultaneous keyboard and display operation facility allows to
interleave keyboard and display software.
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Pin Diagram of 8279
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• Data Bus (D7 – D0) :
• All data and commands between the microprocessor and 8279 are transmitted on
these lines.
• RD (Read) :
• Microprocessor reads the data/status from 8279.
• WR (Write) :
• Microprocessor writes the data to 8279.
• A0 :
• A HIGH signal on this line indicates that the word is a command or status. A LOW
signal indicates the data.
• RESET :
• High signal in this pin resets the 8279. After being reset, the 8279 is placed in the
following modes
• 16 x 8-bit character display –left entry
• Two key lock out
• CS (Chip Select) :
• A LOW signal on this input pin enables the communication between 8279 and the
microprocessor.
• IRQ (Interrupt Request) :
• The interrupt line goes low with each FIFO/sensor RAM reads and returns high if
there is still information in the RAM.
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• SL0 – SL3 :
• Scan lines which are used to scan the key switch or sensor matrix and the
display digits.
• These lines can be either encoded (1 of 16) or decoded (1 of 4).
• RL0 – RL7 :
• Input return lines which are connected to the scan lines through the keys or
sensor switches. They have active internal pull-ups to keep them high until a
switch closure pull one low. These also serve as an 8-bit input in the strobed
input mode.
• SHIFT :
• It has an active internal pul lup to keep it high until a switch closure pulls it low.
• CNTL/STB :
• For keyboard mode, this line is used as a control input and stored like status on
a key closure. The line is also the strobed line to enter the data in to the FIFO in
the strobed input mode.
• OUT A0 – OUT A3, OUT B0 – OUT B3 :
• These two ports are the outputs for the 16´4 display refresh registers. These
two ports may also be considered as one 8-bit port. The two 4-bit ports may be
blanked independently.
• BD :
• This output is used to blank the display during digit switching or by a display
blanking command.
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Block Diagram of 8279
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The 8279 has the following four sections.
• CPU Interface Section
• Keyboard Section
• Scan Section
• Display Section
CPU Interface Section
• This section has bi-directional data buffer (DB0 – DB7), I/O
control lines ( RD , WR , CS , A0) and Interrupt Request line (IRQ).
• The A0 signal determines whether transmit/receive control word
or data is used.
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Keyboard Section
• This section has keyboard debounce and control,
8x8 FIFO/Sensor RAM, 8 Return lines (RL0 – RL7)
and CNTL/STB and shift lines.
• In the keyboard debounce and control unit, keys
are automatically debounced and the keyboard
can be operated in two modes.
Two key lock out
N – key roll over
• In the two key lock out mode, if two keys are
pressed simultaneously, the first key only
recognized. In the N-key roll over mode, it stores
the codes of simultaneous keys pressed in the
internal buffer, it can also be setup so that no key
is recognized until only one key remains pressed.
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Scan Section
• This section has scan counter and four scan lines
(SL0–SL3). These lines are decoded by 4 to16
decoder to generate 16 scan lines. Generally SL0 –
SL3 are connected with the rows of a matrix
keyboard.
Display Section
• This section has two groups of output lines A0 – A3
and B0–B3. These lines are used to send data to
display drivers. BD line is used blank the display. It
also has 16 x 8 display RAM.
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INTERFACING OF KEYBOARD AND
DISPLAY USING 8086 MICROPROCESSOR
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Interrupt Controller
• The 8259A programmable interrupt controller
extends the hardware interrupt facility
provided in a microprocessor.
• It manages up to 8 vectored priority
interrupts for a processor.
• It has built-in features for expandability to
other 8259A’s (up to 64 vectored priority
interrupts).
• It is programmed by the system’s software as
an I/O peripheral.
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Features of 8259 A
• It can manage 8 priority interrupts.
• By cascading 8259s it is possible to get 64 priority interrupts.
• It can be programmed to accept either the level triggered or the
edge triggered interrupt request.
• Reading of interrupt request register (IRR) and in-service register
(ISR) through data bus.
• Writing and reading of interrupt mask register (IMR) through data
bus.
• The various modes of operation of the 8259 are:
Fully nested mode
Special fully nested mode.
Special mask mode
Buffered mode
Poll command mode
Cascade mode with master or slave selection
Automatic end-of-interrupt mode
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Interrupt controller pin diagram
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8259 Consists of the following blocks :
• Control logic unit
• In-Service Register (ISR)
• Priority Resolver
• Read/Write logic
• Data Bus buffer
• Cascade buffer
• Interrupt Request Register (IRR)
• Interrupt Mask Register (IMR).
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Interrupt Request Register (IRR)
• The interrupts at the IR input lines are
handled by two registers in cascade, the
Interrupt Request Register (IRR) and the In-
Service Register (ISR). The IRR is used to store
all the interrupt levels which are requesting
service.
In-Service Register (ISR)
• The ISR is used to store all the interrupt levels
which are being serviced.
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Priority Resolver
• This logic block determines the priorities of the
bits set in the IRR. The highest priority is selected
and strobed into the corresponding bit of the ISR
during INTA pulse.
Interrupt Mask Register (IMR)
• The IMR stores the bits which mask the interrupt
lines to be masked. The IMR operates on the IRR.
Masking of a higher priority input will not affect
the interrupt request lines of lower quality.
Data Bus Buffer
• This 3-state, bidirectional 8-bit buffer is used to
interface the 8259A to the system data bus.
Control words and status information are
transferred through the Data Bus Buffer.
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Read/Write Control Logic
• The function of this block is to accept output commands from the
Microprocessor. It contains the Initialization Command Word (ICW)
registers and Operation Command Word (OCW) registers which store the
various control formats for device operation. This function block also
allows the status of the 8259A to be transferred onto the data bus.
• CS
• WR
• (Chip Select)
• A LOW on this input enables the 8259A. No reading or writing of the chip
will occur unless the device is selected.
• (Write)
• A LOW on this input enables the CPU to write control words (ICWs and
OCWs) to the 8259A.
• RD (Read)
• A LOW on this input enables the 8259A to send the status of the Interrupt
Request Register (IRR), In Service Register (ISR), the Interrupt Mask
Register (IMR), or the Interrupt level onto the Data Bus.
• A0
• This input signal is used in conjunction with WR and RD signals to write
commands into the various command registers, as well as reading the
various status registers of the chip. This line can be tied directly to one of
the address lines.
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Cascade Buffer/Comparator
• This block is used to expand the number of interrupt levels by
cascading two or more 8259s.
• This function block stores and compares the IDs of all 8259A’s used
in the system. The associated three I/O pins (CAS0-2) are outputs
when the 8259A is used as a master and are inputs when the 8259A
is used as a slave. As a master, the 8259A sends the ID of the
interrupting slave device onto the CAS0±2 lines. The slave thus
selected will send its preprogrammed subroutine address onto the
Data Bus during the next one or two consecutive INTA pulses.
Control Logic
• This block has two pins INT and INTA.
INT (Interrupt)
• This output goes directly to the CPU interrupt input. The voltage
level on this line is designed to be fully compatible with the 8080A,
8085A and 8086 input levels.
INTA (Interrupt Acknowledge)
• INTA pulses will cause the 8259A to release vectoring information
onto the data bus.
• The format of this data depends on the system mode of the 8259A.
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8257-PROGRAMMABLE DMA
CONTROLLER
Direct Memory Access :
• The ability of an I/O sub system is to transfer data
to and from a memory subsystem, which is used
for high speed data transfer.
• Ex : Data transfer between a floppy disk and
memory.
DMA Controller :
• It is a device that can control data transfer
between an I/O subsystem and a memory
subsystem without the help of CPU.
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DMA Operation sequence :
• Once interface is ready to receive data, DMA
request is made.
• Bus request is made by the DMA.
• Bus grant is returned by the processor.
• DMA places address on the address bus.
• DMA request is acknowledged.
• Memory places data on the data bus.
• Interface latches data.
• Bus request is dropped and control is returned to
the processor.
• Bus grant is dropped by the processor.
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Features of 8257
• Enable / Disable control of individual DMA Requests.
• Four Independent DMA channels - CH0, CH1, CH2 and
CH3.
• Independent auto-initialization of all channels.
• Memory to memory transfer.
• Memory block initialization.
• Address increment or decrement.
• High speed performance - transfers upto 1.6 M
bytes/second.
• Directly expandable to any number of channels.
• Software DMA requests.
• Independent polarity control for DRQ and DACK
signals.
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DMA controller
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• Data Bus Buffer :
• It is a tri-state, bidirectional, 8 bit buffer which interfaces
the 8257 to the system data bus. In the slave mode, it is
used to transfer data between microprocessor and internal
registers of 8257. In master mode, it is used to send higher
byte address (A8–A15) on the data bus.
• Read/Write Logic :
• When the microprocessor is programming or reading one
of the internal registers of 8257 (ie, slave mode), the
Read/Write logic accepts the I/O Read (IOR) or IOW signal,
decodes the least significant four address bits (A0–A3) and
either writes the contents of the data bus into the
addressed register (if IOW=0) or places the contents of the
addressed register onto the data bus (if IOR=0)
• During DMA cycles (ie, Master mode) the Read/Write logic
generates the I/O read and memory write (DMA write
cycle) or I/O Write and Memory read (DMA read cycle)
signals which control the data transfer between peripheral
and memory device.
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DMA Channels
• The 8257 provides four identical channels labelled CH0,
CH1, CH2 and CH3. Each channel has two-16 bit
registers
DMA address register
Terminal Count register
Control Logic :
• It controls the sequence of operations during all DMA
cycles (DMA read, DMA write, DMA verify) by
generating the appropriate control signals and the 16-
bit address that specifies the memory location to be
accessed. It consists of mode set register and status
register. Mode set register is programmed by the CPU
to configure 8257 whereas the status register is read by
CPU to check which channels have reached a terminal
count condition and status of update flag.
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Priority Resolver :
It resolves the peripherals request. It can be programmed to work in two modes,
either in fixed mode or rotating priority mode.
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INTERFACING LED DISPLAYS TO 8086
• LED’s are most important display device. Fig shows a
single LED. The I/O device cannot be connected directly
to the microprocessor, it can be connected through a
latch IC.
The most important application of LED is to display alphanumeric
characters. The seven LED‘s are arranged as a segment and
selectively lighted up to display the alphanumeric characters.
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• The LED modules can be used in the common
anode or common cathode configuration.
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INTERFACING LIQUID CRYSTAL
DISPLAYS (LCD) TO8086
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TRAFFIC LIGHT CONTROLLER USING 8086
• The traffic light control is implemented in road
crossings using a microprocessor system by
automatically switching ON/OFF of traffic lights in the
desired sequence.
• A traffic light control is implemented by interfacing
8255 with 8086. A block diagram of traffic light
controller using 8086 is shown in Fig.
• The traffic light system consists of EPROM for program
storage, RAM. The keyboard is provided for manual
control. Seven segment LED display is provided to
display the direction of traffic.
• The Red (stop), Yellow (wait) and Green (go) LED’s are
switched ON or OFF in a desired sequence using
microprocessor system. The LED are interfaced to the
bus through buffer and ports of 8255.
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ALARM CONTROLLER
• The alarm controller using 8086 microprocessor
is explained by the following example.
Design a pre-settable alarm system using 8254 timer. Use thumbwheel
switches to accept 4 digit value in seconds. Alarm should last for 5
seconds.
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Interfacing of 4*4 Keyboard with 8086
Microprocessor
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Interfacing of 8 keys and 8 LED display
with 8086 through 8255
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Unit 3 mpmc

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Unit 3 mpmc