![03-10-2024
Types of Schemes
• Pulse sequence is decided by the required motion of the shaft.
• Types of schemes
o Wave Scheme
o Full Step Scheme
o Half Step Scheme
• Wave Scheme
o A simple scheme to rotate the shaft of stepper motor.
o Here Wa, Wb, Wc, and Wd are applied with the required voltage pulses, in
cyclic fashion. To change the rotation in opposite direction give pulse
sequence in reverse direction.
• Full Step Scheme
o Here consecutive two windings are excited at a time. These are shifted only
one position at a time.
Half Step Scheme
o Combination of Wave and Full Step scheme. Used for step angle reduction.
97
Table 1: Wave Winding
D
C
B
A
Step
Motion
0
0
0
1
1
Clockwise
0
0
1
0
2
0
1
0
0
3
1
0
0
0
4
0
0
0
1
5
0
0
0
1
1
Anticlockwise
1
0
0
0
2
0
1
0
0
3
0
0
1
0
4
0
0
0
1
5
98
Table 2: Full Step Winding
D
C
B
A
Step
Motion
1
1
0
0
1
Clockwise
0
1
1
0
2
0
0
1
1
3
1
0
0
1
4
1
1
0
0
5
1
1
0
0
1
Anticlockwise
1
0
0
1
2
0
0
1
1
3
0
1
1
0
4
1
1
0
0
5
99
Operation of
Stepper Motor
Stepper motor contains Permanent
Magnet (rotor) and electromagnet
Stator, with one-phase-on configuration.
In the top left figure, North pole of rotor
is attracted by South pole of A+
electromagnet. South pole of rotor is
attracted by North pole of A+
electromagnet.
A and B are stator poles.
Image Courtesy: Faulhaber Brochure [1]
100
97 98
99 100](https://image.slidesharecdn.com/unit3all-241026055546-51d0bca2/85/Unit3_all-timer-interfacing-in-microcontroller-25-320.jpg)
![03-10-2024
Typical Stepper Motor
A typical stepper motor may have parameters like torque 3
kg-cm, operating voltage 12 V, current rating 0.2 V and a step
angle 1.8°.
The number of rotor teeth is equal to the count for one
rotation, i.e. 360°. For any specified angle 𝜃°
the count (𝐶) is
calculated as:
𝑪 =
𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝒓𝒐𝒕𝒐𝒓 𝒕𝒆𝒆𝒕𝒉
𝟑𝟔𝟎°
× 𝜽°
Image Courtesy: Faulhaber
Reference
[1]_https://www.faulhaber.com/fileadmin/user_upload_global/support/MC_Support/Motors/A
ppNotes/Faulhaber_AN001_EN.pdf ~ Interesting and well written article
101
Dr. A Bhargavi Haripriya, Asst.Prof., BME, SRMIST
From Other Source (1/5)
102
Image Courtesy: Mrs. Suganthi Brindha G., In turn Google
Rotors
invariably
made up of
permanent
magnet
From Other Source (2/5)
103
Single Coil
Excitation.
Excited coil
is shown in
red colour
Image Courtesy: Mrs. Suganthi Brindha G., In turn Google
104
From Other Source (3/5)
TWO Coil
Excitation.
Each
successive
pair of
adjacent
coils is
energized in
turn.
Image Courtesy: Mrs. Suganthi Brindha G., In turn Google
101 102
103 104](https://image.slidesharecdn.com/unit3all-241026055546-51d0bca2/85/Unit3_all-timer-interfacing-in-microcontroller-26-320.jpg)
Unit3_all timer interfacing in microcontroller
- 1. 03-10-2024 Unit 3: Interfacing Devices By Dr. Rohit Gupta Assistant Professor Department of Biomedical Engineering SRMIST, Kattankulathur Microcontroller and its Application in Medicine (21BMC302J) Contents • Timer Interfacing • Programmable Communication Interface 8251:USART • External Memory Interfacing • Basic techniques for reading & writing from I/O port pins • Keyboard interfacing • Stepper Motor interfacing • LCD interfacing TIMER PROGRAMMING Unit 3: Interfacing Devices 8051: Pin Diagram 12MHz PORT 3 1 2 3 4
- 2. 03-10-2024 Concepts of 8051 Timer Programming Two 16-bit timers (T0, T1) Can be used as a timer as well as a counter If it counts the internal clock pulse, it works as a timer If it counts the external clock pulse, it works as a counter Works only as UP counter • Accessed as low byte and high byte • The low byte register is called TL0/TL1 and • The high byte register is called TH0/TH1 • Accessed like any other register • MOV TL0,#4FH • MOV R5,TH0 6 Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming 5 6 7 8
- 3. 03-10-2024 Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming 9 10 11 12
- 4. 03-10-2024 Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming 13 14 15 16
- 5. 03-10-2024 Concepts of 8051 Timer Programming Concepts of 8051 Timer Programming • Timers of 8051 do starting and stopping by either software or hardware control • In using software to start and stop the timer where GATE=0 • The start and stop of the timer are controlled by way of software by the TR (timer start) bits TR0 and TR1 • – The SETB instruction starts it, and it is stopped by the CLR instruction • – These instructions start and stop the timers as long as GATE=0 in the TMOD register • The hardware way of starting and stopping the timer by an external source is achieved by making GATE=1 in the TMOD register Concepts of 8051 Timer Programming 19 Concepts of 8051 Timer Programming 17 18 19 20
- 6. 03-10-2024 Concepts of 8051 :Generating delay without timer 1 MOV R2, #10H Delay: 2 DJNZ R2, LOOP LOOP: 1 NOP 1 NOP 1 NOP 2 RET Time delay: (1+(2x10)+1+1+1+2)x1.085uSec Time delay: 28.21uSec Time delay: 26x1.085uSec Concepts of 8051 Timer Programming: Delay Calculation E.g. Calculate the amount of time delay in the DELAY subroutine generated by the timer. Assume XTAL = 11.0592 MHz. Solution: • The timer works with a clock frequency of 1/12 of the XTAL frequency; therefore, we have 11.0592 MHz / 12 = 921.6 kHz as the timer frequency. • The number of counts for the roll over is FFFFH – FFF2H = 0DH (13decimal). • As a result, each clock has a period of T = 1/921.6kHz = 1.085us. • In other words, Timer counts up each 1.085 us resulting in delay = number of counts × 1.085us. • However, we add one to 13 because of the extra clock needed when it rolls over from FFFF to 0 and raise the TF flag. • This gives 14 × 1.085us = 15.19us Delay calculation with Load Count Concepts of 8051 Timer Programming: Delay Calculation E.g.: The following program generates a square wave on pin P1.5 Using timer1, Find the frequency of the generated waveform. Consider XTAL = 11.0592 MHz. MOV TMOD, #10H AGAIN: MOV TL1, #34H MOV TH1, #12H SETB TR1 BACK: JNB TF1, BACK CLR TR1 CPL P1.5 CLR TF1 SJMPAGAIN • FFFFH – 1234H + 1 = EDCCH = 60876 clock count Maximum count – count uploaded + 1 = actual needed count • Half period = 60876 x 1.085us = 66.050 ms • Total period = 2 x 66.050 ms = 132.100ms • Frequency = 1/132.100ms = 7.57 Hz Concepts of 8051 Timer Programming: Delay Calculation E.g. Program to generate a square wave of frequency 9Hz on pin P1.5 Using timer1, Consider XTAL = 11.0592 MHz. MOV TMOD, #10H AGAIN: MOV TL1, ?# MOV TH1, ?# SETB TR1 BACK: JNB TF1, BACK CLR TR1 CPL P1.5 CLR TF1 SJMPAGAIN • Frequency = 9Hz • Total Period= 1/9=0.1111sec • Half Period= 0.1111/2=0.0555sec • Clock count = 0.0555/ 1.085us=50691 Maximum count – count uploaded + 1 = actual needed count Maximum count – count uploaded + 1 = 50691 count uploaded = 65536–50691+ 1 count uploaded = 14576= 38F0H 21 22 23 24
- 7. 03-10-2024 Concepts of 8051 Timer Programming: Delay Calculation Eg.: Program to generate a square wave of frequency 9Hz on pin P1.5 Using timer1, Consider XTAL = 11.0592 MHz. MOV TMOD, #10H AGAIN: MOV TL1, # F0H MOV TH1, # 38H SETB TR1 BACK: JNB TF1, BACK CLR TR1 CPL P1.5 CLR TF1 SJMPAGAIN • Frequency = 9Hz • Total Period= 1/9=0.1111sec • Half Period= 0.1111/2=0.0555sec • Clock count = 0.0555/ 1.085us=50691 Maximum count – count uploaded + 1 = actual needed count Maximum count – count uploaded + 1 = 50691 count uploaded = 65536–50691+ 1 count uploaded = 14576= 38F0H Concepts of 8051 Timer Programming: Delay Calculation E.g.: What will be the load count to generate a delay of 1ms for the 8051 microcontroller if the timer 1 is used in mode 1? • Clock count = 1000/ 1.085us=921 Maximum count – count uploaded + 1 = actual needed count Maximum count – count uploaded + 1 = 921 count uploaded = 65536–921+ 1 count uploaded = 64616= FC68H • 1ms=0.001sec=1000usec MOV TL1, # 68H MOV TH1, # FCH PROGRAMMABLE COMMUNICATION INTERFACE 8251:USART Unit 3: Interfacing Devices Terminologies Serial data transmission Parallel data transmission 25 26 27 28
- 8. 03-10-2024 Terminologies Simplex data transmission Half-duplex data transmission Full-duplex data transmission Tx Rx Rx Rx Tx Tx Rx Tx Terminologies Bit rate Baud rate Baud rate is 1Bd Baud rate is 3Bd Bit rate is 1bits/Sec Bit rate is 2bits/Sec Baud rate is 1Bd Baud rate is 1Bd Terminologies Synchronous data transmission Asynchronously data transmission 8251 USART 8251 Universal synchronous asynchronous receiver transmitter (USART) acts as a mediator between microprocessor and peripheral to transmit serial data into parallel form and vice versa. It takes data serially from peripheral (outside devices) and converts it into parallel data. After converting the data into parallel form, it transmits it to the CPU. It receives parallel data from the microprocessor and converts it into serial form. After converting data into a serial form, it transmits it to the outside device (peripheral). MCU 8251 P-S Peripheral MCU 8251 S-P Peripheral 29 30 31 32
- 9. 03-10-2024 8251 USART: Architecture 8251 USART: Architecture Data Bus Buffer: It basically interfaces the 8251 with the internal system buses of the processor. The data bus buffer has 8-bit bidirectional data bus that allows the transfer of data bytes, status or command word between the processor and external devices. 8251 USART: Architecture Read/Write Control Logic: It generates a control signal for the operation of 8251 according to the signal present in the control bus of the processor. It performs decoding operation of the control signal produced by the processor, so that respective operation can be performed by the USART. CS: (chip select): A low signal at this pin shows that processor has selected 8251 in order to communicate with the peripheral devices. C/D: When a high signal is present at this pin then control or status register is addressed. While in case of low signal data register is addressed. RD and WR: Both read and write are active low signal pins. A low signal at RD shows that the processor is reading the control, status or data bytes from the 8251. While low signal at WR indicates the write operation over the data bus of 8251. CLK and RESET: CLK stands for clock and it produces the internal timing for the device. While an active high signal at the RESET pin puts the 8251 in the idle mode 8251 USART: Architecture 33 34 35 36
- 10. 03-10-2024 8251 USART: Architecture Modem Control: It holds input and output control signals that simplify the operation of the whole system. The control circuitry for handing various signals is provided by the modem control unit. It includes DTS, RTS, DTR and CTS. These are all active low signals. DSR (data set ready): It is used to check whether the data set is ready or not when the processor is in the urge of communication. DTR (data terminal ready): An active-low signal at this pin shows that the 8251 is now ready to accept the data from the processor. RTS (request to send): A low signal shows an assertion for data transmission as requested by 8251 CTS (Clear to send): Low signal at this pin then it clears all the data present in the modem in order to allow further communication. 8251 USART: Architecture Transmit Buffer: This unit is used to change the parallel data received from the CPU into serial data by inserting the necessary framing information. 8251 USART: Architecture Transmit Control: It controls the transmission action by accepting and sending signals both externally and internally. TxRDY (transmit ready): This signal is used to notify the processor that the buffer register of the 8251 is empty and ready to accept the data. TxE (transmitter empty): It is an active high signal that indicates that the output buffer is empty and thus data received from the processor can be loaded to it for conversion. TxC (transmitter clock): It is an active low pin. It controls the rate of character transmission by the USART. 8251 USART: Architecture Transmit Control: It controls the transmission action by accepting and sending signals both externally and internally. 37 38 39 40
- 11. 03-10-2024 8251 USART: Architecture Receive Buffer: It takes the serial data from the external devices, changes it to the parallel form so that it can be accepted by the processor. 8251 USART: Architecture Receive Control: This unit controls the operation of the receiver buffer. It manages the data reception, detects the presence of false start bit, error in parity bit, framing errors etc RxRDY (receiver ready): When this signal goes high then it indicates that the receiver buffer register is holding the data and is ready to transfer it to the processor. Once the CPU reads the data sent by the 8251 then this pin is reset. RxC (receiver clock): This clock signalling controls the rate at which the 8251 receives the data in the synchronous mode of operation. It is provided by the modem and is equal to the baud rate. SYNDET/BRKDET (synchronous Detection/Break Detection): It is a bidirectional pin. It can be used as an input as well as output 8251 USART: Architecture SYNDET/BRKDET (synchronous Detection/Break Detection): It is a bidirectional pin. It can be used as an input as well as output When used as an output, the SYNDET pin will go high which indicates that a SYNC character is located in the receive mode. When this is used as an input, positive going signal will cause 8251A to start assembling a data character on the rising edge of the next RXC. In asynchronous mode this pin acts as a BRKDET, a high on this pin goes low for RXD through two consecutive stop bit sequences. If RXD is high, it provides break during last bit of next character 8251 USART: Architecture Receive Control: This unit controls the operation of the receiver buffer. It manages the data reception, detects the presence of false start bit, error in parity bit, framing errors etc 41 42 43 44
- 12. 03-10-2024 8251 USART: Architecture 8251 USART: Pin Diagram It is packed in a 28 pin DIP 8251 USART: Mode of Operation • 8251 USART can take place with four different ways. – Asynchronous transmission – Asynchronous reception – Synchronous transmission – Synchronous reception • These communication modes can be enabled by writing proper mode and command instructions. The mode instruction defines the baud rate (in case of asynchronous mode), character length, number of stop bit(s) and parity type. After writing proper mode instruction it is necessary to write appropriate command instruction depending on the communication type. 47 Asynchronous transmission 1. Asynchronous transmission • Transmission can be enabled by setting transmission enable bit (bit 0) in the command instruction. When transmitter is enabled and CTS = 0 the transmitter is ready to transfer data on TxD line. Operation : • When transmitter is ready to transfer data on TxD line, CPU sends data character and it is loaded in the transmit buffer register. The 8251 USART then automatically adds a start bit (low level) followed by the data bits (least significant bit first), and the programmed number of STOP bit(s) to each character. 48 45 46 47 48
- 13. 03-10-2024 Asynchronous transmission (Cont’d…) • It also adds parity information prior to STOP bit(s), as defined by the mode instruction. The character is then transmitted as a serial data stream on the TxD output at the falling edge of TxC. The rate of transmission is equal to 1, 1/16 or 1/64 that of the TxC, as defined by the mode instruction. Fig. 14.41 shows the transmitter output in the asynchronous mode. 49 Asynchronous Reception 2. Asynchronous Reception: • Reception can be enabled by setting receive enable bit (bit 2) in the command instruction. Operation : • The RxD line is normally high. 8251A looks for a low level on the RxD line. When it receives the low level, it assumes that it is a START bit and enables an internal counter. At a count equivalent to one-half of a bit time, the RxD line is sampled again. If the line is still low, a valid START bit is detected and the 8251A proceeds to assemble the character. 50 Asynchronous Reception (Cont’d…) • After successful reception of a START bit the 8251A receives data, parity, and STOP bits and then transfers the data on the receiver input register. • The data is then transferred into the receiver buffer register. Fig. 14.16 shows the receiver input in the asynchronous mode. 51 Synchronous Transmission 3. Synchronous Transmission: • Another 8251 Usart is Transmission can be enabled by setting transmission enable bit (bit 0) in the command instruction. When transmitter is enabled and CTS = 0, the transmitter is ready to transfer data on TxD line. Operation : • When transmitter is ready to transfer data on TxD line, 8251A transfers characters serially out on the TxD line at the falling edge of the. TxC. The first character usually is the SYNC character. Once transmission has started, the data stream at the TxD output must continue at the TxC rate. 52 49 50 51 52
- 14. 03-10-2024 Synchronous Transmission (Cont’d…) • If CPU does not provide 8251A with a data character before transmitter buffers become empty, the SYNC characters will be automatically inserted in the TxD data stream, as shown in the Fig. 14.43. In this case, the TxEMPTY pin is raised high to indicate CPU that transmitter buffers are empty. The TxEMPTY pin is internally reset when CPU writes data character in the transmitter buffer. 53 Synchronous Reception 4. Synchronous Reception : • Reception can be enabled by setting receive enable bit (bit 2) in the command instruction. Operation : • In this 8251 Usart, character synchronization can be achieved internally or externally. Internal SYNC To detect the SYNC character 8251A should be programmed in the ‘Enter HUNT’ mode by setting bit 7 in the command. insturction. Once 8251A enters in the ‘Enter HUNT’ mode it starts sampling data on the RxD pin on the rising edge of the RxC 54 Synchronous Reception (Cont’d…) • The content of the receiver buffer is compared at every bit boundary with the first SYNC character until a match, occurs. • If the 8251A has been programmed for two SYNC characters, the subsequent SYNC characters are compared until the match occurs. Once 8251A detects SYNC character(s) it enters from ‘HUNT’ mode to character synchronization mode, and starts receiving the data characters on the rising edge of the next RxC. • To indicate that the synchronization is achieved 8251A sets the SYNDET pin high. • It is reset automatically when CPU reads the status register. 55 EXTERNAL MEMORY INTERFACING WITH 8051 Unit 3: Interfacing Devices 53 54 55 56
- 15. 03-10-2024 8051: Memory Map Program Memory (ROM) Data Memory RAM Address line calculation Address Lines Memory 10 2 × 2 = 2 1KBytes 11 2 × 2 = 2 2KBytes 12 2 × 2 = 2 4KBytes 13 2 × 2 = 2 8KBytes 14 2 × 2 = 2 16KBytes 15 2 × 2 = 2 32KBytes 16 2 × 2 = 2 64KBytes 8051: Memory interfacing (Program memory, ROM) E.g.: Interface 8Kbytes of program memory with 8051 The address line required will be 13 8𝐾𝑏 = 2 × 2 = 2 8051: Memory interfacing (Program memory, ROM) E.g.: Interface 8Kbytes of program memory with 8051 The address line required will be 13 57 58 59 60
- 16. 03-10-2024 8051: Memory interfacing (Data memory, RAM) E.g.: Interface 4Kbytes of data memory with 8051 The address line required will be 12 4𝐾𝑏 = 2 × 2 = 2 8051: Memory interfacing (Data memory, RAM) E.g.: Interface 4Kbytes of data memory with 8051 The address line required will be 12 8051: Memory interfacing (RAM+ROM) E.g.: Interface 4Kbytes of data memory and 4Kbytes of program memory with 8051 The address line required will be 12 for both RAM and ROM 4𝐾𝑏 = 2 × 2 = 2 8051: Memory interfacing (RAM+ROM) E.g.: Interface 4Kbytes of data memory and 4Kbytes of program memory with 8051 The address line required will be 12 for both RAM and ROM ROM Addresses RAM Addresses 61 62 63 64
- 17. 03-10-2024 8051: Memory interfacing (RAM+ROM) E.g.: Interface 64Kbytes of data memory and 64Kbytes of program memory with 8051 The address line required will be 16 for both RAM and ROM 64𝐾𝑏 = 2 × 2 = 2 BASIC TECHNIQUES FOR READING & WRITING FROM I/O PORT PINS Unit 3: Interfacing Devices 8051: I/O port Input-output functionality is available with all 4 Ports Port 0: holds the lower 8 bits of address Additional Functions: Port 1: No additional functions Port 2: holds the higher 8-bits of address Port 3: There are multiple additional functions External RAM 8051: I/O port Input-output functionality is available with all 4 Ports Port 0: holds the lower 8 bits of address Additional Functions: Each pin must be connected externally to a 10K ohm pull-up resistor This is due to the fact that P0 is an open drain, unlike P1, P2, and P3 Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips 65 66 67 68
- 18. 03-10-2024 8051: I/O port(programming) • All the ports upon RESET are configured as input, ready to be used as input ports – When the first 0 is written to a port, it becomes an output – To reconfigure it as an input, a 1 must be sent to the port • 1>>>as input • 0>>>as output 8051: I/O port(programming) E.g.: Get the data from port 0 and send it to port 1 To configure it as an input, a 1 must be sent to the port Configure Port 0 as input port and port 1 as output port To configure it as an output, a 0 must be sent to the port MOV A, #FFH MOV P0, A MOV A, #00H MOV P1, A MOV A, P0 BACK: MOV P1, A SJMP BACK 8051: I/O port(programming) E.g.: Get the data from port 1 and save to registers • 1>>>as input • 0>>>as output 8051: I/O port(programming) Write a program to toggle all bits of port 2 in every ¼ sec. Assume the crystal frequency is 11.0592 MHZ MOV A, #00H MOV P2, A MOV A, #55H BACK: MOV P2, A ACALL DELAY4 MOV A, #AAH MOV P2, A ACALL DELAY4 SJMP BACK MOV R5, #?H DELAY4: MOV R4, #?H H3: MOV R3, #?H H2: DJNZ R3, H1 H1: DJNZ R4, H2 DJNZ R5, H3 RET 69 70 71 72
- 19. 03-10-2024 8051: I/O port(programming) Write a program to toggle all bits of port 2 in every ¼ sec. Assume the crystal frequency is 11.0592 MHZ MOV A, #00H MOV P2, A MOV A, #55H BACK: MOV P2, A ACALL DELAY4 MOV A, #AAH MOV P0, A ACALL DELAY4 SJMP BACK 1 MOV R5, #aH DELAY4: 1xa MOV R4, #bH H3: (1xb)xa MOV R3, #cH H2: ((2xc)xb)xa DJNZ R3, H1 H1: (2xb)xa DJNZ R4, H2 (2xa) DJNZ R5, H3 2 RET Delay Calculation: (1+a+ab+2abc+2ab+2a+2)x1.085x10 =0.25sec (3+a+ab+2abc+2ab+2a)=230414.74 Let c=255: (a+ab+510ab+2ab+2a)=230411.74 Let b=255: (130815a+2a)=230411.74 (130817a)=230156.74 a=1.75~2 • 1>>>as input • 0>>>as output (513ab+2a)=230411.74 8051: I/O port(programming) Write a program to toggle all bits of port 2 in every ¼ sec. Assume the crystal frequency is 11.0592 MHZ MOV A, #00H MOV P2, A MOV A, #55H BACK: MOV P2, A ACALL DELAY4 MOV A, #AAH MOV P2, A ACALL DELAY4 SJMP BACK MOV R5, #02H DELAY4: MOV R4, #FFH H3: MOV R3, #FFH H2: DJNZ R3, H1 H1: DJNZ R4, H2 DJNZ R5, H3 RET • 1>>>as input • 0>>>as output 8051: I/O port(programming) Different ways of Accessing Entire 8 Bits 8051: I/O port(programming): Bit addressability Sometimes we need to access only 1 or 2 bits of the port 73 74 75 76
- 20. 03-10-2024 8051: I/O port(programming): Bit addressability Instructions that are used for signal-bit operations are as following 8051: I/O port(programming) • 1>>>as input • 0>>>as output 8051: I/O port(programming) • 1>>>as input • 0>>>as output KEYBOARD INTERFACING Unit 3: Interfacing Devices 77 78 79 80
- 21. 03-10-2024 8051: Keyboard Interfacing • Keyboards are organized in a matrix of rows and columns. • The CPU processes both rows and columns through ports • So, with two 8-bit ports, an 8X8 matrix of keys can be connected to the controller. • When a key is pressed, a row and a column make a contact. Otherwise there is no connection • In microcontroller, programs stored in EPROM scan the keys continuously. • 4 X 4 matrix connected to two ports. rows are connected to output ports and columns are connected to an input port. 8051: Keyboard Interfacing 8051: Keyboard Interfacing 8051: Keyboard Interfacing (Scanning & IdentifyingKey) • It is a function of microcontroller to scan the keyboard continuously to detect and identify key pressed • To detect Pressed key microcontroller grounds all rows by providing 0 to output latch, then it reads the columns • If the data read from columns is D3-D0 = 1111 , no key is pressed and the process continues till key press is detected. • If one of the column bits has a zero, means key press has • occurred. • If D3-D0 = 1101 this means that key in the column D1 has been pressed. • After detecting a key press, microcontroller will go through the process • of identifying key. 81 82 83 84
- 22. 03-10-2024 8051: Keyboard Interfacing 8051: Keyboard Interfacing (Scanning & IdentifyingKey) • Starting with the top Row, the microcontroller grounds it by providing a low to Row D0 only If reads a column if data read is all 1s, no key in that row is activated and the process is moved to the next row. • It grounds the next row, reads the columns, and checks for any zero This process continues until row is identified • After identification of the Row in which Key has been pressed, find out column the key press belongs to 8051: Keyboard Interfacing (Scanning & IdentifyingKey) STEEPER MOTOR INTERFACING Unit 3: Interfacing Devices 85 86 87 88
- 23. 03-10-2024 Stepper Motor Basics • A stepper motor is an electric motor whose main feature is that its shaft rotates by performing steps, that is, by moving by a fixed amount of degrees. This feature is obtained thanks to the internal structure of the motor, and allows to know the exact angular position of the shaft by simply counting how may steps have been performed, with no need for a sensor. This feature also makes it fit for a wide range of applications. Stepper Motor Working Principles • The basic working principle of the stepper motor is the following: By energizing one or more of the stator phases, a magnetic field is generated by the current flowing in the coil and the rotor aligns with this field. By supplying different phases in sequence, the rotor can be rotated by a specific amount to reach the desired final position. • At the beginning, coil A is energized and the rotor is aligned with the magnetic field it produces. When coil B is energized, the rotor rotates clockwise by 60° to align with the new magnetic field. The same happens when coil C is energized. In the pictures, the colors of the stator teeth indicate the direction of the magnetic field generated by the stator winding. Stepper Motor Driving Techniques: wave mode • Only one phase at a time is energized. For simplicity, we will say that the current is flowing in a positive direction if it is going from the + lead to the - lead of a phase (e.g. from A+ to A-); otherwise, the direction is negative. Starting from the left, the current is flowing only in phase A in the positive direction and the rotor, represented by a magnet, is aligned with the magnetic field generated by it. • In the next step, it flows only in phase B in the positive direction, and the rotor spins 90° clockwise to align with the magnetic field generated by phase B. Later, phase A is energized again, but the current flows in the negative direction, and the rotor spins again by 90°. In the last step, the current flows negatively in phase B and the rotor spins again by 90°. Stepper Motor Driving Techniques: full-step mode • two phases are always energized at the same time. The steps are similar to the wave mode ones, the most significant difference being that with this mode, the motor is able to produce a higher torque since more current is flowing in the motor and a stronger magnetic field is generated. 89 90 91 92
- 24. 03-10-2024 Stepper Motor Driving Techniques: Half-step mode • It is a combination of wave and full-step modes. Using this combination allows for the step size to be reduced by half (in this case, 45° instead of 90°). The only drawback is that the torque produced by the motor is not constant, since it is higher when both phases are energized, and weaker when only one phase is energized. Stepper Motor Interfacing • A stepper motor is a device to obtain an accurate position control of rotating shaft. Rotation of shaft takes place in terms of steps unlike AC or DC motors. • To rotate the shaft, sequences of pulses are applied to the windings of the stepper motor, in a sequence. • No of pulses required for one complete rotation of the shaft of the stepper motor is equivalent to number of teeth on its rotor. • When the rotor teeth and stator teeth lock with each other to fix a shaft in a position • When a pulse applied to the winding, the rotor rotates by one tooth or an angle 𝑥. …. (1) 𝒙 = 𝟑𝟔𝟎° 𝒏𝒐. 𝒐𝒇 𝒓𝒐𝒕𝒐𝒓 𝒕𝒆𝒆𝒕𝒉 94 Stepper Motor Interfacing (2) • After rotation of the shaft through angle 𝑥, the rotor locks itself with the next tooth in the sequence on the internal surface of stator. Internal Schematic of a four winding Stepper motor Schematic of a stepper motor rotor with six teeth on its surface 95 Winding Information Winding arrangement of stepper motor Image Courtesy: Adv. µP by A.K. Ray Interfacing Stepper Motor Winding Wa Image Courtesy: Adv. µP by A.K. Ray Stepper motors are designed to work with digital circuits. Binary level pulses (0-5 V) are applied to energize the windings. 96 93 94 95 96
- 25. 03-10-2024 Types of Schemes • Pulse sequence is decided by the required motion of the shaft. • Types of schemes o Wave Scheme o Full Step Scheme o Half Step Scheme • Wave Scheme o A simple scheme to rotate the shaft of stepper motor. o Here Wa, Wb, Wc, and Wd are applied with the required voltage pulses, in cyclic fashion. To change the rotation in opposite direction give pulse sequence in reverse direction. • Full Step Scheme o Here consecutive two windings are excited at a time. These are shifted only one position at a time. Half Step Scheme o Combination of Wave and Full Step scheme. Used for step angle reduction. 97 Table 1: Wave Winding D C B A Step Motion 0 0 0 1 1 Clockwise 0 0 1 0 2 0 1 0 0 3 1 0 0 0 4 0 0 0 1 5 0 0 0 1 1 Anticlockwise 1 0 0 0 2 0 1 0 0 3 0 0 1 0 4 0 0 0 1 5 98 Table 2: Full Step Winding D C B A Step Motion 1 1 0 0 1 Clockwise 0 1 1 0 2 0 0 1 1 3 1 0 0 1 4 1 1 0 0 5 1 1 0 0 1 Anticlockwise 1 0 0 1 2 0 0 1 1 3 0 1 1 0 4 1 1 0 0 5 99 Operation of Stepper Motor Stepper motor contains Permanent Magnet (rotor) and electromagnet Stator, with one-phase-on configuration. In the top left figure, North pole of rotor is attracted by South pole of A+ electromagnet. South pole of rotor is attracted by North pole of A+ electromagnet. A and B are stator poles. Image Courtesy: Faulhaber Brochure [1] 100 97 98 99 100
- 26. 03-10-2024 Typical Stepper Motor A typical stepper motor may have parameters like torque 3 kg-cm, operating voltage 12 V, current rating 0.2 V and a step angle 1.8°. The number of rotor teeth is equal to the count for one rotation, i.e. 360°. For any specified angle 𝜃° the count (𝐶) is calculated as: 𝑪 = 𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝒓𝒐𝒕𝒐𝒓 𝒕𝒆𝒆𝒕𝒉 𝟑𝟔𝟎° × 𝜽° Image Courtesy: Faulhaber Reference [1]_https://www.faulhaber.com/fileadmin/user_upload_global/support/MC_Support/Motors/A ppNotes/Faulhaber_AN001_EN.pdf ~ Interesting and well written article 101 Dr. A Bhargavi Haripriya, Asst.Prof., BME, SRMIST From Other Source (1/5) 102 Image Courtesy: Mrs. Suganthi Brindha G., In turn Google Rotors invariably made up of permanent magnet From Other Source (2/5) 103 Single Coil Excitation. Excited coil is shown in red colour Image Courtesy: Mrs. Suganthi Brindha G., In turn Google 104 From Other Source (3/5) TWO Coil Excitation. Each successive pair of adjacent coils is energized in turn. Image Courtesy: Mrs. Suganthi Brindha G., In turn Google 101 102 103 104
- 27. 03-10-2024 105 From Other Source (4/5) HALF Step Sequence. 2 sequences interleaved. normal (4 step) + wave drive (4 step) Total 8 steps. Image Courtesy: Mrs. Suganthi Brindha G., In turn Google 106 Two-Coil Excitation Single-Coil Excitation Interleaved Single- and Two-Coil Excitation Half-Stepping From Other Source (5/5) LCD INTERFACING Unit 3: Interfacing Devices 105 106 107 108