![Verilog code for 4 bit binary parallel
adder
Verilog HDL Dr. H P Koringa
11
module adder4 (A,B,S,C); //module name and port list
input [3..0] A,B; // port declaration
output [3..0] S;
output c;
fulladder add0 (.A[0](a), .B[0](b), .S[0](s),](https://image.slidesharecdn.com/verilog-hdlslideshare-230823115541-8d23e44c/85/Verilog-HDL-11-320.jpg)
![Physical Data Types
Registers (reg):
- Store values
reg [7:0] A; // 8-bit register
reg X; // 1-bit register
How to declare a memory in verilog?
reg [7:0]A [1023:0]; // A is 1K words each 8-bits
Wires ( wire ):
- Do not store a value.
- Represent physical connections between entities.
wire [7:0] A;
wire X;
Verilog HDL Dr. H P Koringa
23](https://image.slidesharecdn.com/verilog-hdlslideshare-230823115541-8d23e44c/85/Verilog-HDL-23-320.jpg)
![Nets/Wire
Verilog HDL Dr. H P Koringa
24
InVerilog default declaration of any variable is net/wire type.
A net/wire does not store value except for trireg net.
Net/wire must be driven by such as gate or continuous
assignment.
If no driver connected to net, it value will be high impedance
(z).
Multi bit wire: wire [31..0] data_bus32](https://image.slidesharecdn.com/verilog-hdlslideshare-230823115541-8d23e44c/85/Verilog-HDL-24-320.jpg)
![Register
Verilog HDL Dr. H P Koringa
29
Declaration
reg <signed><range><list_of_register_variables>;
reg data; // single bit variable
reg signed [7..0] data_bus; // multiple bit signed variable
reg [7..0] data_bus // multiple bit unsigned variable
Integer: This is general reg type variable. Use to manipulate
mathematical calculation.
This is 32 bit integer sign number
Ex: integer data; // 32 bit signed value;](https://image.slidesharecdn.com/verilog-hdlslideshare-230823115541-8d23e44c/85/Verilog-HDL-29-320.jpg)
![Vector
Verilog HDL Dr. H P Koringa
31
Vector bit select: reg[31..0] data;
bit_select=data[7];
Vector part select: reg[31..0] data;
part_select=data[7..0];
reg[0..31] data_bus;
part_select = data_bus [0..7];
Variable vector part select:
variable_name [<starting_bit>+:width]
byte_select = data_bus[16+:8]; //starting from 16 to 23
variable_name [<starting_bit->:width];
byte_select = data_bus[16-:8]; //starting from 9 to 16](https://image.slidesharecdn.com/verilog-hdlslideshare-230823115541-8d23e44c/85/Verilog-HDL-31-320.jpg)
![Verilog HDL Dr. H P Koringa
32
Memory: memory is multi bit array
Ex. reg [7..0] mem_data [0..N-1];
Parameter: To declare constant value inVerilog parameter is
used.
Localparam:
LocalparamWD=32](https://image.slidesharecdn.com/verilog-hdlslideshare-230823115541-8d23e44c/85/Verilog-HDL-32-320.jpg)
![Other operators:
Unary Reduction Operators
Unary reduction operators produce a single bit result from applying the
operator to all of the bits of the operand.
For example, &A will AND all the bits of A.
Concatenation:
C = {A[0], B[1:7]}
Shift Left:
A =A << 2 ; // right >>
Conditional:
A = C > D ? B + 3 : B – 2 ; ex 2x1 mux assign out=control?in1:in0
4x1 mux : assign out = s1? (s0? I3 : i2) : (s0? i1: i0);
Replication:
A = {4{B}}; // will replicate value of B four times and
assign toA
Verilog HDL Dr. H P Koringa
53](https://image.slidesharecdn.com/verilog-hdlslideshare-230823115541-8d23e44c/85/Verilog-HDL-53-320.jpg)
Verilog HDL
- 1. Dr. Hasmukh P Koringa, EC Dept. Government Engineering College Rajkot Verilog HDL
- 2. Acknowledgment Verilog HDL Dr. H P Koringa 2 This presentation is summarize and taken references from various books, papers, websites and presentation on Verilog HDL. I would like to thanks to all professors, researchers and authors who have created such good work on this Verilog HDL. My special thanks to Verilog HDL book author Samir palnitkar.
- 3. Verilog/VHDL is Used Verilog HDL Dr. H P Koringa 3
- 4. What is Verilog? It is a Hardware Description Language ( HDL ) to design the digital system. Two major HDL languages: -Verilog -VHDL Verilog is easier to learn and use (It is like the C language). Verilog HDL is both behavioral and structural language It is case sensitive language Models of verilog HDL can describe both function of design and the components It can also define connection of components in design Verilog HDL Dr. H P Koringa 4
- 5. History Verilog HDL Dr. H P Koringa 5 Verilog was invented by PhilMoorby and Prabhu Goel in 1983/1984 at Gateway Design automation. GDA was purchased by Candence Design system in 1990. Originally, verilog was intended for describe and simulation only. Later support for synthesis added. Cadence transferredVerilog into the public domain under the OpenVerilog International (OVI). Verilog was later submitted to IEEE and became IEEE standard 1364-1995, commonly referred to asVerilog -95.
- 6. History Verilog HDL Dr. H P Koringa 6 Verilog 2001 Extensions toVerilog-95 were submitted back to IEEE to cover few limitation ofVerilog -95. This extension become IEEE Standard 1364-2001 known as Verilog-2001. Verilog -2001 is the dominant flavor ofVerilog supported by the majority of commercial EDA software packages. Today all EDA developer companies are usingVerilog-2001. Verilog 2005 : Don’t be confused with SystemVerilog,Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections. A separate part of theVerilog standard,Verilog-AMS, attemmpts to integrate analog and mixed signal modeling with traditional Verilog.
- 7. History Verilog HDL Dr. H P Koringa 7 SystemVerilog is a superset ofVerilog-2005 with new features and capabilities to aid design-verification and design-modeling. As of 2009, the SystemVerilog andVerilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800- 2009). The advent of hardware verification language such as OpenVera, System C encouraged the development of Superlog by Co-Design Automation Inc. Co-DesignAutomation Inc was later purchased by Synopsys. The foundations of Superlog andVera were donated to Accellera, which later became the IEEE standard 1800-2005: SystemVerilog.
- 8. Design Methodology Verilog HDL Dr. H P Koringa 8 Based on Design Hierarchy Based on Abstraction
- 9. Based on Design Hierarchy Verilog HDL Dr. H P Koringa 9 Top Down Design Methodology Bottom Up Design Methodology
- 10. Top Down Design Methodology Verilog HDL Dr. H P Koringa 10
- 11. Verilog code for 4 bit binary parallel adder Verilog HDL Dr. H P Koringa 11 module adder4 (A,B,S,C); //module name and port list input [3..0] A,B; // port declaration output [3..0] S; output c; fulladder add0 (.A[0](a), .B[0](b), .S[0](s),
- 12. Bottom Up Design Methodology Verilog HDL Dr. H P Koringa 12
- 13. Based on Abstraction Level Verilog HDL Dr. H P Koringa 13 Behavioral Level Data Flow Level Gate Level Switch Level
- 14. Based on Abstraction Level Verilog HDL Dr. H P Koringa 14 Behavioral Level Data Flow Level Gate Level Switch Level
- 15. Lexical Conventions Close to C / C++. Comments: // Single line comment /* multiple lines comments */ /b Black Space /tTab Space /n New line Case Sensitive: Keywords: - Reserved. - lower case. - Examples: module, case, initial, always. Number: decimal, hex, octal, binary Verilog HDL Dr. H P Koringa 15
- 16. Identifier • A ... Z ,a ... z ,0 ... 9 , Underscore , $ Strings are limited to 1024 chars First char of identifier must not be a digit and $ Verilog HDL Dr. H P Koringa 16
- 17. Numbers: <size>’<base format><number> - Size: No. of bits (optional)( default size is 32 bits). - Base format: b: binary d : decimal o : octal h : hexadecimal (DEFAULT IS DECIMAL) Verilog HDL Dr. H P Koringa 17
- 18. Verilog HDL Dr. H P Koringa 18 Underscore character - Underscore can be place between digit of number Data= 16’b 1010_1100_0011_0101; - Note: Never put starting digit as underscore String: var= " Enclose between quotes on a single line“; Verilog support string data type assignment and treated as ASCII character.
- 19. Program Structure Verilog describes a system as a set of modules. Each module has an interface to other modules. Usually: - Each module is put in a separate file. - One top level module that contains: Instances of hardware modules. Test data. Modules can be specified: - Behaviorally. - Structurally. Verilog HDL Dr. H P Koringa 19
- 20. Module General definition module module_name ( port_list ); port declarations; … variable declaration; … description of behavior; … task and function; endmodule module HalfAdder (A, B, Sum Carry); input A, B; output Sum, Carry; assign Sum = A ^ B; //^ denotes XOR assign Carry = A & B; // & denotes AND endmodule Verilog HDL Dr. H P Koringa 20
- 21. Port Verilog HDL Dr. H P Koringa 21 input output inout
- 22. reg and wire data objects may have a value of: - 0 : logical zero - 1 : logical one - x : unknown - z : high impedance Registers are initialized to x at the start of simulation. Any wire not connected to something has the value x. Verilog HDL Dr. H P Koringa 22
- 23. Physical Data Types Registers (reg): - Store values reg [7:0] A; // 8-bit register reg X; // 1-bit register How to declare a memory in verilog? reg [7:0]A [1023:0]; // A is 1K words each 8-bits Wires ( wire ): - Do not store a value. - Represent physical connections between entities. wire [7:0] A; wire X; Verilog HDL Dr. H P Koringa 23
- 24. Nets/Wire Verilog HDL Dr. H P Koringa 24 InVerilog default declaration of any variable is net/wire type. A net/wire does not store value except for trireg net. Net/wire must be driven by such as gate or continuous assignment. If no driver connected to net, it value will be high impedance (z). Multi bit wire: wire [31..0] data_bus32
- 25. Advanced Net types Verilog HDL Dr. H P Koringa 25 tri: it is similar to wire as syntax wise as well as functionally Only difference between tri and wire is, wire denote single driver, while tri means multiple driver.
- 26. Advanced Net Types Verilog HDL Dr. H P Koringa 26 trireg: trireg is wire except that when the net having capacitive effect. Capacitive effect means it can store previous value. Therefore it work on two state. Driver state: when the driver net having value 1,0,x then the driver net follow the driver net. Capacitive state: when driver net unconnected or having high impedance then driver net hold last value.
- 27. Advanced Net Types Verilog HDL Dr. H P Koringa 27 trio & tri1 : trio & tri1 are resistive Pulldown and pullup devices. when the value of the driving net is high then driven net will get a value of the input. When the value of the driving net is low the driven net get a value of pulldown or pullup. Ex: trio y; buff tristate (y,a,ctrl); // when control signal is high, y=a; // when control signal is low ; y=0 instead of high impedence.
- 28. Advanced Net Types Verilog HDL Dr. H P Koringa 28 supply0 & supply1 : these are used to model ground and power. Ex: supply1 VDD; supply0 GND; wor, wand, trior and triand : When one single net is driven by two net having same signal strength then it is difficult to determine the output of driven net. In this case we can use the output oring or anding on both the nets.
- 29. Register Verilog HDL Dr. H P Koringa 29 Declaration reg <signed><range><list_of_register_variables>; reg data; // single bit variable reg signed [7..0] data_bus; // multiple bit signed variable reg [7..0] data_bus // multiple bit unsigned variable Integer: This is general reg type variable. Use to manipulate mathematical calculation. This is 32 bit integer sign number Ex: integer data; // 32 bit signed value;
- 30. Real Verilog HDL Dr. H P Koringa 30 real: This is real register data type. Default value of real data type is zero. Ex: real data=3.34; real data 2e6; //2*10^6 Note: real value can not be passed from one module to another module.
- 31. Vector Verilog HDL Dr. H P Koringa 31 Vector bit select: reg[31..0] data; bit_select=data[7]; Vector part select: reg[31..0] data; part_select=data[7..0]; reg[0..31] data_bus; part_select = data_bus [0..7]; Variable vector part select: variable_name [<starting_bit>+:width] byte_select = data_bus[16+:8]; //starting from 16 to 23 variable_name [<starting_bit->:width]; byte_select = data_bus[16-:8]; //starting from 9 to 16
- 32. Verilog HDL Dr. H P Koringa 32 Memory: memory is multi bit array Ex. reg [7..0] mem_data [0..N-1]; Parameter: To declare constant value inVerilog parameter is used. Localparam: LocalparamWD=32
- 33. Verilog system task Verilog HDL Dr. H P Koringa 33 To perform routing operation (to display output value, simulation time etc.) System task start with $ Ex. $display $monitor $strobe $write $time $finish $recordfile $dumpfile
- 34. Display Verilog HDL Dr. H P Koringa 34 Display Information:Value can be display in binary, hexadecimal, octal or decimal.
- 35. Verilog Compiler Directive Verilog HDL Dr. H P Koringa 35 Compiler directive: compiler directive are define in Verilog or macro. These macro are define like‘<keyword> Ex.‘timescale 1ns/1ns ‘define data_width 8 ‘include ‘ifdefine
- 36. Timescale Verilog HDL Dr. H P Koringa 36 ‘timescale <reference time unit>/<precision>; Ex.‘timescale 1ns/1ps; #1.003; //will be consider as valid delay #1.0009; // will be consider as 1ns delay
- 37. Gate level abstraction Verilog HDL Dr. H P Koringa 37 This is also know as structural abstraction. Design is describe in terms of gates. Very easy to write code if design in structural form. For large circuit its very difficult to implement using gate level.
- 38. Basic gate primitive in Verilog Verilog HDL Dr. H P Koringa 38
- 39. Basic gate primitive in Verilog Verilog HDL Dr. H P Koringa 39
- 40. Basic gate primitive in Verilog Verilog HDL Dr. H P Koringa 40
- 41. Example Verilog design using gate level abstraction 1-bit full adder circuit Expression Sum = (in1 xor in2 xor cin) Carryout = (in1 and in2) or (in2 and cin) or (in1 and cin) in1 in2 cin sum cout 1-bit Full adder circuit Verilog HDL Dr. H P Koringa 41
- 42. Structural model of a full adder circuit module fadd(in1, in2, cin, sum,cout); input in1,in2, cin; output sum, cout; wire x1,a1,a2,a3,o1,o2; xor(x1,in1,in2); xor(sum,x1,cin); and(a1,in1,in2); and(a2,in1,cin); and(a3,in2,cin); or(o1, a1,a2); or(cout,o1,a3); endmodule Verilog HDL Dr. H P Koringa 42
- 43. Gate Delay Verilog HDL Dr. H P Koringa 43 Rise delay Fall delay Turn-off delay Gate output transition to high impedance state (z).
- 44. Gate delay examples Verilog HDL Dr. H P Koringa 44 and # (5) a1 (out,in1,in2); //delay 5 for all transition. and # (4,5) a2(out,in1,in2); //rise =4, fall =5 and turn- off=min (4,5) Bufif0 #(3,4,5) b1(out,in,cntr); //rise=3,fall=4 and turn- off=5;
- 45. Min/Typ/Max values Verilog HDL Dr. H P Koringa 45 For each type of delay-rise, fall and turn-off-three values min, typ and max can be specified. Min/Typ/Max values are used to model devices whose delays varies within min to max range because of IC fabrication process variations. Ex. and #(3:4:5) a1(out,in1,in2); // when one delay is specified. and # (3:4:5, 4:5:6) a2(out,in1,in2); // when two delays are specified. and #(3:4:5, 3:4:5, 4:5:6) a3(out,in1,in2); //when all three delays are specified.
- 46. Data Flow level abstraction Verilog HDL Dr. H P Koringa 46 The gate level approach is very well for small scale logic. With the synthesis tool we can convert data level code to gate level code. All the boolean function can be implemented using data flow level. Expressed using continuous assignment. Expressions, Operators, Operands.
- 47. Continuous Assignment Verilog HDL Dr. H P Koringa 47 This is used to drive a value onto a net. This is equivalent to gate after synthesis. Define by key word assign Ex . assign out = in1& in2; The left hand side value know as output net and it must be net data type. Operands on right hand side can be reg as well wire. Delay can be specified in term of #time_unit assign sum #10 = a+b;
- 48. Delay Type Verilog HDL Dr. H P Koringa 48 Three ways to define delay in continuous assignment statement Regular assignment delay ex. assign #10 dout = in1$in2; Implicit assignment delay ex. wire #10 dout = in1$in2; Net declaration delay. ex. wire #10 dout; assign dout = in1$in2;
- 49. Operators Binary Arithmetic Operators: Operator Type Operator Symbol Operation Performed Number of Operands Arithmetic * multiply two / divide two + add two - subtract two % modulus two ** power one Verilog HDL Dr. H P Koringa 49
- 50. Relational Operators: Operator Type Operator Symbol Operation Performed Number of Operands Relational > greater than two < less than two >= greater than or equal two <= less than or equal two == equality two != inequality two === Case equality two !== Case inequality two Verilog HDL Dr. H P Koringa 50
- 51. Logical Operators: Operator Type Operator Symbol Operation Performed Number of Operands Logical ! logical negation one && logical and two || logical or two Verilog HDL Dr. H P Koringa 51
- 52. Operator Type Operator Symbol Operation Performed Number of Operands Bitwise ~ bitwise negation one & bitwise and two | bitwise or two ^ bitwise xor two ^~ or ~^ bitwise xnor two Bitwise Operators: Verilog HDL Dr. H P Koringa 52
- 53. Other operators: Unary Reduction Operators Unary reduction operators produce a single bit result from applying the operator to all of the bits of the operand. For example, &A will AND all the bits of A. Concatenation: C = {A[0], B[1:7]} Shift Left: A =A << 2 ; // right >> Conditional: A = C > D ? B + 3 : B – 2 ; ex 2x1 mux assign out=control?in1:in0 4x1 mux : assign out = s1? (s0? I3 : i2) : (s0? i1: i0); Replication: A = {4{B}}; // will replicate value of B four times and assign toA Verilog HDL Dr. H P Koringa 53
- 54. Data flow Level Model 4x1 multiplexer module MUX_4x1 (out ,in4 , in3 , in2, in1 , cntrl2, cntrl1); output out; input in1, in2, in3, in4, cntrl1, cntrl2; wire out; assign out = (in1 & ~cntrl1 & ~cntrl2) | (in2 & ~cntrl1 & cntrl2)| (in3 & cntrl1 & ~cntrl2)| (in4 & cntrl1 & cntrl2); endmodule Verilog HDL Dr. H P Koringa 54
- 55. Data Flow model of a full adder circuit module fadd(in1, in2, cin, sum,cout); input in1,in2, cin; output sum, cout; assign {cout, sum} = in1 + in2 + cin ; endmodule Verilog HDL Dr. H P Koringa 55
- 56. Behavioral level Abstraction Verilog HDL Dr. H P Koringa 56 Modelling circuit with logic gate and continuous assignments is quite complex. Behavioral level is the higher level of abstraction in which model can be defined as its functional behavioral. Verilog behavioral models contain structured procedural statements that control the simulation and manipulate variables. Two types of structured procedure constructs Initial and always
- 57. initial Statement always Statement initial Statement : Executes only once always Statement : Executes in a loop Example: … initial begin Sum = 0; Carry = 0; end … … always @(A or B) begin Sum = A ^ B; Carry = A & B; end … Two Procedural Constructs Verilog HDL Dr. H P Koringa 57
- 58. Procedural Assignment Verilog HDL Dr. H P Koringa 58 Procedural assignment , are used or updating reg, integer, time and memory variables. Continuous assignment Procedural assignment Drives net/wire variables only Drive reg, integer, time and memory variables Update output whenever an input operand changes its value Procedural assignment update the value of reg variables under the control of procedural flow constructs that surround them
- 59. Blocking assignments Verilog HDL Dr. H P Koringa 59 Blocking assignments statements are executed in the order they are specified in a sequential block. The = operator is used for blocking assignments. Ex. reg a,b,c,d; initial begin a=1’b0; b=1’b1; # 5 c = a&b; #10 d = a| b; end
- 60. Nonblocking assignments Verilog HDL Dr. H P Koringa 60 Nonblocking assignments allows scheduling of assignments without blocking execution of the statements that follow in sequential block. The <= operator is used to specify nonblocking assignments. Ex. reg a,b,c,d; initial begin a=1’b0; b=1’b1; c <= # 5 a&b; d <= #10 a| b; end
- 61. Nonblocking assignments Verilog HDL Dr. H P Koringa 61 Operation of nonblocking assignments 1.The right hand side expressions are evaluated, results are stored internally in simulator. 2. At the end of time step, in which the given delay has expired or the appropriate event has taken place, the simulator executes the assignments by assigning the stored value to the left-hand side. Ex. a<=b; b <= a; Sequence to write statements is not important.
- 62. Timing control Verilog HDL Dr. H P Koringa 62 Delay basedTiming Control Intra-AssignmentTiming Controls Inter-AssignmentTiming Controls Zero-Assignment Delay Even basedTiming Control Regular Event Control Named Event Control Event OR Control Level SensitiveTiming Control
- 63. Conditional Statement Verilog HDL Dr. H P Koringa 63 The if statement Syntax: if (conditional_expression ) statement; else statement; module mux (out,in0,in1,sel); input in1,in2,sel; output out; reg out; alway @(in1 @ in2 @ sel) if (sel==1) out=in1; else out = in0; endmodule
- 64. The if else statement Verilog HDL Dr. H P Koringa 64
- 65. Case Statement Verilog HDL Dr. H P Koringa 65 The case statement Syntax: case(Expression ) Alternative 1: statement1; Alternative 1: statement1; Alternative 1: statement1; Default: statement_default; endcase module mux (out,in0,in1,sel); input in1,in2,sel; output out; reg out; alway @(in1 @ in2 @ sel) case (sel) 1’b0: out = in0; 1’b1: out = in1; default: $display(“Invalid”); endcase endmoule
- 66. Looping Constructs Verilog HDL Dr. H P Koringa 66 There are four looping constructs in Verilog are while, for, repeat and forever. All of these can only appear inside initial and always blocks. while: executes a statement or set of statements while a condition is true. for: executes a statement or a set of statements. This loop can initialise, test and increment the index variable in a neat fashion. repeat: executes a statement or a set of statements a fixed umber of times. forever: executes a statement or a set of statements forever and even, or until the simulation is halted.
- 67. While Loop Verilog HDL Dr. H P Koringa 67 Syntax: while(condition) begin statement1; statement2; statement3; --- end the while loop executes while condition is true, the conditional can be consist of logical expression. ‘define jugvol 100; module jug_and_cup; variable jug, cup; initial begin jug = 0; cup = 10; while ( jug<jugvol) begin jug = jug +cup; end end endmodule
- 68. for Loop Verilog HDL Dr. H P Koringa 68 Syntax: for(initialisation;conditional; update) begin statement1; statement2; statement3; --- end same as the for loop of C module for_loop_ex; variable data, index; initial begin data =0; for ( index=0; index<10; index = index+1) begin data= data+5; end end endmoule
- 69. repeat Loop Verilog HDL Dr. H P Koringa 69 Syntax: repeat(conditional) begin statement1; statement2; statement3; --- end •repeat loop execute fixed number of times. •Conditional can be constant, variable or signal value but must be number. •If conditional is x or z then it treated as zero. module jug_and_cup; variable jug, cup, count; initial begin jug =0; cup=10; count = 5; repeat( count) begin jug = jug +cup; end end endmodule
- 70. forever Loop Verilog HDL Dr. H P Koringa 70 Syntax: forever statement; • Forever loop executes continuously until end of simulation is requested by a $finish. •It is similar to while loop whose condition is always true. •The forever statement must be used with timing control to limit the execution. reg clock; initial begin clock=1’b0; forever #5 clock = ~clock; end initial #2000 $finish;
- 71. Tasks and Functions Verilog HDL Dr. H P Koringa 71 Tasks and functions provide the ability to execute common procedures from several different places in a description. They also provide a means of breaking up large procedures into smaller ones to make it easier to read and debug the source descriptions. Input, output and inout argument values can be passed into and out of both tasks and functions.
- 72. Tasks and Functions Verilog HDL Dr. H P Koringa 72 A function must execute in one simulation time unit; a task can contain time controlling statements. A function cannot enable a task bit task can enable other task and functions. A function must have at list one input argument while task can have zero or more arguments of any type. A function return a single value while task does not return a value The purpose of function is to respond to an input value by returning a single value. A task can support multiple goals and can calculate multiple result values. However, only the output or inout arguments pass result values back fro the invocation of a task. A Verilog model uses a functional as an operand in an expression. The value of that operand is the value returned by the function.
- 73. Task Verilog HDL Dr. H P Koringa 73 Syntax: Syntax: task <name_of_task> <parameter_declaration> <input_declaration> <output_declaration> <inout_declaration> <reg_declaration> <time_declaration> <integer_declaration> <real_declaration> <event_declaration> <task body> endtask Example: task clk_gen; input integer clk_period; begin clk = 1’b0; forever #clk_period/2 clk = ~clk; end endtask
- 74. Function Verilog HDL Dr. H P Koringa 74 Syntax: function<range_or_type?><name_of_function> <parameter_declaration> <input_declaration> <output_declaration> <inout_declaration> <reg_declaration> <time_declaration> <integer_declaration> <real_declaration> <event_declaration> endtask Example: Function integer add; input integer data1; input integer data2; begin add = data1 +data2; end endfunction
- 75. Calling a task and Function Verilog HDL Dr. H P Koringa 75 module task_funct_test; integer data_type; initial begin task_name(task_parameter); data_type = function_name(funct_parameter); end assign funct_value = function_name(funct_parameter); endmodule
- 76. Q ? Verilog HDL Dr. H P Koringa 76