SlideShare a Scribd company logo
A Project On VLSI Laboratory
Name of the project:
Verilog RTL for a 32-bit Carry
Select Adder (CSA)
To: Mr. Salahuddin Ahmed (Lecturer)
By: Md. Aman Ullah
Id: 021132091
 An adder is a digital circuit that performs addition of
numbers.
 In processor it is used to calculate addresses, table indices,
and similar operations.
 It can be constructed for many numerical representations,
the most common adders operate on binary numbers.
ADDER MEANS???
Objectives:
 Write Verilog RTL for a 32-bit Carry Select Adder (CSA) that runs at 4GHz.
Simulate, synthesize and physical design of that adder
 Directions below to create the 32-bit CSA
 A 4-bit Carry Look Ahead (CLA) adder
 Combine 8-stages of the CLA adder to create the 32-bit CSA
 Use 4-bit 2-to-1 mux to choose the sum from each set of CLA
 Use 1-bit 2-to-1 mux to select the carry for the next stage
Carry Look ahead adder:
CLA is a type of adder using in digital logic.
A carry look ahead adder improves speed
by reducing amount of time required to
determine carry bits.
 A carry-lookahead adder (CLA) or fast
adder is a type of adder used in digital
logic.
 A carry-lookahead adder improves
speed by reducing the amount of time
required to determine carry bits.
Carry Look ahead adder:

 A carry-select adder is a particular way to implement
an adder, which is a logic element that computes the -bit
sum of two -bit numbers. The carry-select adder is simple
but rather fast.
Carry Select Adder
Carry Select Adder
44
4
C3
44
4
44
4
4-bit 2to1 MUX
4
C (1)
C (0)
S3 ~ S0
A3 ~ A0 B3 ~ B0
S7 ~ S4
C0●
A7 ~ A4 B7 ~ B4
A7 ~ A4 B7 ~ B4
1-bit 2to 1 MUX
MULTIPLEXER(MUX):
A multiplexer (or mux) is a device that selects one of
several analog or digital input signals and forwards the
selected input into a single line
Simulation Output:
Synthesis: Report Timing
Report Timing:
Report Power:
Physical Design
Setup Mode:
Thank You

More Related Content

PPTX
Ripple Carry Adder
PDF
PPTX
Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)
PPTX
Lecture 10
PDF
Lect2 organization 2
PPTX
Half adder and full adder | Digital electronics | engineering
PPTX
Programmable Logic Controls training day 1
Ripple Carry Adder
Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)
Lecture 10
Lect2 organization 2
Half adder and full adder | Digital electronics | engineering
Programmable Logic Controls training day 1

What's hot (20)

PPTX
Unit 4-booth algorithm
PPTX
Programmable Logic Controls training day 2
PPTX
Lecture 8
PPTX
Optimized Floating-point Complex number multiplier on FPGA
PPTX
Adder
PPTX
Fluke 173x hand on final, Milano meeting
PPTX
Co ppt
PPTX
Lecture 2
PPT
Computer organization prashant odhavani- 160920107003
PPTX
Half Adder_Digital logic_
PPTX
Half Adder and Full Adder
PPTX
Lecture15 fsm i_ic
DOCX
Logic gates
PPTX
Indoor Wireless Localization - Zigbee
PPTX
Adder Presentation
PPTX
Half adder and full adder
PDF
Analysis and Design of PID controller with control parameters in MATLAB and S...
PPTX
Computer arithmetics (computer organisation & arithmetics) ppt
PPT
Half Adder & Full Adder
DOCX
Vlsi ieee 2014 be, b.tech_completed list(m)
Unit 4-booth algorithm
Programmable Logic Controls training day 2
Lecture 8
Optimized Floating-point Complex number multiplier on FPGA
Adder
Fluke 173x hand on final, Milano meeting
Co ppt
Lecture 2
Computer organization prashant odhavani- 160920107003
Half Adder_Digital logic_
Half Adder and Full Adder
Lecture15 fsm i_ic
Logic gates
Indoor Wireless Localization - Zigbee
Adder Presentation
Half adder and full adder
Analysis and Design of PID controller with control parameters in MATLAB and S...
Computer arithmetics (computer organisation & arithmetics) ppt
Half Adder & Full Adder
Vlsi ieee 2014 be, b.tech_completed list(m)
Ad

Similar to Vlsi project presentation (20)

PDF
Paper id 37201520
PPT
Short.course.introduction.to.vhdl for beginners
PPT
Short.course.introduction.to.vhdl
PDF
implementation and design of 32-bit adder
PDF
Hardware accelerator for financial application in HDL and HLS, SAMOS 2017
PDF
128-Bit Area Efficient Reconfigurable Carry Select Adder
PDF
Iaetsd vlsi implementation of efficient convolutional
PDF
J43015355
PDF
IJETT-V9P226
PDF
I43024751
PDF
Hx3414601462
PPTX
Onnc intro
PPTX
THE PROCESSOR
PDF
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...
PPT
32-bit unsigned multiplier by using CSLA & CLAA
PDF
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
PPTX
Single Cycle Processing
PPTX
RIPPLE CARRY ADDER.pptx
PPTX
Final Video PPT V_05 Final UNIT 3 part 2_DL and COA Programming.pptx
PDF
Cadancesimulation
Paper id 37201520
Short.course.introduction.to.vhdl for beginners
Short.course.introduction.to.vhdl
implementation and design of 32-bit adder
Hardware accelerator for financial application in HDL and HLS, SAMOS 2017
128-Bit Area Efficient Reconfigurable Carry Select Adder
Iaetsd vlsi implementation of efficient convolutional
J43015355
IJETT-V9P226
I43024751
Hx3414601462
Onnc intro
THE PROCESSOR
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...
32-bit unsigned multiplier by using CSLA & CLAA
Design Of 64-Bit Parallel Prefix VLSI Adder For High Speed Arithmetic Circuits
Single Cycle Processing
RIPPLE CARRY ADDER.pptx
Final Video PPT V_05 Final UNIT 3 part 2_DL and COA Programming.pptx
Cadancesimulation
Ad

Recently uploaded (20)

PPTX
NEW EIA PART B - Group 5 (Section 50).pptx
PPTX
UNIT III - GRAPHICS AND AUDIO FOR MOBILE
PPTX
LITERATURE CASE STUDY DESIGN SEMESTER 5.pptx
PPT
pump pump is a mechanism that is used to transfer a liquid from one place to ...
PPTX
rapid fire quiz in your house is your india.pptx
PDF
Pongal 2026 Sponsorship Presentation - Bhopal Tamil Sangam
PPTX
CLASS_11_BUSINESS_STUDIES_PPT_CHAPTER_1_Business_Trade_Commerce.pptx
PPT
robotS AND ROBOTICSOF HUMANS AND MACHINES
PPTX
Presentation.pptx anemia in pregnancy in
PDF
UNIT 1 Introduction fnfbbfhfhfbdhdbdto Java.pptx.pdf
PDF
Introduction-to-World-Schools-format-guide.pdf
PPTX
DOC-20250430-WA0014._20250714_235747_0000.pptx
PDF
Chalkpiece Annual Report from 2019 To 2025
PDF
Test slideshare presentation for blog post
PPTX
BSCS lesson 3.pptxnbbjbb mnbkjbkbbkbbkjb
PPTX
Entrepreneur intro, origin, process, method
PPTX
Causes of Flooding by Slidesgo sdnl;asnjdl;asj.pptx
PPTX
22CDO02-IMGD-UNIT-I-MOBILE GAME DESIGN PROCESS
PPTX
Media And Information Literacy for Grade 12
PPT
EthicsNotesSTUDENTCOPYfghhnmncssssx sjsjsj
NEW EIA PART B - Group 5 (Section 50).pptx
UNIT III - GRAPHICS AND AUDIO FOR MOBILE
LITERATURE CASE STUDY DESIGN SEMESTER 5.pptx
pump pump is a mechanism that is used to transfer a liquid from one place to ...
rapid fire quiz in your house is your india.pptx
Pongal 2026 Sponsorship Presentation - Bhopal Tamil Sangam
CLASS_11_BUSINESS_STUDIES_PPT_CHAPTER_1_Business_Trade_Commerce.pptx
robotS AND ROBOTICSOF HUMANS AND MACHINES
Presentation.pptx anemia in pregnancy in
UNIT 1 Introduction fnfbbfhfhfbdhdbdto Java.pptx.pdf
Introduction-to-World-Schools-format-guide.pdf
DOC-20250430-WA0014._20250714_235747_0000.pptx
Chalkpiece Annual Report from 2019 To 2025
Test slideshare presentation for blog post
BSCS lesson 3.pptxnbbjbb mnbkjbkbbkbbkjb
Entrepreneur intro, origin, process, method
Causes of Flooding by Slidesgo sdnl;asnjdl;asj.pptx
22CDO02-IMGD-UNIT-I-MOBILE GAME DESIGN PROCESS
Media And Information Literacy for Grade 12
EthicsNotesSTUDENTCOPYfghhnmncssssx sjsjsj

Vlsi project presentation

  • 1. A Project On VLSI Laboratory Name of the project: Verilog RTL for a 32-bit Carry Select Adder (CSA) To: Mr. Salahuddin Ahmed (Lecturer) By: Md. Aman Ullah Id: 021132091
  • 2.  An adder is a digital circuit that performs addition of numbers.  In processor it is used to calculate addresses, table indices, and similar operations.  It can be constructed for many numerical representations, the most common adders operate on binary numbers. ADDER MEANS???
  • 3. Objectives:  Write Verilog RTL for a 32-bit Carry Select Adder (CSA) that runs at 4GHz. Simulate, synthesize and physical design of that adder  Directions below to create the 32-bit CSA  A 4-bit Carry Look Ahead (CLA) adder  Combine 8-stages of the CLA adder to create the 32-bit CSA  Use 4-bit 2-to-1 mux to choose the sum from each set of CLA  Use 1-bit 2-to-1 mux to select the carry for the next stage
  • 4. Carry Look ahead adder: CLA is a type of adder using in digital logic. A carry look ahead adder improves speed by reducing amount of time required to determine carry bits.  A carry-lookahead adder (CLA) or fast adder is a type of adder used in digital logic.  A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits.
  • 5. Carry Look ahead adder: 
  • 6.  A carry-select adder is a particular way to implement an adder, which is a logic element that computes the -bit sum of two -bit numbers. The carry-select adder is simple but rather fast. Carry Select Adder
  • 7. Carry Select Adder 44 4 C3 44 4 44 4 4-bit 2to1 MUX 4 C (1) C (0) S3 ~ S0 A3 ~ A0 B3 ~ B0 S7 ~ S4 C0● A7 ~ A4 B7 ~ B4 A7 ~ A4 B7 ~ B4 1-bit 2to 1 MUX
  • 8. MULTIPLEXER(MUX): A multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line