VLSI - UNIT III (1)(1).pptxyujh vlsi nodes

UNIT III
SEQUENTIAL CIRCUIT DESIGN
EC3552 VLSI and Chip Design
1

Syllabus
Static latches and Registers, Dynamic
latches and Registers, Pulse Registers,
Sense Amplifier Based Register,
Pipelining, Schmitt Trigger, Monostable
Sequential Circuits, Astable Sequential
Circuits.
Timing Issues: Timing Classification of
Digital System, Synchronous Design.
2

Introduction
 Combinational circuits in which the output
is a function of the current inputs.
 Sequential circuits in which the output
depends on previous as well as current
inputs.
 Sequential circuits are usually designed with
flip-flops or latches, which are sometimes
called memory elements.
3

Sequencing Static Circuits
 latches and flip-flops are the two most commonly
used sequencing elements.
 Both have three terminals: data input (D), clock (clk),
and data output (Q).
 The latch is transparent when the clock is high and
opaque when the clock is low; in other words, when the
clock is high, D flows through to Q as if the latch were
just a buffer, but when the clock is low, the latch holds
its present Q output even if D changes.
 The flip-flop is an edge-triggered device that copies D
to Q on the rising edge of the clock and ignores D at all
other times.
4

Static Latches and Registers
1. The Bistability Principle
 Static memories use positive feedback to
create a bistable circuit - a circuit having
two stable states that represent 0 and 1.
 In absence of any triggering, the circuit
remains in a single state and hence
remembers a value.
 A trigger pulse must be applied to change
the state of the circuit.
 Another common name for a bistable
circuit is flip-flop
5

2. SR Flip-Flops
 The cross-coupled NOR gates shown in the figure. The
second input of the NOR gates is connected to the
trigger inputs (S and R), that make it possible to force
the outputs Q and Q to a given state.
 These outputs are complimentary (except for the SR =
11 state). When both S and R are 0, the flip-flop is in a
quiescent state and both outputs retain their value.
 If a positive (or 1) pulse is applied to the S input, the Q
output is forced into the 1 state (with Q going to 0). Vice
versa, a 1 pulse on R resets the flip-flop and the Q
output goes to 0.
6

 Clocked SR flip-flop - a level-sensitive positive latch
is shown in Figure.
 It consists of a cross-coupled inverter pair, plus 4
extra transistors to drive the flip-flop from one state to
another and to provide clocked operation.
 The presented flip-flop does not consume any static
power.
 In steady-state, one inverter resides in the high state,
while the other one is low. No static paths between
VDD and GND can exist except during switching. 7

3. Multiplexer-Based Latches
 Multiplexer based latches can provide similar functionality to the
SR latch, but has the important added advantage that the sizing of
devices only affects performance and is not critical to the
functionality.
 Figure shows an implementation of static positive and negative
latches based on multiplexers.
 For a negative latch, when the clock signal is low, the input 0 of
the multiplexer is selected, and the D input is passed to the
output.
 When the clock signal is high, the input 1 of the multiplexer,
which connects to the output of the latch, is selected. The feedback
holds the output stable while the clock signal is high.
 Similarly in the positive latch, the D input is selected when clock
is high, and the output is hold (using feedback) when clock is low.8

9
4. Master-Slave Edge-Triggered Register
 The most common approach for constructing an edge-
triggered register is to use a master-slave
configuration, as shown in Figure.
 The register consists of cascading a negative latch
(master stage) with a positive latch (slave stage).
 A multiplexer-based latch is used in this particular
implementation, although any latch could be used.
 On the low phase of the clock, the master stage is
transparent, and the D input is passed to the master
stage output QM.

10
 During this period, the slave stage is in the hold
mode, keeping its previous value using feedback.
 On the rising edge of the clock, the master stage
stops sampling the input, and the slave stage
starts sampling.
 During the high phase of the clock, the slave
stage samples the output of the master stage
(QM), while the master stage remains in a hold
mode.

11
 A complete transistor-level implementation of a the master-slave
positive edge-triggered register is shown in the Figure.
 The multiplexer is implemented using transmission gates as
discussed in the previous section.
 When the clock is low (CLK = 1), T1 is on and T2 is off, and the D
input is sampled onto node QM . During this period, T3 is off and T4
is on and the cross-coupled inverters (I5 , I6) holds the state of
the slave latch.
 When the clock goes high, the master stage stops sampling the
input and goes into a hold mode.
 T1 is off and T2 is on, and the cross coupled inverters I3 and I4
holds the state of QM.
 Also, T3 is on and T4 is off, and QM is copied to the output Q.

12
Timing Properties of Multiplexer-based
Master-Slave Registers:
Registers are characterized by three important
timing parameters: the set-up time, the hold
time and the propagation delay.
 Set-up time - It is the time before the rising
edge of the clock that the input data D must
become valid.
 Hold time - The time that the input must be
held stable after the rising edge of the clock.
 Propagation delay - It is the time for the
value of QM to propagate to the output Q.

13
5. Low-Voltage Static Latches
 The scaling of supply voltages is critical for low power
operation.
 Unfortunately, certain latch structures don’t function
at reduced supply voltages.
 Scaling to low supply voltages hence requires the use of
reduced threshold devices.
 However, this has the negative effect of exponentially
increasing the sub-threshold leakage power.
 When the registers are constantly accessed, the leakage
energy is typically insignificant compared to the
switching power.
 However, with the use of conditional clocks, it is
possible that registers are idle for extended periods and
the leakage energy expended by registers can be quite
significant.

Dynamic Latches and Registers
Static Logic:
Storage in a static sequential circuit
relies on the concept that a cross -
coupled inverter pair produces a
bistable element and can thus be used
to memorize binary values.
This approach has the useful property
that a stored value remains valid as
long as the supply voltage is applied
to the circuit, hence the name static.
The major disadvantage of the static
gate, however, is its complexity. 14

15
Dynamic Logic:
 In dynamic logic – charge stored on a
capacitor can be used to represent a logic
signal.
 The absence of charge denotes a 0, while its
presence stands for a stored 1.
 No capacitor is ideal, unfortunately, and some
charge leakage is always present.
 A stored value can hence only be kept for a
limited amount of time, typically in the range of
milliseconds.
 If one wants to preserve signal integrity, a
periodic refresh of its value is necessary. Hence
the name dynamic storage.

1. Dynamic Transmission-Gate Edge-triggered Registers
 A fully dynamic positive edge-triggered register based on the master-
slave concept is shown in the Figure.
 When CLK = 0, the input data is sampled on storage node 1, which has
an equivalent capacitance of C1 consisting of the gate capacitance of I1,
the junction capacitance of T1, and the overlap gate capacitance of T1.
 During this period, the slave stage is in a hold mode, with node 2 in a
high-impedance (floating) state.
 On the rising edge of clock, the transmission gate T2 turns on, and the
value sampled on node 1 right before the rising edge propagates to the
output Q.
 Node 2 now stores the inverted version of node 1. This
implementation of an edge-triggered register is very efficient as it
requires only 8 transistors. 16

 The set-up time of this circuit is simply the
delay of the transmission gate, and
corresponds to the time it takes node 1 to
sample the D input.
 The hold time is approximately zero, since the
transmission gate is turned off on the clock
edge and further inputs changes are ignored.
 The propagation delay (tc-q) is equal to two
inverter delays plus the delay of the
transmission gate T2.
 One important consideration for such a dynamic
register is that the storage nodes (i.e., the state)
has to be refreshed at periodic intervals to
prevent a loss due to charge leakage, due to
diode leakage as well as sub-threshold currents.
17

18
Impact of non-overlapping clocks:
 During the 0-0 overlap period, the NMOS of T1 and the
PMOS of T2 are simultaneously on, creating a direct
path for data to flow from the D input of the register to
the Q output. This is known as a race condition.
 The same is true for the 1-1 overlap region, where an
input-output path exists through the PMOS of T1 and
the NMOS of T2.
 The overlap period constraint is given as:
toverlap 0–0 < tT1 + tI1 + tT2
 Similarly, the constraint for the 1-1 overlap is given as:
thold > toverlap1–1

19
2. C2
MOS - A Clock-Skew Insensitive Approach
The C2
MOS Register:
 Figure shows an ingenious positive edge -
triggered register, based on a master-slave
concept insensitive to clock overlap.
 This circuit is called the C2
MOS (Clocked CMOS)
register, and operates in two phases.

 CLK = 0 (CLK = 1): The first tri-state driver is
turned on, and the master stage acts as an
inverter sampling the inverted version of D on
the internal node X. The master stage is in the
evaluation mode. Meanwhile, the slave section
is in a high-impedance mode, or in a hold
mode. Both transistors M7 and M8 are off,
decoupling the output from the input. The
output Q retains its previous value stored on
the output capacitor CL2
 The roles are reversed when CLK = 1: The
master stage section is in hold mode (M3 - M4
off), while the slave section evaluates (M7 - M8
on). The value stored on CL1 propagates to the
output node through the slave stage which acts
20

Dual-edge Registers:
 The edge-triggered registers
that sample the input data on
only one of the clock edges
(rising or falling).
 It is also possible to design
sequential circuits that sample
the input on both edges.
 The Figure shows a
modification of the C2
MOS
register to enable sampling on
both edges.
 It consists of two parallel
master-slave based edge-
triggered registers, whose
outputs are multiplexed
using the tri-state drivers.
21

22
 When clock is high, the positive latch composed of
transistors M1 - M4 is sampling the inverted D input on
node X.
 Node Y is held stable, since devices M9 and M10 are
turned off.
 On the falling edge of the clock, the top slave latch M5 -
M8 turns on, and drives the inverted value of X to the
Q output.
 When clock is low, the bottom master latch (M1, M4,
M9, M10) is turned on, sampling the inverted D input
on node Y.
 Note that the devices M1 and M4 are reused, reducing
the load on the D input.
 On the rising edge, the bottom slave latch conducts,
and drives the inverted version of Y on node Q. Data
hence changes on both edges.

23
3. True Single-Phase Clocked Register
(TSPCR)
 The True Single-Phase Clocked
Register (TSPCR), uses a single clock.
 The basic single-phase positive and
negative latches are shown in Figure.

24
 For the positive latch, when CLK is high, the latch is
in the transparent mode and corresponds to two
cascaded inverters; the latch is non-inverting, and
propagates the input to the output.
 On the other hand, when CLK = 0, both inverters are
disabled, and the latch is in hold-mode. Only the
pull-up networks are still active, while the pull-down
circuits are deactivated.
 As a result of the dual-stage approach, no signal can
ever propagate from the input of the latch to the
output in this mode.
 A register can be constructed by cascading positive
and negative latches.
 Advantages: a single clock phase used, High
performance, Reduced delay overhead, Less
complexity.
 Disadvantages: increase in the number of transistors

Pulse Registers
 We have used the master-slave configuration to
create an edge-triggered register.
 A fundamentally different approach for
constructing a register uses pulse signals.
 The idea is to construct a short pulse around
the rising (or falling) edge of the clock.
 This pulse acts as the clock input to a latch,
sampling the input only in a short window.
 Race conditions are thus avoided by keeping
the opening time of the latch very short.
 The combination of the glitch-generation
circuitry and the latch results a positive
edge-triggered register.
25

 Figure shows an example circuit for
constructing a short intentional glitch on
each rising edge of the clock.
26

 When CLK = 0, node X is charged up to VDD.
 On the rising edge of the clock, there is a short period of time
when both inputs of the AND gate are high, causing CLKG to
go high.
 This in turn activates MN, pulling X and eventually CLKG low.
 The length of the pulse is controlled by the delay of the AND
gate and the two inverters.
 The delay exists between the rising edges of the input clock
(CLK) and the glitch clock (CLKG) also equal to the delay of the
AND gate and the two inverters.
 If set-up time and hold time are measured in reference to the
rising edge of the glitch clock, the set-up time is essentially
zero, the hold time is equal to the length of the pulse and the
propagation delay (tc-q) equals two gate delays.
• Advantages: Reduced clock load, Required less transistors,
The glitch-generation circuitry can be amortized over multiple
register bits
 Disadvantages: Increase in verification complexity.
27

Sense-Amplifier Based Registers
 Figure introduces another technique that uses
a sense amplifier structure to implement an
edge-triggered register.
28

 Sense-amplifier circuits accept small input signals
and amplify them to generate rail-to-rail swings.
 Sense amplifier circuits are used extensively in
memory cores and in low swing bus drivers to
amplify small voltage swings present in heavily
loaded wires.
 The circuit shown in Figure uses a precharged front-
end amplifier that samples the differential input
signal on the rising edge of the clock signal.
 The outputs of front-end are fed into a NAND cross-
coupled SR FF that holds the data and guarantees
that the differential outputs switch only once per
clock cycle.
 The differential inputs in this implementation don’t
have to have rail-to-rail swing and hence this register
can be used as a receiver for a reduced swing
differential bus. 29

 The core of the front-end consists of a cross-
coupled inverter (M5-M8), whose outputs (L1 and
L2) are precharged using devices M9 and M10
during the low phase of the clock.
 As a result, PMOS transistors M7 and M8 to be
turned off and the NAND SR FF is holding its
previous state.
 Transistor M1 is similar to an evaluate switch in
dynamic circuits and is turned off ensuring that
the differential inputs don’t affect the output
during the low phase of the clock.
 On the rising edge of the clock, the evaluate
transistor turns on and the differential input pair
(M2 and M3) is enabled, and the difference
between the input signals is amplified on the
output nodes on L and L 30

 The cross-coupled inverter pair flips to one of its the
stable states based on the value of the inputs. For
example, if IN is 1, L1 is pulled to 0, and L2 remains
at VDD.
 The shorting transistor, M4, is used to provide a DC
leakage path from either node L3, or L4, to ground.
 This is necessary to accommodate the case where the
inputs change their value after the positive edge of
CLK has occurred, resulting in either L3 or L4 being
left in a high-impedance state with a logical low
voltage level stored on the node.
 Without the leakage path that node would be
susceptible to charging by leakage currents.
 The latch could then actually change state prior to
the next rising edge of CLK! . This is best illustrated
graphically, as shown in the Figure. 31

Pipelining
 Pipelining is a popular design technique often
used to accelerate the operation of the
datapaths in digital processors.
 The figure shows an example circuit is to
compute log(|a + b|), where both a and b
represent streams of numbers, that is, the
computation must be performed on a large set
of input values.
33

 The minimal clock period Tmin necessary to
ensure correct evaluation is given as:
Tmin = tc-q + tpd,logic + tsu
Where
 tc-q - Propagation delay
 tpd,logic- worst-case delay path through the
combinational network
 Tsu - Setup time
 The adder unit is active during the 1/3 of the
period and remains idle, it does no useful
computation during the other 2/3 of the period.
34

 Pipelining is a technique to improve the
resource utilization, and increase the
functional throughput.
 Assume that we introduce registers
between the logic blocks, as shown in
Figure.
35

 The result for the data set (a1, b1) only appears at the
output after three clock-periods.
 At that time, the circuit has already performed parts of the
computations for the next data sets, (a2, b2) and (a3, b3).
 The computation is performed in an assembly-line fashion,
hence the name pipeline.
 This effectively reduces the value of the minimum
allowable clock period:
Tmin,pipe = tc-q + max (tpd,add, tpd,abs, tpd,log) + tsu
36

Latch vs. Register-Based Pipelines
 Pipelined circuits can be constructed using level-
sensitive latches instead of edge-triggered registers.
 The pipeline system shown in figure is implemented
based on pass-transistor-based positive and
negative latches instead of edge triggered registers.
37

 Latch-based systems give significantly more
flexibility in implementing a pipelined system,
and offers higher performance.
 When the clocks CLK and CLK are non-
overlapping, correct pipeline operation is
obtained.
 Input data is sampled on C1 at the negative
edge of CLK and the computation of logic
block F starts; the result stored on C2 on the
falling edge of CLK, and the computation of
logic block G starts.
 The non-overlapping of the clocks ensures
correct operation. 38

 The value stored on C2 at the end of the CLK low
phase is the result of passing the previous input
(stored on the falling edge of CLK on C1) through
the logic function F.
 When overlap exists between CLK and CLK, the
next input is already being applied to F, and its
effect might propagate to C2 before CLK goes
low.
 A race develops between the previous input and
the current one. 39

NORA CMOS
A Logic Style for Pipelined Structures
 The latch-based pipeline circuit can also be
implemented using C2
MOS latches, as shown in Figure.
 This topology has one additional, important property:
 A C2
MOS based pipelined circuit is race-free as long as
all the logic functions F between the latches are non-
inverting. 40

 During a (0-0) overlap between CLK and CLK, all
C2
MOS latches, simplify to pure pull-up networks.
 The only way a signal can race from stage to stage
under this condition is when the logic function F is
inverting as illustrated in following Figure.
 where F is replaced by a single, static CMOS inverter.
41

 Logic and latch are clocked in such a way that
both are simultaneously in either evaluation,
or hold (precharge) mode.
 A block that is in evaluation during CLK = 1
is called a CLK-module, while the inverse is
called a CLK-module.
 A NORA datapath consists of a chain of
alternating CLK and CLK modules.
 While one class of modules is precharging
with its output latch in hold mode, preserving
the previous output value, the other class is
evaluating.
 Data is passed in a pipelined fashion from
module to module.
42

Schmitt Trigger
Definition
 A Schmitt trigger is a device with two important properties:
 It responds to a slowly changing input waveform with a
fast transition time at the output.
 The voltage-transfer characteristic of the device displays
different switching thresholds for positive and
negative going input signals. The switching thresholds
for the low-to-high and high-to-low transitions are called
VM+ and VM- respectively. The hysteresis voltage is defined
as the difference between the two switching thresholds.
43

 One of the main uses of the Schmitt trigger
is to turn a noisy or slowly varying input
signal into a clean digital output signal.
 The “secret” behind the Schmitt trigger
concept is the use of positive feedback.
44

Monostable Sequential Circuits
 A monostable element is a circuit that generates a
pulse of a predetermined width everytime the
quiescent circuit is triggered by a pulse or
transition event.
 It is called monostable because it has only one
stable state (the quiescent one).
 This circuit, also called a one-shot, is useful in
generating pulses of a known length.
 The implementation of one-shots is the use of a
simple delay element to control the duration of the
pulse is illustrated in Figure.
45

Astable Sequential Circuits
 An astable circuit has no stable states.
 The output oscillates back and forth
between two quasi-stable states with a
period determined by the circuit topology
and parameters (delay, power supply, etc.)
 One of the main applications of oscillators
is the on-chip generation of clock
signals.
 The ring oscillator is a simple, example of
an astable circuit.
 It consists of an odd number of inverters
connected in a circular chain.
46

Timing Classification of Digital System
In digital systems, signals can be classified
depending on how they are related to a local
clock.
Signals that transition only at
predetermined periods in time can be
classified as synchronous, mesochronous,
or plesiochronous with respect to a system
clock.
A signal that can transition at arbitrary
times is considered asynchronous.
47

Synchronous Interconnect
 A synchronous signal is one that has the exact
same frequency, and a known fixed phase
offset with respect to the local clock.
 The signal is “synchronized” with the clock,
and the data can be sampled directly without
any uncertainty.
 The Figure shows where the flow of data in a
circuit proceeds in lockstep with the system
clock.
48

 The input data signal In is sampled with
register R1 to give signal Cin which is
synchronous with the system clock and then
passed along to the combinational logic block.
 After a suitable setting period, the output Cout
becomes valid and can be sampled by R2
which synchronizes the output with the clock.
 The “certainty period” of signal Cout - the
period where data is valid is synchronized
with the system clock.
• The “uncertainty period” - the period where
data is not valid.
49

50
Mesochronous interconnect
 A mesochronous signal is one that has the
same frequency but an unknown phase offset
with respect to the local clock.
 “meso” from Greek is “middle”
 In this system, it is not possible to directly
sample the output at the receiving module
because of the uncertainty in the phase offset.
 A mesochronous synchronizer can be used to
synchronize the data signal with the receiving
clock as shown below.

 Signal D1 is synchronous with respect to ClkA
 However, D1 and D2 are mesochronous with ClkB
because of the unknown phase difference
between ClkA and ClkB and the unknown
interconnect delay in the path between Block A
and Block B
 The role of the synchronizer is to adjust the
variable delay line such that the data signal D3 is
aligned properly with the system clock of Block B
 In this example, the variable delay element is
adjusted by measuring the phase difference
between the received signal and the local clock.
 After register R2 samples the incoming data
during the certainty period, then signal D4
becomes synchronous with ClkB
51

52
Plesiochronous Interconnect
 A plesiochronous signal is one that has nominally
the same, but slightly different frequency as the
local clock
 “plesio” from Greek is “near”
 The phase difference drifts in time.
 The transmitted signal can arrive at the receiving
module at a different rate than the local clock,
one needs to utilize a buffering scheme to ensure
all data is received.

 In this digital communications framework,
the originating module issues data at
some unknown rate characterized by C1,
which is plesiochronous with respect to
C2.
 The timing recovery unit is responsible
for deriving clock C3 from the data
sequence, and buffering the data in a
FIFO.
 As a result, C3 will be synchronous with
the data at the input of the FIFO and will
be mesochronous with C1.
53

Asynchronous Interconnect
 Asynchronous signals can transition at any arbitrary
time, and are not slaved to any local clock.
 Communication between modules is controlled through
a handshaking protocol to perform the proper
ordering of commands.
 It will generate a completion signal DV to indicate that
output data is valid.
 The handshaking signals then initiate a data transfer to
the next block, which latches in the new data and
begins a new computation by asserting the
initialization signal I.
54

Synchronous Design
 All systems designed today use a periodic synchronization
signal or clock.
 The generation and distribution of a clock has a
significant impact on performance and power dissipation.
 Assume the clock paths from a central distribution point to
each register are perfectly balanced, the phase of the clock
at various points in the system is going to be exactly equal.
 Figure shows the basic structure of a synchronous pipelined
datapath.
55

The clock at registers 1 and 2 have the same
clock period and transition at the exact same
time.
The following timing parameters characterize
the timing of the sequential circuit.
 The contamination (minimum) delay tc-q,cd and
maximum propagation delay of the register tc-q
 The set-up (tsu) and hold time (thold) for the
registers.
 The contamination delay tlogic,cd and maximum
delay tlogic of the combinational logic.
 tclk1 and tclk2, corresponding to the position of
the rising edge of the clock.
56

 Under ideal conditions (tclk1 = tclk2), the worst case
propagation delays determine the minimum
clock period required for this sequential circuit.
 The period must be long enough for the data to
propagate through the registers and logic and be
set-up at the destination register before the next
rising edge of the clock.
T > tc-q+ tlogic + tsu
 The hold time of the destination register must be
shorter than the minimum propagation delay
through the logic network,
thold < tc-q,cd + tlogic,cd
 The above analysis is simplistic since the clock is
never ideal and the clock signal can have spatial
and temporal variations 57

Clock Jitter
 Clock jitter - The temporal variation of the
clock period at a given point on the chip.
 The clock period can reduce or expand on a
cycle-by-cycle basis.
 Cycle-to-cycle jitter (Tjitter) refers to time
varying deviation of a single clock period
relative to an ideal reference clock.
 Jitter directly impacts the performance of a
sequential system.
58

Impact of Skew and Jitter on Performance:
 The combined impact of skew and jitter is studied
with respect to conventional edge-triggered clocking.
Consider the sequential circuit show in Figure.
 The ideal clocks are distributed to both registers (the
clock period is identical every cycle and the skew is 0).
 The static skew δ between the two clock signals
(assume that δ > 0).
59

 Assume that CLK1 has a jitter of tjitter1 and CLK2
has a jitter of tjitter2
 The worst case happen when the leading edge of
the current clock period on CLK1 happens late
(edge 3) and the leading edge of the next cycle of
CLK2 happens early (edge 10).
TCLK + δ – tjitter1 – tjitter2 ≥ tc – q + tlogic + tsu
 Jitter has a negative impact on the minimum
clock period consider the case when the leading
edge of the CLK1 cycle arrives early (edge 1) and
the leading edge the current cycle of CLK2 arrives
late (edge 6).
 The separation between edge 1 and 6 should be
smaller than the minimum delay through the
network.
δ + thold + tjitter1 + tjitter2 < t(c – q, cd) + t(logic, cd) 60

Sources of Skew and Jitter:
 A perfect clock is defined as perfectly periodic signal that is
simultaneous triggered at various memory elements on the
chip.
 However, due to a variety of process and environmental
variations, clocks are not ideal.
 consider the simplistic view of clock generation and distribution
as shown in Figure.
61

Sources:
Clock-Signal Generation (1)
Manufacturing Device Variations (2)
Interconnect Variations (3)
Environmental Variations (4 and 5)
Capacitive Coupling (6 and 7)
62

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