シミュレーション事例:擬似共振電源回路シミュレーション Quasi-Resonant Switching Power Supply using FA5541
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This document describes a quasi-resonant switching power supply simulation using the FA5541 IC, with a focus on output voltage and current characteristics. Simulation results demonstrate the power supply achieves a stable output of 19V at 5A, with a minimal ripple voltage and specific step-load response characteristics. Various operational aspects, including startup sequences and transformer behaviors, are also analyzed in detail.
シミュレーション事例:擬似共振電源回路シミュレーション Quasi-Resonant Switching Power Supply using FA5541
- 1. 擬似共振電源回路シミュレーション Quasi-Resonant Switching Power Supply using FA5541 1 2015年2月17日 マルツエレック株式会社 PSpiceシミュレーション事例
- 2. Contents 1. Quasi-Resonant Switching Power Supply 19V/5A 1.1 Output voltage 1.2 Output current 1.3 Output ripple voltage 1.4 Step-load response 2. Basic operation of switching power supply using FA5541 3. Start-up sequence simulation 4. Bridge diode peak current at start-up 5. Transformer 6. RCD Clamping network 7. Power MOSFET switching device 8. Schottky barrier diode D21 and D22 waveforms 9. Photocoupler 2
- 3. 1.Quasi-Resonant Switching Power Supply 19V/5A D1 DERA38-06 D2 DERA22-02 REF K A SR1 TA76432F D21 YG865C15R1 23 C10 0.01uF D22 YG865C15RLs {Nsp*Nsp*Lp} 1 2 L1 4.7uH 1 2 VO_19V C_T1 2200pF 0 100V/50Hz C1 220uF IC = 139 K K1 COUPLING = 0.98 K_Linear L1 = Ls L2 = Lp L3 = Lsub Lsub {Nsubp*Nsubp*Lp} 1 2 PC1 TLP281 IC1 FA5541 SSIC = 0 ZCD FB IS GND OUT VCC NC VH R12 4.7 R8 4.7k R14 100 RSL1 150m C11 4700pF C13 22pF R3 13k R4 15k C8 2200pF C9 0.01uFR5 10k R6 10k R7 2k R1 7.5k R15 200k ESR7 50m FB IS R13 100k 0 C3 33uF IC = 10.199 FB PARAMETERS: Np = 57 Ns = 10 Lp = 360uH Nsub = 8 Nsp = {Ns/Np} Nsubp = {Nsub/Np} IC=0/1 ZCD Cd 220pF 19V / 0 to 5A Lp {Lp} 1 2 Rp_T1 0.150 C2 2200pF R2 56k Rsns 0.22 R10 10 R11 100 0 DBR1 D3SB80 D3 D1NL20U_S C14 4700pF D4 D1NL20U_S M1 2SK3681-01S LESL7 12nH 1 2 C7 1000uF V1 FREQ = 50Hz VAMPL = 141.42 C12 1000pF RL 3.84 C4 3300uF ESR4 40m LESL4 15nH 1 2 C5 3300uF ESR5 40m LESL5 15nH 1 2 C6 3300uF ESR6 40m LESL6 15nH 1 2 3
- 4. 1.1 Output voltage • Simulation result confirming that the output voltage would be 19 Volt at 5-A load. The result also shows that the circuit need 60ms to reach steady state. Time 0s 20ms 40ms 60ms 80ms 100ms 120ms V(VO_19V) 0A 5A 10A 15A 20A 4
- 5. 1.2 Output current • Simulation result confirming that the output current would be 5 Amp. The result also shows that the circuit need 60ms to reach steady state. Time 0s 20ms 40ms 60ms 80ms 100ms 120ms I(RL) 0A 2.0A 4.0A 6.0A 5
- 6. • Simulation results shows the output ripple voltage at maximum current load (approximately 17.5mVP-P). Time 107.56ms 107.58ms 107.60ms 107.62ms 107.64ms 107.66ms 107.68ms 107.70ms 107.72ms 107.74ms V(VO_19V) 18.66V 18.67V 18.68V 18.69V 18.70V 1.3 Output ripple voltage 6
- 7. 1.4 Step-load response • Simulation results shows waveform of the output voltage responding to stepping current 3/5A. Time 16ms 18ms 20ms 22ms 24ms 25ms V(VO_19V) 19.0V 18.5V 19.5V SEL>> I(IL) 0A 4.0A 8.0A 7
- 8. 2.Basic operation of switching power supply using FA5541 • Power supply using FA5541 is switching using self-excited oscillation. • When IC turns the MOSFET ON ,drain current Id (primary current of T1) begins to rise from zero. • V(IS pin) is voltage-converted from the Id current. REF K A 0 0 0 OUT ZCD IS FB RZCD CZCD RS 0 M1 Cd D1T1 0 0 + Vds - ON Id + V(RS) = Id*RS - OFF 8
- 9. 2.Basic operation of switching power supply using FA5541 Time 3.580ms 3.584ms 3.588ms 3.592ms 3.596ms 3.600ms 3.604ms 3.608ms 3.612ms -I(Lp) 0A 6A V(M1:1,M1:3) 0V 0.6KV V(IC1:OUT) -1V 19V SEL>> • When Id reaches the reference level, FA5541 will turn M1 OFF Id Vds VG Id begins rising M1 turns ON Id reaches reference level M1 turns OFF VDS and winding voltage have step change 9
- 10. REF K A 0 0 0 OUT ZCD IS FB RZCD CZCD RS 0 M1 Cd D1T1 0 0 • When M1 turns OFF ,and the winding voltage of the transformers has step change and IF(D1) is provided from the transformer into secondary side. + Vds - OFF IF(D1) ON 2.Basic operation of switching power supply using FA5541 10
- 11. 2.Basic operation of switching power supply using FA5541 Time 16.0us 20.0us 24.0us 28.0us 32.0us 36.0us 40.0us 44.0us12.8us V(IC1:ZCD) 0V 4.0V V(Lsub:1) 0V -30V 30V SEL>> -I(Ls) 0A 40A • When IF(D1) gets zero, Vds drops rapidly due to resonance of transformers inductance and Cd. At the same time Vsub also drops rapidly. • When V(ZCD) < Vth(of valley detection) ,FA5541 turns M1 ON again IF(D1) Id begins rising IF(D1) is provided from the transformer into secondary side V(ZCD) < Vth, M1 turns ON IF(D1) gets zero VSUB V(ZCD) Vsub drops rapidly Vth 11
- 12. 3.Start-up sequence simulation D1 DERA38-06 D2 DERA22-02 REF K A SR1 TA76432F C4 9900uF D21 YG865C15R C10 0.01uF D22 YG865C15R 3300uFx3 Ls {Nsp*Nsp*Lp} 1 2 RL 3.84 L1 4.7uH 1 2 VO_19V C_T1 2200pF 0 100V/50Hz K K1 COUPLING = 1 K_Linear L1 = Ls L2 = Lp L3 = Lsub Lsub {Nsubp*Nsubp*Lp} 1 2 PC1 TLP281 IC1 FA5541 SSIC = 0 ZCD FB IS GND OUT VCC NC VH R12 4.7 R8 4.7k R14 100 C11 4700pF C13 22pF R3 13k R4 15k C8 2200pF C9 0.01uFR5 10k R6 10k R7 2k R1 7.5k R15 200kFB IS R13 100k 0 FB PARAMETERS: Np = 57 Ns = 10 Lp = 360uH Nsub = 8 Nsp = {Ns/Np} Nsubp = {Nsub/Np} ZCD Cd 220pF 19V / 0 to 5A Lp {Lp} 1 2C2 2200pF R2 56k V1 FREQ = 50 VAMPL = 141.42 Rsns 0.22 R10 10 R11 100 0 DBR1 D3SB80 D3 D1NL20U_S C14 4700pF D4 D1NL20U_S M1 2SK3681-01S C7 1000u C1 220uF C3 33u C12 1000pF No parasitic elements and no initial condition is set CVCC Auxiliary winding 12
- 13. 3.Start-up sequence simulation Time 0s 10ms 20ms 30ms 40ms 50ms 60ms 70ms 80ms 90ms 100ms V(IC1:OUT) 0V 4V 8V 12V 16V SEL>> V(IC1:VCC) 10.2 12.4 0V 4V 8V 12V 16V VSTOFF VCCON ,VSTRST1 VCC pin stop charging current Auxiliary supply takes over FA5541 turn onFA5541 turn off t1 t2 t3 Total start-up time VCC OUT 13
- 14. 3.Start-up sequence simulation FA5541 under voltage lockout (UVLO) characteristics (VCC pin) ON threshold voltage: VCCON = 10.2V Startup circuit shutdown: VSTOFF = 12.4V Startup circuit reset voltage: VSTRST1 = 10.2V t1,t2: VCC < VSTOFF ,startup circuit turns on ,VCC pin charges capacitor CVCC (C2). t2: VCC reaches VCCON ,FA5541 is turned on t3: after VCC reaches VSTOFF ,startup circuit turns off , VCC decreases until Auxiliary supply takes over. D2 DERA22-02 Lsub {Nsubp*Nsubp*Lp} 1 2 IC1 FA5541 SSIC = 0 ZCD FB IS GND OUT VCC NC VH R12 4.7 0 C2 33u I(VCC) I(Aux) 14
- 15. 3.Start-up sequence simulation Time 0s 100ms V(IC1:OUT) 0V 4V 8V 12V 16V V(IC1:VCC) 0V 4V 8V 12V 16V SEL>> • the simulation result shows the tradeoff between Total start-up time and Design margin, which is the difference of V(VCC) and VSTRST1 when the auxiliary winding takes over from the IC startup circuit. • 33uF-CVCC is selected for higher Design margin although total start-up time is high. CVCC=33uF CVCC=22uF Design margin (CVCC=22uF) VSTRST1 Design margin (CVCC=33uF) VCC (CVCC=22uF) Total start-up time (CVCC=33uF) 15
- 16. 4.Bridge diode peak current at start-up D1 DERA38-06 D2 DERA22-02 REF K A SR1 TA76432F C4 9900uF D21 YG865C15R C10 0.01uF D22 YG865C15R 3300uFx3 Ls {Nsp*Nsp*Lp} 1 2 RL 3.84 L1 4.7uH 1 2 VO_19V C_T1 2200pF 0 100V/50Hz K K1 COUPLING = 1 K_Linear L1 = Ls L2 = Lp L3 = Lsub V1 FREQ = 50 VAMPL = 141.42 Lsub {Nsubp*Nsubp*Lp} 1 2 PC1 TLP281 IC1 FA5541 SSIC = 0 ZCD FB IS GND OUT VCC NC VH R12 4.7 R8 4.7k R14 100 C11 4700pF C13 22pF R3 13k R4 15k C8 2200pF C9 0.01uFR5 10k R6 10k R7 2k R1 7.5k R15 200kFB IS R13 100k 0 FB PARAMETERS: Np = 57 Ns = 10 Lp = 360uH Nsub = 8 Nsp = {Ns/Np} Nsubp = {Nsub/Np} ZCD Cd 220pF 19V / 0 to 5A Lp {Lp} 1 2C3 2200pF R2 56k Rsns 0.22 R10 10 R11 100 0 DBR1 D3SB80 D3 D1NL20U_S C14 4700pF D4 D1NL20U_S M1 2SK3681-01S C7 1000u C1 220uF C2 {Cv cc} C12 1000pF PARAMETERS: CVCC = 33u No parasitic elements and no initial condition is set 16
- 17. 4.Bridge diode peak current at start-up Time 0s 40ms 80ms 120ms I(DBR1:2) -12A -8A -4A 0A 4A 8A 12A • Simulation result of the current through bridge rectifier diode DBR1 when the power supply is plug to the wall outlet. the peak current is approximately 9.8 which is less than Absolute maximum value IFSM from the datasheet. I 17
- 18. 5.Transformer D1 DERA38-06 D2 DERA22-02 REF K A SR1 TA76432F C4 9900uF D21 YG865C15R C10 0.01uF D22 YG865C15R 3300uFx3 Ls {Nsp*Nsp*Lp} 1 2 RL 3.84 L1 4.7uH 1 2 VO_19V C_T1 2200pF 0 100V/50Hz K K1 COUPLING = 1 K_Linear L1 = Ls L2 = Lp L3 = Lsub V1 FREQ = 50 VAMPL = 141.42 Lsub {Nsubp*Nsubp*Lp} 1 2 PC1 TLP281 IC1 FA5541 SSIC = 1 ZCD FB IS GND OUT VCC NC VH R12 4.7 R8 4.7k R14 100 C11 4700pF C13 22pF R3 13k R4 15k C8 2200pF C9 0.01uFR5 10k R6 10k R7 2k R1 7.5k R15 200k IS FB R13 100k 0 FB PARAMETERS: Np = 57 Ns = 10 Lp = 360uH Nsub = 8 Nsp = {Ns/Np} Nsubp = {Nsub/Np} ZCD Cd 220pF 19V / 0 to 5A Lp {Lp} 1 2C3 2200pF R2 56k Rsns 0.22 R10 10 R11 100 0 DBR1 D3SB80 D3 D1NL20U_S C14 4700pF D4 D1NL20U_S M1 2SK3681-01S C7 1000u IC = 18.7 C1 220uF IC = 139 C2 33u IC = 10.199 C12 1000pF IC = 4.2 V+ V- V+ V- V+ V- No parasitic elements 18
- 19. Time 0s 100us 200us 300us 400us 500us V(Lsub:1,Lsub:2) 0V -20V 20V SEL>> V(Ls:1,Ls:2) 0V -40V 40V V(Lp:2,Lp:1) 0V -200V 200V VP(t) -VS(t) -VSUB(t) 5.Transformer 19
- 20. 5.Transformer • Lleak = LP(1-k2) • LS/LP = N2 N : winding ratio of the transformer VS = VP*(NS/NP) VSUB = VP*(NSUB/NP) • Transformer is modeled by using SPICE primitive k ,the transformer spec is Lp=360uH and Np:Ns:Nsub=57:10:8 20
- 21. 6.Transformer leakage inductance IL 5Adc D1 DERA38-06 D2 DERA22-02 REF K A SR1 TA76432F D21 YG865C15R1 23 C10 0.01uF D22 YG865C15RLs {Nsp*Nsp*Lp} 1 2 L1 4.7uH 1 2 VO_19V C_T1 2200pF 0 100V/50Hz C1 220uF IC = 139 K K1 COUPLING = {k} K_Linear L1 = Ls L2 = Lp L3 = Lsub Lsub {Nsubp*Nsubp*Lp} 1 2 PC1 TLP281 IC1 FA5541 SSIC = 1 ZCD FB IS GND OUT VCC NC VH R12 4.7 R8 4.7k R14 100 RSL1 150m C11 4700pF C13 22pF R3 13k R4 15k C8 2200pF C9 0.01uFR5 10k R6 10k R7 2k R1 7.5k R15 200k ESR7 50m IS FB R13 100k 0 FB C3 33uF IC = 10.199 PARAMETERS: Np = 57 Ns = 10 Lp = 360uH Nsub = 8 Nsp = {Ns/Np} Nsubp = {Nsub/Np} ZCD IC=0/1 Cd 220pF 19V / 0 to 5A Lp {Lp} 1 2 Rp_T1 0.150 C2 {Cclp} R2 56k Rsns 0.22 R10 10 R11 100 0 DBR1 D3SB80 D3 D1NL20U_S C14 4700pF D4 D1NL20U_S M1 2SK3681-01S LESL7 12nH 1 2 C7 1000uF IC = 18.8 C12 1000pF IC = 4.2 C4 3300uF IC = 19.60 ESR4 40m LESL4 15nH 1 2 C5 3300uF ESR5 40m LESL5 15nH 1 2 C6 3300uF ESR6 40m LESL6 15nH 1 2 V1 FREQ = 50Hz VAMPL = 141.42 PARAMETERS: k = 0.98 Cclp = 2200pF Parametric sweep “k” 21
- 22. 6.Transformer leakage inductance • Transformer model using SPICE primitive k ,leakage inductance: Lleak = LP(1-k2) • LP=360uH ,leakage inductance is14.256uH for k=0.98 and 7.164uH for k=0.99 • Check the VDS overshoot voltage versus the transformer leakage inductance. Time 20us 40us 60us 80us 100us10us 110us V(M1:1) 0V 200V 400V 600V Time 15.0us 20.0us 25.0us 30.0us 35.0us 40.0us12.8us 44.8us V(M1:1) 0V 200V 400V 600V SEL>> Design margin (Lleak=14.256uH) M1: VDSS=600V Design margin (Lleak=7.164uH) M1: VDS(t) (Zoom) 22
- 23. 7.RCD Clamping network IL 5Adc D1 DERA38-06 D2 DERA22-02 REF K A SR1 TA76432F D21 YG865C15R1 23 C10 0.01uF D22 YG865C15RLs {Nsp*Nsp*Lp} 1 2 L1 4.7uH 1 2 VO_19V C_T1 2200pF 0 100V/50Hz C1 220uF IC = 139 K K1 COUPLING = {k} K_Linear L1 = Ls L2 = Lp L3 = Lsub Lsub {Nsubp*Nsubp*Lp} 1 2 PC1 TLP281 IC1 FA5541 SSIC = 1 ZCD FB IS GND OUT VCC NC VH R12 4.7 R8 4.7k R14 100 RSL1 150m C11 4700pF C13 22pF R3 13k R4 15k C8 2200pF C9 0.01uFR5 10k R6 10k R7 2k R1 7.5k R15 200k ESR7 50m IS FB R13 100k 0 FB C3 33uF IC = 10.199 PARAMETERS: Np = 57 Ns = 10 Lp = 360uH Nsub = 8 Nsp = {Ns/Np} Nsubp = {Nsub/Np} ZCD IC=0/1 Cd 220pF 19V / 0 to 5A Lp {Lp} 1 2 Rp_T1 0.150 C2 {Cclp} R2 56k Rsns 0.22 R10 10 R11 100 0 DBR1 D3SB80 D3 D1NL20U_S C14 4700pF D4 D1NL20U_S M1 2SK3681-01S LESL7 12nH 1 2 C7 1000uF IC = 18.8 C12 1000pF IC = 4.2 C4 3300uF IC = 19.60 ESR4 40m LESL4 15nH 1 2 C5 3300uF ESR5 40m LESL5 15nH 1 2 C6 3300uF ESR6 40m LESL6 15nH 1 2 V1 FREQ = 50Hz VAMPL = 141.42 PARAMETERS: k = 0.98 Cclp = 2200pF Parametric sweep “Cclp” 23
- 24. 7.RCD Clamping network Time 0s 20us 40us 60us 80us 100us V(M1:1) 0V 200V 400V 600V Time 20.0us 25.0us 30.0us 35.0us 40.0us 45.0us15.5us V(M1:1) 0V 200V 400V 600V SEL>> • Compare VDS overshoot of the circuit with CCLP(C2) = 220pF and 2200pF ,larger CCLP value get better design margin for MOSFET VDS • CCLP=2200uF is selected for the better M1: VDS design margin. M1: VDS(t) Design margin (CCLP=C2=2200pF) M1: VDSS=600V Design margin (CCLP=C2=220pF) M1: VDS(t) (Zoom) 24
- 25. 8.Power MOSFET switching device D1 DERA38-06 D2 DERA22-02 REF K A SR1 TA76432F D21 YG865C15R1 23 C10 0.01uF D22 YG865C15RLs {Nsp*Nsp*Lp} 1 2 L1 4.7uH 1 2 VO_19V C_T1 2200pF 0 100V/50Hz C1 220uF IC = 139 K K1 COUPLING = 0.98 K_Linear L1 = Ls L2 = Lp L3 = Lsub Lsub {Nsubp*Nsubp*Lp} 1 2 PC1 TLP281 IC1 FA5541 SSIC = 1 ZCD FB IS GND OUT VCC NC VH R12 4.7 R8 4.7k R14 100 RSL1 150m C11 4700pF C13 22pF R3 13k R4 15k C8 2200pF C9 0.01uFR5 10k R6 10k R7 2k R1 7.5k R15 200k ESR7 50m IS FB R13 100k 0 C3 33uF IC = 10.199 FB PARAMETERS: Np = 57 Ns = 10 Lp = 360uH Nsub = 8 Nsp = {Ns/Np} Nsubp = {Nsub/Np} IC=0/1 ZCD Cd 220pF 19V / 0 to 5A Lp {Lp} 1 2 Rp_T1 0.150 C2 2200pF R2 56k Rsns 0.22 R10 10 R11 100 0 DBR1 D3SB80 D3 D1NL20U_S C14 4700pF D4 D1NL20U_S M1 2SK3681-01S LESL7 12nH 1 2 C7 1000uF IC = 18.8 C12 1000pF IC = 4.2 IL 5Adc C4 3300uF IC = 19.61 ESR4 40m LESL4 15nH 1 2 C5 3300uF ESR5 40m LESL5 15nH 1 2 C6 3300uF ESR6 40m LESL6 15nH 1 2 V1 FREQ = 50Hz VAMPL = 141.42 25
- 26. 8.Power MOSFET switching device Time 0s 20ms 40ms 60ms 80ms 100ms 120ms 1 V(M1:1) 2 I(M1:1) 0V 250V 500V 1 0A 25A -15A 2 >> Time 119.90ms 119.92ms 119.94ms 119.96ms 119.98ms 120.00ms 1 V(M1:1) 2 I(M1:1) -200V 0V 200V 400V 600V 1 -2.0A 0A 2.0A 4.0A 6.0A 2 SEL>>SEL>> • Simulation results shows the peak value of M1: VDS and ID . 10usec. / Div. VDS(t) ID(t) VDS(t) ID(t) 20msec. / Div. Peak value Peak value 26
- 27. 8.Power MOSFET switching device Time 19.57ms 19.58ms 19.59ms 19.60ms 19.61ms 19.62ms 19.63ms 19.64ms 19.65ms 19.66ms 1 V(M1:1) 2 I(M1:1) 3 V(M1:2) -600V -400V -200V 0V 200V 400V 600V 1 -6.0A -2.0A 0A 2.0A 4.0A 6.0A 2 SEL>> 0V 50V 3 SEL>> 1 W(M1) 2 AVG(W(M1)) -0.5KW 0W 0.5KW 1.0KW 1.5KW 1 0W 2.5W 5.0W 7.5W 10.0W 2 >> • Simulation results shows the peak value of MOSFET VDS and ID . Calculated switching power loss and average power loss are also shown 10usec. / Div. M1 Power Loss M1 Power Lossavg VDS(t) ID(t) Peak value VGS(t) 27
- 28. 9.Schottky barrier diode D21 and D22 waveforms Time 0s 20ms 40ms 60ms 80ms 100ms 120ms 1 -I(Ls) 2 V(D22:2,D22:3) 20A 40A -5A 1 SEL>> 0V 40V 80V 2 SEL>> Time 119.92ms 119.93ms 119.94ms 119.95ms 119.96ms 119.97ms 119.98ms 119.99ms 1 -I(Ls) 2 V(D22:2,D22:3) 50A -10A 1 >> 0V 50V 2 • Simulation results shows the peak value of SBD: VKA and IF . 10usec. / Div. IF(t) VKA(t) IF(t) VKA(t) 20msec. / Div. Peak value Peak valuePeak value 28
- 29. 9.Schottky barrier diode D21 and D22 waveforms Time 19.57ms 19.58ms 19.59ms 19.60ms 19.61ms 19.62ms 19.63ms 19.64ms 19.65ms 19.66ms -I(LS) V(D22:2,D22:3) -50 -25 0 25 50 SEL>> 1 W(D21)+ W(D22) 2 AVG(W(D21)+ W(D22)) -40W 0W 40W 1 -5.0W 0W 5.0W 2 >> • Simulation results shows the peak value of SBD VKA and IF . Calculated power loss and average power loss are also shown 10usec. / Div. SBD Power Loss SBD Power Lossavg VKA(t)IF(t) Peak valuePeak value 29
- 30. 10.Photocoupler V I V- V+ D1 DERA38-06 D2 DERA22-02 REF K A SR1 TA76432F D21 YG865C15R1 23 C10 0.01uF D22 YG865C15RLs {Nsp*Nsp*Lp} 1 2 L1 4.7uH 1 2 VO_19V C_T1 2200pF 0 100V/50Hz C1 220uF IC = 139 K K1 COUPLING = 1 K_Linear L1 = Ls L2 = Lp L3 = Lsub Lsub {Nsubp*Nsubp*Lp} 1 2 PC1 TLP281 IC1 FA5541 SSIC = 1 ZCD FB IS GND OUT VCC NC VH R12 4.7 R8 4.7k R14 100 RSL1 150m C11 4700pF C13 22pF R3 13k R4 15k C8 2200pF C9 0.01uFR5 10k R6 10k R7 2k R1 7.5k R15 200k ESR7 50m IS FB R13 100k 0 C3 33uF IC = 10.199 FB PARAMETERS: Np = 57 Ns = 10 Lp = 360uH Nsub = 8 Nsp = {Ns/Np} Nsubp = {Nsub/Np} IC=0/1 ZCD Cd 220pF 19V / 0 to 5A Lp {Lp} 1 2 Rp_T1 0.150 C2 2200pF R2 56k Rsns 0.22 R10 10 R11 100 0 DBR1 D3SB80 D3 D1NL20U_S C14 4700pF D4 D1NL20U_S M1 2SK3681-01S C7 1000uF IC = 18.9 C12 1000pF IC = 4.2 IL 5Adc C4 9900uF IC = 19.665 ESR4 13.3m 3300uFx3 V1 FREQ = 50Hz VAMPL = 141.42 No parasitic elements: Lleak and ESL ,to aid simulation convergence 30
- 31. 10.Photocoupler Time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms V(VO_19V) 18V 19V 20V V(PC1:A,PC1:K) 0V 1.0V SEL>> Time 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms 1 I(PC1:C) 2 V(FB) -12uA 380uA 1 >> 0V 2.5V 5.0V 2 • When power supply output reaches spec voltage (19V) ,a shunt regulator draws current through resistor (R6) and VAK of photocoupler increases. • When VAK turns on photocoupler, collector current Ic increases. This causes FB pin voltage to decreases before power supply output voltage go to the stable state. 2msec. / Div. IC (photocoupler) V(FB pin) VAK (photocoupler) 2msec. / Div. VO_19V(t) VAK turns on the photocoupler VO stable at 19V 31