Week 3 intro to computer organization and assembly language
- 1. Lecture 3 COAL Dr. Adeel Asghar
- 2. Narrated Hasan: Knowledge is of two types. Firstly, knowledge perceived by the heart, and that is useful knowledge; secondly, the knowledge at on the tip of one’s tongue, and that is an argument from Allah, the Exalted and Glorious, against the children of Adam. Transmitted by Darimi. Al-Tirmidhi – Hadith 270
- 3. Connecting • All the units must be connected • Different type of connection for different type of unit • Memory • Input/Output • CPU
- 4. Memory Connection • Receives and sends data • Receives addresses (of locations) • Receives control signals • Read • Write
- 5. Input/Output Connection(1) • Similar to memory from Proccesser’s viewpoint • Output • Receive data from computer • Send data to peripheral • Input • Receive data from peripheral • Send data to computer
- 6. Input/Output Connection(2) • Receive control signals from computer • Send control signals to peripherals • e.g. spin disk • Receive addresses from computer • e.g. port number to identify peripheral • Send interrupt signals
- 7. CPU Connection • Reads instruction and data • Writes out data (after processing) • Sends control signals to other units • Receives (& acts on) interrupts
- 9. Buses • There are a number of possible interconnection systems • e.g. Unibus (DEC-PDP) • e.g. Control/Address/Data bus
- 10. What is a Bus? • A shared communication pathway connecting two or more devices • Usually broadcast • Often grouped • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels • Power lines may not be shown
- 12. Data Bus • Carries data • Remember that there is no difference between “data” and “instruction” at this level • Width is a key determinant of performance • 8, 16, 32, 64 bit
- 13. Address bus • Identify the source or destination of data • e.g. CPU needs to read an instruction (data) from a given location in memory • Bus width determines maximum memory capacity of system • e.g. 8080 has 16 bit address bus giving 64k address space
- 14. Control Bus • Control and timing information • Memory read/write signal • I/O read/write signal • Bus request/grant • Interrupt request • Clock signals
- 16. Physical Realization of Bus Architecture
- 17. Single Bus Problems • Lots of devices on one bus leads to: • Propagation delays • Long data paths mean that co-ordination of bus use can adversely affect performance • If aggregate data transfer approaches bus capacity • Most systems use multiple buses to overcome these problems
- 19. Bus Types • Dedicated • Separate data & address lines • Multiplexed • Shared lines • Address valid or data valid control line • Advantage - fewer lines • Disadvantages • More complex control • Reduction performance
- 20. Bus Arbitration • More than one module controlling the bus • e.g. CPU and DMA controller • Only one module may control bus at one time • Arbitration may be centralised or distributed
- 21. Centralised or Distributed Arbitration • Centralised • Single hardware device controlling bus access • Bus Controller • Arbiter • May be part of CPU or separate • Distributed • Each module may claim the bus • Control logic on all modules
- 22. Error Correction • Hard Failure • Permanent defect • Soft Error • Random, non-destructive • No permanent damage to memory • Detected using Hamming error correcting code
- 23. Error Correcting Code Function
- 24. Hamming Error correction code
- 25. Example (single bit error) at M=8 • Determine code length • Bit by bit comparison is done using XOR and the result is called syndrome, indicating the error bit • Length of syndrome bits = length of K bits and range between 0-2^K -1 • Calculate check bits using • The code just described is known as a single-error- correcting (SEC)
- 27. PCI Bus • Peripheral Component Interconnection