Usha Mehta

vlsi cmos sta static timing analysis testing and verification of vlsi design set-up and hold time violation timing verification of vlsi design digital vlsi design testing atpg verification fault simulation vlsi design digital design prom bist ic fabrication lut design for testing fpga dft test pattern generation hold time violation set-up time violation timing anylysis stiatic timing analysis formal verification emulation timing violation in vlsi circuits maximum clock frequency for digital vlsi design false path clock domain crossing multiple clocks timing verification latch up dynamic logic mos static and dynamic logic speed binning propagation_delay cell_delay set up and hold time violation technology trends digital vlsi introduction combinational circuit failure mode analysis diagnosis fault modeling stuck-at faults transistor-faults fault propagation scoap testability validation built-in-self-test functional verification bug code coverage eprom eeprom fuse antifuse flash programmable devices cpld spld pal pla ga field programmable gate arrays fpga architecture lookup table reconfigurable logic programmable logic programmable interconnect programmable input output simulation synthesis pnr place and route behavioural coding rtl register transfer level fpga design flow technology mapping functiional verification sequential design d flipflop transistor invention of transistor evolution of cmos logic first ic integrated circuits combinational design combinational circuits pass gate pass transistor logic euler's theorm stick diagram for cmos layout design for cmos integrated circuit fabrication fab layout n-well isolation methods ic asic design flow ic design cmos ic application specific integrate programmable switches switch