10 static timing_analysis_1_concept_of_timing_analysis
0 likes593 views
This document discusses static timing analysis (STA), which is used to verify that a digital circuit design meets timing requirements without simulating the circuit. It begins by explaining the objectives of timing analysis and the differences between static and dynamic timing analysis. Static timing analysis is described as examining all possible signal paths to calculate worst-case arrival times and check for timing violations, while dynamic analysis uses test vectors but is slower. The document then covers gate and net delay models used in STA, limitations of simple fixed delay models, and lumped and distributed RC net delay models.
![1/25/2022
Static
Timing
Analysis
Limitation of Fixed Delay Model
• Process Variation
• Delay in its real sense, is a probability distribution function.
• Simplest way to express is in [min, max]
22](https://image.slidesharecdn.com/10statictiminganalysis1conceptoftiminganalysis-220125073116/85/10-static-timing_analysis_1_concept_of_timing_analysis-22-320.jpg)
10 static timing_analysis_1_concept_of_timing_analysis
- 1. Concept of Timing Analysis Prof. Usha Mehta Professor, PG-VLSI Design, EC, Institute of Technology, Nirma University, Ahmedabad usha.mehta@nirmauni.ac.in usha.mehta@ieee.org Does the design meet a given timing requirement?!! How fast can I run the design?!!!
- 2. 1/25/2022 Static Timing Analysis Acknowledgement 2 This presentation has been summarized from various books, papers, websites and presentations and so on …. all over the world. I couldn’t remember where these large pull of hints and work come from. However, I’d like to thank all professors and scientists who create such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. I am thankful to them to make my teaching process more effective.
- 3. 1/25/2022 Static Timing Analysis Agenda • ASIC Design Flow : with timing considerations • Objective of Timing Analysis • Types of Timing Analysis • Static Timing Analysis : Introduction • STA in ASIC Flow • Gate Delay Models • Net Delay Models 3
- 4. 1/25/2022 Static Timing Analysis • What you know • Logic synthesis • How to simulate the design to verify what it does • What you don’t know • Verify the timing behaviour of given synthesized design • Timing Analysis • We have gate level netlist • Some timing information of gates and wires are given • We need to tell • When signal arrives in various points in the network • Shortest and longest delays through network • Does netlist meets timing requirements? 4
- 5. 1/25/2022 Static Timing Analysis Objective of Timing Analysis Timing verification • Verifies whether a design meets a given timing constraint • Verifies that the design work properly for all possible combination “EVERY TIME” Timing optimization • Needs to identify critical portion of a design for further optimization • Critical path identification • Like component selection • A slow memory can degrade processor performance In both applications, the more accurate, the better 5
- 6. 1/25/2022 Static Timing Analysis Types of Timing Analysis • Dynamic Timing Analysis • Verifies the functionality of design by applying input vectors and checking the correctness and timing of output vectors • Static Timing Analysis • Checks static delay requirements without applying any vectors • It does not check functionality 6
- 7. 1/25/2022 Static Timing Analysis Dynamic Timing Analysis • Requires too many patterns, exponential in the number of design inputs • Even worse, if we consider the sequence need to initialize the latches • It does not find all the errors, because it is pattern dependent. It can only check the timing paths sensitized by the input pattern. If the patterns do not cause an error to occur, the error is not detected. • Can be very accurate (spice-level) • Analysis quality depends on stimulus vectors • Non-exhaustive, slow 7
- 8. 1/25/2022 Static Timing Analysis Then What to do? • Separate function from timing • Determine when transition occurred without worrying about how? • Instead of considering infinite long simulation sequence, fold all possible transitions back into a single clock cycles • Assume that signal gets stable at latest possible time and unstable at earliest possible time. • If the design works at these extremes, it can be guaranteed that it will always work safely • Do it static means do not simulate. 8
- 9. 1/25/2022 Static Timing Analysis Static Timing Analysis • It is a method of validating the timing performance of a design by checking all possible paths from timing violations under worst case conditions • It considers worst logical delay through each logic element but not the logical operation of the circuit. • Input independent method So no vector generation is required. • It does not check the functionality 9
- 10. 1/25/2022 Static Timing Analysis Static Time Analysis What it typically does: • Calculate latest and earliest possible switching times for each node in the design • Determine the arrival time of signals for the worst case (latest or earliest) of all possible paths leading to a given node in the design • Compare calculated signal arrival times with expected (required) arrival times at storage elements, other clock meets data points (such as dynamic circuits) and primary outputs in the design. 10
- 11. 1/25/2022 Static Timing Analysis STA…. • Much faster than timing driven gate level simulation (dynamic). • There are huge number of logic paths inside a chip of complex design and STA calculates delay for all possible paths whether they are real or potential false path. So it is exhaustive in nature. • False paths need to be handled separately. • It is not suitable for all design styles. Proven efficient for synchronous design only but most of the designs are synchronous so it is there in mainstream. Asynchronous designs need separate attention. • It is pessimistic and hence less accurate • Conservative analysis. Calculates upper bound on frequency but guarantees that the design will function at least as fast as predicted. 11
- 12. 1/25/2022 Static Timing Analysis Static Timing Analysis • Consider all paths • Does not checks circuit functionality • Reports False Paths • Pessimism by considering false paths which are never exercised • Not so accurate • Fast Dynamic Timing Analysis • Depends on input stimulus vectors • Checks circuit functionality • Does not report timing on false paths • By large number of testing vectors • Accurate • Slow 12
- 13. 1/25/2022 Static Timing Analysis • Multiple clocks • False paths: Proper circuit functionality is not checked • Latches • Multicycle paths Works best with synchronous (not asynchronous) logic Complex to learn Must define timing requirements / exceptions Difficulty in handling: Limitations of STA 13
- 14. 1/25/2022 Static Timing Analysis Delay/Time Calculation for a design • The total delay of a path is the sum of all • Gate/Cell Delays in the path • Net /Path Delays in the path 14
- 15. 1/25/2022 Static Timing Analysis Gate/Cell Delays • Timing Delay between input pin and output pin of a logic gate/cell in a path • The cell delay information is contained in the library of the cell e.g. .lef file • In ASICs, the delay of a cell is affected by: • The input transition time (or slew rate) • The total load “seen” by the output transistors • Net capacitance and “downstream” pin capacitances • These will affect how quickly the input and output transistors can “switch” • Inherent transistor delays and “internal” net delays 15
- 16. 1/25/2022 Static Timing Analysis Definition of Delays for Cell 16
- 17. 1/25/2022 Static Timing Analysis Gate Delay Models Unit Delay Model • Simplest • Each gate with unit delay • Longest path delay = 2 Arbitrary but Fixed Delay Model • Simple • Each gate with some constant delay which does not depend on circuit or netlist 17
- 18. 1/25/2022 Static Timing Analysis Limitations of Fixed Delay Model • Fanouts • Loading effect on transistors inside gates • Gates with more fanouts are slower than gates with less fanouts 18
- 19. 1/25/2022 Static Timing Analysis Limitation of Fixed Delay Model Input Waveform • Slop of the input waveform also affects delay (RC affects) • Rising signal vs Falling signal also affects 19
- 20. 1/25/2022 Static Timing Analysis Limitations of Fixed Delay Model • Location of pins • Delay is not actually through a gate • but it is actually from individual input pin to output • 20
- 21. 1/25/2022 Static Timing Analysis Limitation of Fixed Delay Model • Rising and Falling Waveforms • pMOS has larger delay compared to nMOS. • Rising and falling delay for output may be different • More complicated for Non- Monotonic functions 21
- 22. 1/25/2022 Static Timing Analysis Limitation of Fixed Delay Model • Process Variation • Delay in its real sense, is a probability distribution function. • Simplest way to express is in [min, max] 22
- 23. 1/25/2022 Static Timing Analysis Net/ Wire Delays • Net delay is the difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net. Wire delay = function of (Rnet, Cnet+Cpin) • Total net delays are affected by: • Characteristics of driver cell and receiver cell • net material, length and cross sectional are • net fanout • Number of vias traversed by the net • Proximity to other nets (crosstalk) • The effects of Interconnect Parasitic • Interconnect parasites cause an increase in propagation delay (i.e. it slows down working speed) 23
- 24. 1/25/2022 Static Timing Analysis Lumped Capacitor Model • As long as the resistive component of the wire is small, and switching frequencies are in the low to medium range, it is meaningful to consider only the capacitive component of the wire, and to lump the distributed capacitance into a single capacitance. 24
- 25. 1/25/2022 Static Timing Analysis Lumped RC Model • If wire length is more than a few millimeters, the lumped capacitance model is inadequate and a resistive capacitive model has to be adopted. • In lumped RC model the total resistance of each wire segment is lumped into one single R, combines the global capacitive into single capacitor C. • Analysis of network with larger number of R and C becomes complex as network contains many time constants (zeroes and poles). 25
- 26. 1/25/2022 Static Timing Analysis Distributed RC Model • Lumped RC model is always pessimistic and distributed RC model provides better accuracy over lumped RC model. But distributed RC model is complex and no closed form solution exists. Hence distributed RC line model is not suitable for Computer Aided Design Tools. The behavior of the distributed RC line can be approximated by a lumped RC ladder network such as Elmore Delay model hence these are extensively used in EDA tools. 26
- 27. 1/25/2022 Static Timing Analysis Elmore Delay Model • Resistance Oriented Formula 27 , T R C delay i downstream i Tdelay,4=R1(C1+C2+C3+C4+C5)+R2(C2+C4+C5)+R4C4
- 28. Thanks! 28