5 verification methods
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This document discusses various methods for verifying VLSI chip designs, including functional verification through simulation, formal verification techniques like equivalence checking and model checking, and timing analysis. It describes functional verification approaches like black-box, white-box, and grey-box testing. It also notes limitations of functional verification and outlines how formal verification can be used as an alternative to verify that small non-functional design modifications do not change functionality. Specific formal verification methods like equivalence checking, model checking, and binary decision diagrams are introduced.
5 verification methods
- 2. Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 Dr Usha Mehta 25-01-2022
- 3. Verification Methods • Functional Verification • Simulation • Emulation • Formal Verification • Equivalence Checking • Model Checking • Semiformal Verification • Assertion Based Methods 3 Dr Usha Mehta 25-01-2022
- 4. Verification Techniques • Simulation (functional and timing) • Behavioral • RTL • Gate-level (pre-layout and post-layout) • Switch-level • Transistor-level • Model Based Formal Verification (functional) • Binary Decision Diagrams • Equivalence Checking • Model Checking • Static and Dynamic Timing Analysis (timing) 4 Dr Usha Mehta 25-01-2022
- 6. Functional Verification Approaches: Black Box Approach • Can not look into the design • Functional verification to be performed without any internal implementation knowledge • Through available interfaces only, no internal state access • Examples: • Check a multiplier by supplying random numbers to multiply • Check a braking system by hitting the brakes at different speeds • Check a traffic light controller by simulating pre-recorded traffic patterns 6 Dr Usha Mehta 25-01-2022
- 7. Black Box….. • Advantage • Independent of implementation • Verification process parallel with design process • Less efforts and time consumption • Disadvantage • Lack of visibility and controllability • Difficult to set interesting state/combinations • Difficult to locate the source of problem • Difficulty rises when there is a long delay between occurrence of a problem and its symptom is visible 7 Dr Usha Mehta 25-01-2022
- 8. Functional Verification Approaches • White Box • Intimate knowledge and controls of internals of a design • This approach can ensure that implementation specific features behave properly • Pure white box approach is being used at system level where modules are treated like black boxes but system itself is treated like white box. • Grey Box • Black box test cases written with full knowledge of internal details. • Mostly written to increase code coverage 8 Dr Usha Mehta 25-01-2022
- 10. Simulation Based Functional Verification Flow 10 Dr Usha Mehta 25-01-2022
- 11. Limitations of Functional Verification • Large numbers of simulation vectors are needed to provide confidence that the design meets the required specifications. • Logic simulators must process more events for each stimulus vector because of increased design size and complexity. • More vectors and larger design sizes cause increased memory swapping, slowing down performance 11 Dr Usha Mehta 25-01-2022
- 13. Alternative to Functional Verification • Once the Behavioural design is verified, there are many requirements for small non-functional modifications in RTL. • Ideally, after each such modification, there must be a round of verification which is not practical. • So alternative to this is Formal Verification • Mathematically proving that the modification has not changed functionality 13 Dr Usha Mehta 25-01-2022
- 14. Examples of Non-Functional Changes in RTL of Design • Adding clock gating circuitry for power reduction • Restructuring critical paths • Reorganizing logic for area reduction • Adding test logic (scan circuitry) to a design • Reordering a scan chain in a design • Inserting a clock tree into a design • Adding I/O pads to the netlist • Performing design layout • Performing flattening and cell sizing 14 Dr Usha Mehta 25-01-2022
- 15. Combinational Comparison • One very fundamental question is whether two given combinational circuits are equivalent for all given input combinations • Example: • The circuit is optimized to reduce the gates • The task is to prove that after optimization, the circuit has not changed functionally. • This can be verified by comparing the “Truth Table” : Tautology • Though this can be automated, in practical, working with truth tables are tedious and inefficient 15 Dr Usha Mehta 25-01-2022
- 16. Formal Verification Methods • Technique to prove or disprove the functional equivalence of two designs. • The techniques used are static and do not require simulation vectors. • You only need to provide a functionally correct, or “golden” design (called the reference design),and a modified version of the design (called the implementation). • By comparing the implementation against the reference design, you can determine whether the implementation is functionally equivalent to the reference design 16 Dr Usha Mehta 25-01-2022
- 17. Formal Verification Methods • Equivalence Checking • Model Checking • Binary Decision Diagram • Theorem Proving • Satisfiability Problems (SAT Theory) 17 Dr Usha Mehta 25-01-2022
- 18. Timing Analysis • Is output correct? • Is output correct at required time? • Timing analysis – a separate chapter 18 Dr Usha Mehta 25-01-2022
- 20. Thanks……