LogicMindtech Nologies

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LogicMindtech Nologies

Documentos

A generalized algorithm and reconfigurable

A high performance fir filter architecture for

A low power hybrid ro puf with improved thermal stability for lightweight applications

A novel area efficient vlsi architecture

Aging aware reliable multiplier design with

An area efficient relaxed half-stochastic decoding architecture for nonbinary ldpc codes

An optimized modified booth recoder for efficient design of the add multiply operator

Area–delay–power efficient carry select adder

Area efficient fixed-width squarer with dynamic error-compensation circuit

Based on vertical horizontal binary common

Critical path analysis and low-complexity implementation of the lms adaptive algorithm

Data encoding techniques for reducing energyb consumption in network on-chip

Design and analysis of approximate

Ecursive approach to the design of a parallel self timed adder

Efficient coding schemes for fault tolerant

Energy and area efficient three input xor xno rs with systematic cell design methodology

Energy and area efficient three input xor xno rs with systematic cell design methodology

Fast sign detection algorithm for the rns moduli set {2n+1 − 1, 2n − 1, 2n}

Fault tolerant parallel ff ts using error correction codes and parseval checks

Fully reused vlsi architecture of fm0 manchester encoding using sols technique for dsrc applications

Graph based transistor network generation

High speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels

High throughput finite field multipliers using redundant basis for fpga and asic implementations

High throughput multistandard transform core supporting mpeg h 264 vc 1 using common sharing distributed arithmetic

Improved 8 point approximate dct for image and video compression requiring only 14 additions

Input vector monitoring concurrent bist architecture using sram cells

Improved 8 point approximate dct for image and video compression requiring only 14 additions

Input based dynamic reconfiguration of

Low cost high-performance vlsi architecture for montgomery modular multiplication

Low power and area-efficient shift register using pulsed latches