Connected by Arteris | LinkedIn Edition #5
Welcome to the fifth edition of our monthly newsletter 👋
The world of chip design is evolving rapidly, with increasing complexity driving innovation across the board. This issue dives into the cutting-edge technologies shaping the semiconductor industry, from simplifying IP reuse with our new Magillem Packaging product to accelerating multi-die SoC designs. Explore how Arteris is driving breakthroughs in NoC design, chiplet integration, and AI-driven solutions. Read on to learn more.
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Product Spotlight
Arteris to Provide FlexGen Smart NoC IP in Next-Generation AMD AI Chiplet Designs
Arteris’ smart NoC IP will be utilized by AMD in semiconductor designs to enable improved product performance and efficiency. FlexGen will provide high-performance data transport in AMD chiplets powering AI across the company’s broad portfolio which spans from data centers to edge and end devices.
FlexGen NoC IP will work hand in hand with AMD’s Infinity Fabric to accelerate the performance and scalability required by today’s most demanding and diverse applications. FlexGen can be utilized as an independent interconnect solution or in combination with proprietary interconnect technology to accelerate design iterations and time to market schedules.
Accelerating IP Reuse with the New Version of IP-XACT
The days of monolithic chips built entirely in-house are long gone. Today’s complex SoCs can integrate up to 1,000 IP blocks from multiple vendors — and making them work together seamlessly is no easy task. In this tech talk with Ed Sperling of Semiconductor Engineering, Insaf Meliane, Director of Product Management and Marketing at Arteris, explains how the new version of IP-XACT helps automate and simplify this process.
Industry Expertise
DAC 2025: Arteris CMO Michal Siwinski Debunks Chiplet Misunderstandings
In this video, EE Times’ Nitin Dahad spoke to Michal Siwinski, CMO of Arteris, on the company’s announcements at DAC 2025 and some of the misunderstandings about chiplets. They explored the need for IP reuse and what is possible with chiplets today and how, as an industry, we can’t let the perfect be the enemy of the good.
Arteris Expands Their Multi-Die Support
Earlier this summer, we announced expanded support for high-performance multi-die SoCs, including cache coherent and non-coherent NoC IP and advanced automation via Magillem Connectivity for system partitioning and Magillem Registers for memory map integration between chiplets. As the semiconductor industry embraces chiplets to overcome reticle limits and speed up complex designs, this SemiWiki article tells the story of how we work on delivering the silicon-proven IP and tools needed to build performant, power-efficient systems — faster.
Learn more in the article here →
Upcoming Events
Meet the Arteris team in person at an upcoming event. Learn more about future plans here.
Aug 20, 2025 – DVCon Japan – Tokyo, Japan
📌 Join the tutorial session by Josh Rensch, Director of CAE at Arteris: 'Will it Blend?' – Verifying the Hardware / Software Interface of Complex SoCs at 4:50-5:40pm.
Aug 24-26, 2025 – Hot Chips – Palo Alto, CA, USA
Sept 9, 2025 – DVCon Taiwan – Taiwan | 📌 Booth 4
Sept 9-11, 2025 – AI Infra Summit – Santa Clara, CA, USA
📌 Meet the team at booth 517 and join the panel with Laurent Moll, COO at Arteris on September 9, 2:35-3:15pm: Designing Power Efficient Chips – from the Edge to the Data Center.
Sept 16, 2025 – D&R IP SoC Korea – Seoul, Korea
📌 Join the session by John Min, VP of Customer Success at Arteris: Updated Methodology to Generate Optimal NoCs in 2025.
➡️ Request a meeting with the team here.
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Director of Application Engineering
5dI guess I am going to Japan this month! I hope to see people there.