93 appendix pic18(l)f2 x4xk22 (1)

PIC18LF46K22
Data Sheet
28/40/44-Pin, Low-Power,
High-Performance Microcontrollers
With XLPTechnology
© 2010-2012 Microchip Technology Inc. DS41412F

PIC18LF46K22
28/40/44-Pin, Low-Power, High-Performance
Microcontrollers with XLP Technology
High-Performance RISC CPU:
C Compiler Optimized Architecture:
• Optional extended instruction set
designed to optimize re-entrant code
• Up to 1024 Bytes Data EEPROM
• Up to 64 Kbytes Linear Program
Memory Addressing
• Up to 3896 Bytes Linear Data Memory
Address-ing
• Up to 16 MIPS Operation
• 16-bit Wide Instructions, 8-bit Wide
Data Path
• Priority Levels for Interrupts
• 31-Level, Software Accessible
Hardware Stack
• 8 x 8 Single-Cycle Hardware Multiplier
Flexible Oscillator Structure:
• Precision 16 MHz Internal Oscillator
Block:
- Factory calibrated to ± 1%
- Selectable frequencies, 31 kHz to 16
MHz
- 64 MHz performance available
using PLL – no external
components required
• Four Crystal modes up to 64 MHz
• Two External Clock modes up to 64
MHz
• 4X Phase Lock Loop (PLL)
• Secondary Oscillator using Timer1 @
32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if
peripheral clock stops
- Two-Speed Oscillator Start-up
Analog Features:
• Analog-to-Digital Converter (ADC)
module:10-bit resolution, up to 30
external channels
- Auto-acquisition capability
- Conversion available during Sleep
- Fixed Voltage Reference (FVR)
channel
- Independent input multiplexing
• Analog Comparator module:
- Two rail-to-rail analog comparators
- Independent input multiplexing
• Digital-to-Analog Converter (DAC)
module:
- Fixed Voltage Reference (FVR)
with 1.024V, 2.048V and 4.096V
output levels
- 5-bit rail-to-rail resistive DAC
with positive and negative
reference selection
• Charge Time Measurement Unit
(CTMU) module:
- Supports capacitive touch sensing
for touch screens and capacitive
switches

Extreme Low-Power
Management
PIC18(L)F2X/4XK22 with XLP:
• Sleep mode: 20 nA, typical
• Watchdog Timer: 300 nA, typical
• Timer1 Oscillator: 800 nA @ 32 kHz
• Peripheral Module Disable
Special Microcontroller Features:
• 2.3V to 5.5V Operation –
PIC18FXXK22 devices
• 1.8V to 3.6V Operation –
PIC18LFXXK22 devices
• Self-Programmable under Software
Control
• High/Low-Voltage Detection (HLVD)
module:
- Programmable 16-Level
- Interrupt on High/Low-Voltage
Detection
• Programmable Brown-out Reset (BOR):
- With software enable option
- Configurable shutdown in Sleep
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to
131s
• In-Circuit Serial Programming™
(ICSP™):
- Single-Supply 3V
• In-Circuit Debug (ICD)
Peripheral Highlights:
• Up to 35 I/O Pins plus 1 Input-Only Pin:
- High-Current Sink/Source 25 mA/25
mA
- Three programmable external
interrupts
- Four programmable interrupt-on-
change
- Nine programmable weak pull-ups
- Programmable slew rate
• SR Latch:
- Multiple Set/Reset input options
• Two Capture/Compare/PWM (CCP)
modules
• Three Enhanced CCP (ECCP) modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
- PWM steering
• Two Master Synchronous Serial Port
(MSSP) modules:
- 3-wire SPI (supports all 4 modes)
- I2
C™ Master and Slave modes with
address mask
© 2010-2012 Microchip Technology Inc. DS41412F-page 3

PIC18LF46K22
• Two Enhanced Universal Synchronous
Asynchronous Receiver Transmitter
(EUSART) modules:
- Supports RS-485, RS-232 and LIN
- RS-232 operation using internal oscillator
- Auto-Wake-up on Break
- Auto-Baud Detect
Program
Data Memory
(2)
MSSP
Memory
ECCP(Full-Bridge)
ECCP(Half-Bridge)
Comparator
16-bitTimer
10-bitA/DChannels
EUSART
BOR/LVD
SRLatch
8-bitTimer
Device
#Single-WordInstructions
EEPROM(Bytes)
(1)
CCP
CTMU
Flash(Bytes)
SRAM(Bytes)
I/O
SPI
C™2I
PIC18(L)F23K22 8K 4096 512 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4
PIC18(L)F24K22 16K 8192 768 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4
PIC18(L)F25K22 32K 16384 1536 256 25 19 2 1 2 2 2 2 2 Y Y Y 3 4
PIC18(L)F26K22 64k 32768 3896 1024 25 19 2 1 2 2 2 2 2 Y Y Y 3 4
PIC18(L)F43K22 8K 4096 512 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4
PIC18(L)F44K22 16K 8192 768 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4
PIC18(L)F45K22 32K 16384 1536 256 36 30 2 2 1 2 2 2 2 Y Y Y 3 4
PIC18(L)F46K22 64k 32768 3896 1024 36 30 2 2 1 2 2 2 2 Y Y Y 3 4
Note 1: One pin is input only.
2: Channel count includes internal FVR and DAC channels.
DS41412F-page 4 © 2010-2012 Microchip Technology Inc.

PIC18LF46K22
Pin Diagrams (28-pin)
28-pin PDIP, SOIC, SSOP
PP/RE3 1MCLR/V
RA0 2
RA1 3
RA2 4
RA3 5
RA4 6
RA5 7
VSS 8
RA7 9
RA6 10
RC0 11
RC1 12
RC2 13
RC3 14
28-pin QFN, UQFN
(1)
PIC18(L)F2XK22
28 RB7/PGD
27 RB6/PGC
26 RB5
25 RB4
24 RB3
23 RB2
22 RB1
21 RB0
20 VDD
19 VSS
18 RC7
17 RC6
16 RC5
15 RC4
RA1RA0
MCLR/V/RE3PPRB7/PGDRB6/PGCRB5RB4
28 27 26 25 24 23 22
RA2 1 21 RB3
RA3 2 20 RB2
RA4 3
PIC18(L)F2XK22
19 RB1
RA5/ 4 18 RB0
VSS 5 17 VDD
RA7 6 16 VSS
RA6
7 8 9 10 11 12 13 14 15 RC7
RC0RC1RC2RC3RC4RC5RC6
Note 1: The 28-pin UQFN package is available only for PIC18(L)F23K22 and PIC18(L)F24K22.

PIC18LF46K22
40-pin PDIP
MCLR/VPP/RE3 1
RA0 2
RA1 3
RA2 4
RA3 5
RA4 6
RA5 7
RE0 8
RE1 9
RE2 10
VDD 11
VSS 12
RA7 13
RA6 14
RC0 15
RC1 16
RC2 17
RC3 18
RD0 19
RD1 20
PIC18(L)F4XK22
40 RB7/PGD
39 RB6/PGC
38 RB5
37 RB4
36 RB3
35 RB2
34 RB1
33 RB0
32 VDD
31 VSS
30 RD7
29 RD6
28 RD5
27 RD4
26 RC7
25 RC6
24 RC5
23 RC4
22 RD3
21 RD2

40-pin UQFN
RC6RC5RC4RD3RD2RD1RD0
RC3RC2RC1
40393837363534333231
RC7 1 30 RC0
RD4 2 29 RA6
RD5 3 28 RA7
RD6 4 27 VSS
RD7 5 PIC18(L)F4XK22 26 VDD
VSS 6 25 RE2
VDD 7 24 RE1
RB0 8 23 RE0
RB1 9 22 RA5
RB2 10 21 RA4
11121314151617181920
RB3RB4RB5PGC/RB6PGD/RB7
MCLR/V/RE3PPRA0RA1RA2RA3

pIC18LF46K22
44-pin TQFP
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
RC6RC5RC4RD3RD2RD1RD
0RC3RC2RC1NC
1
4443424140393837363534
33
2 32
3 31
4 30
6
5
PIC18(L)F4XK22 28
29
7 27
8 26
9 25
10 24
11 23
NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4

PIC18LF46K22
TABLE 1: PIC18(L)F2XK22 PIN SUMMARY
28-SSOP,SOIC28-SPDIP
28-QFN,UQFN
I/O
Analog
Comparator
CTMU
SRLatch
Reference
(E)CCP
EUSART
MSSP
Timers
Interrupts
Pull-up
Basic
2 27 RA0 AN0 C12IN0-
3 28 RA1 AN1 C12IN1-
4 1 RA2 AN2 C2IN+ VREF-
DACOUT
5 2 RA3 AN3 C1IN+ VREF+
6 3 RA4 C1OUT SRQ CCP5 T0CKI
7 4 RA5 AN4 C2OUT SRNQ HLVDIN SS1
10 7 RA6 OSC2
CLKO
9 6 RA7 OSC1
CLKI
21 18 RB0 AN12 SRI CCP4 INT0 YSS2
FLT0
22 19 RB1 AN10 C12IN3- P1C SCK2 INT1 Y
SCL2
23 20 RB2 AN8 CTED1 P1B SDI2 INT2 Y
SDA2
24 21 RB3 AN9 C12IN2- CTED2 CCP2 SDO2 Y
P2A
(1)
25 22 RB4 AN11 P1D T5G IOC Y
26 23 RB5 AN13 CCP3 T1G IOC Y
P3A
(4)
T3CKI
(2)
P2B
(3)
27 24 RB6 TX2/CK2 IOC Y PGC
28 25 RB7 RX2/DT2 IOC Y PGD
11 8 RC0 P2B
(3)
SOSCO
T1CKI
T3CKI
(2)
T3G
12 9 RC1 CCP2 SOSCI
P2A
(1)
13 10 RC2 AN14 CTPLS CCP1 T5CKI
P1A
14 11 RC3 AN15 SCK1
SCL1
15 12 RC4 AN16 SDI1
SDA1
16 13 RC5 AN17 SDO1
17 14 RC6 AN18 CCP3 TX1/CK1
P3A(4)
18 15 RC7 AN19 P3B RX1/DT1
1 26 RE3 MCLR
VPP
8 5 VSS
19 16 VSS
20 17 VDD
Note 1: CCP2/P2A multiplexed in fuses.
2: T3CKI multiplexed in fuses.
3: P2B multiplexed in fuses.
4: CCP3/P3A multiplexed in fuses.

PIC18 LF46K22
TABLE 2: PIC18(L)F4XK22 PIN SUMMARY40-PDIP
40-UQFN
44-TQFP
44-QFN
I/O
Analog
Comparator
CTMU
SRLatch
Reference
(E)CCP
EUSART
MSSP
Timers
Interrupts
Pull-up
Basic
2 17 19 19 RA0 AN0 C12IN0-
3 18 20 20 RA1 AN1 C12IN1-
4 19 21 21 RA2 AN2 C2IN+ VREF-
DACOUT
5 20 22 22 RA3 AN3 C1IN+ VREF+
6 21 23 23 RA4 C1OUT SRQ T0CKI
7 22 24 24 RA5 AN4 C2OUT SRNQ HLVDIN SS1
14 29 31 33 RA6 OSC2
CLKO
13 28 30 32 RA7 OSC1
CLKI
33 8 8 9 RB0 AN12 SRI FLT0 INT0 Y
34 9 9 10 RB1 AN10 C12IN3- INT1 Y
35 10 10 11 RB2 AN8 CTED1 INT2 Y
36 11 11 12 RB3 AN9 C12IN2- CTED2 CCP2 Y
P2A
(1)
37 12 14 14 RB4 AN11 T5G IOC Y
38 13 15 15 RB5 AN13 CCP3 T1G IOC Y
P3A
(3)
T3CKI
(2)
39 14 16 16 RB6 IOC Y PGC
40 15 17 17 RB7 IOC Y PGD
15 30 32 34 RC0 P2B
(4)
SOSCO
T1CKI
T3CKI
(2)
T3G
16 31 35 35 RC1 CCP2
(1)
SOSCI
P2A
17 32 36 36 RC2 AN14 CTPLS CCP1 T5CKI
P1A
18 33 37 37 RC3 AN15 SCK1
SCL1
23 38 42 42 RC4 AN16 SDI1
SDA1
24 39 43 43 RC5 AN17 SDO1
25 40 44 44 RC6 AN18 TX1
CK1
26 1 1 1 RC7 AN19 RX1
DT1
19 34 38 38 RD0 AN20 SCK2
SCL2
20 35 39 39 RD1 AN21 CCP4 SDI2
SDA2
21 36 40 40 RD2 AN22 P2B
(4)
22 37 41 41 RD3 AN23 P2C SS2
27 2 2 2 RD4 AN24 P2D SD02
28 3 3 3 RD5 AN25 P1B
29 4 4 4 RD6 AN26 P1C TX2
CK2
30 5 5 5 RD7 AN27 P1D RX2
DT2
8 23 25 25 RE0 AN5 CCP3
P3A
(3)

PIC18 LF46K22
TABLE 2: PIC18(L)F4XK22 PIN SUMMARY (CONTINUED)40-PDIP
40-UQFN
44-TQFP
44-QFN
I/O
Analog
Comparator
CTMU
SRLatch
Reference
(E)CCP
EUSART
MSSP
Timers
Interrupts
Pull-up
Basic
9 24 26 26 RE1 AN6 P3B
10 25 27 27 RE2 AN7 CCP5
1 16 18 18 RE3 Y MCLR
VPP
11 7, 26 7 7,8 VDD
32 28 28, 29
12 6, 27 6 6 VSS
31 29 30, 31
— — 12, 13 13 NC
33, 34
Note 1: CCP2 multiplexed in fuses.
2: T3CKI multiplexed in fuses.
3: CCP3/P3A multiplexed in fuses.
4: P2B multiplexed in fuses.

PIC18LF46K22
1.0 DEVICE OVERVIEW
This document contains device specific information for the following devices:
• PIC18F23K22 •
PIC18LF23
K22
• PIC18F24K22 •
PIC18LF24
K22
• PIC18F25K22 •
PIC18LF25
K22
• PIC18F26K22 •
PIC18LF26
K22
• PIC18F43K22 •
PIC18LF43
K22
• PIC18F44K22 •
PIC18LF44
K22
• PIC18F45K22 •
PIC18LF45
K22
• PIC18F46K22 •
PIC18LF46
K22
This family offers the advantages of all PIC18 microcontrollers – namely, high computational
performance at an economical price – with the addition of high-endurance, Flash program
memory. On top of these features, the PIC18(L)F2X/4XK22 family introduces design
enhancements that make these microcontrollers a logical choice for many high-performance,
power sensitive applications.
1.1 New Core Features
1.1.1 XLP TECHNOLOGY
All of the devices in the PIC18(L)F2X/4XK22 family incorporate a range of features that can
significantly reduce power consumption during operation. Key items include:
Alternate Run Modes: By clocking the controller from the Timer1 source or the internal
oscillator block, power consumption during code execution can be reduced by as much as 90%.
Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals
still active. In these states, power consumption can be reduced even further, to as little as 4% of
normal operation requirements.
On-the-fly Mode Switching: The power-managed modes are invoked by user code during
operation, allowing the user to incorporate power-saving ideas into their application’s software
design.
Low Consumption in Key Modules: The power requirements for both Timer1 and the
Watchdog Timer are minimized.for values.

MULTIPLE OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18(L)F2X/4XK22 family offer ten different oscillator options,
allowing users a wide range of choices in developing application hardware. These include:
• Four Crystal modes, using crystals or ceramic resonators
• Two External Clock modes, offering the option of using two pins (oscillator input and a
divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as
general I/O)
• Two External RC Oscillator modes with the same pin options as the External Clock modes
• An internal oscillator block which contains a 16 MHz HFINTOSC oscillator and a 31
kHz LFINTOSC oscillator, which together provide eight user selectable clock
frequencies, from 31 kHz to 16 MHz. This option frees the two oscillator pins for use as
additional general purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier, available to both external and internal
oscillator modes, which allows clock speeds of up to
64 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock
speeds, from 31 kHz to 64 MHz – all without using an external crystal or clock
circuit.Besides its availability as a clock source, the internal oscillator block provides a
stable reference source that gives the family additional features for robust operation:
• Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a
reference signal provided by the LFINTOSC. If a clock failure occurs, the controller is
switched to the internal oscillator block, allowing for continued operation or a safe
application shutdown.
• Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep mode, until the primary clock source available

PIC18LF46K22
1.2 Other Special Features
• Memory Endurance: The Flash cells for both program memory and data EEPROM are rated
to last for many thousands of erase/write cycles – up to 10K for program memory and 100K
for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40
years.
• Self-programmability: These devices can write to their own program memory spaces under
inter-nal software control. By using a boot loader routine located in the protected Boot Block
at the top of program memory, it becomes possible to create an application that can update
itself in the field.
• Extended Instruction Set: The PIC18(L)F2X/ 4XK22 family introduces an optional
extension to the PIC18 instruction set, which adds eight new instructions and an Indexed
Addressing mode. This extension, enabled as a device configuration option, has been
specifically designed to optimize re-entrant application code originally developed in high-level
languages, such as C.
• Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs
for controlling half-bridge and full-bridge drivers. Other features include:
- Auto-Shutdown, for disabling PWM outputs on interrupt or other select conditions
- Auto-Restart, to reactivate outputs once the condition has cleared
- Output steering to selectively enable one or more of four outputs to provide the PWM
signal.
• Enhanced Addressable EUSART: This serial communication module is capable of standard
RS-232 operation and provides support for the LIN bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When
the microcontroller is using the internal oscillator block, the EUSART provides stable
operation for applications that talk to the outside world without using an external crystal (or its
accompanying power requirement).
• 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for
a channel to be selected and a conversion to be initiated without waiting for a sampling period
and thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit postscaler,
allowing an extended time-out range that is stable across operating voltage and temperature.

PIC18LF46K22
TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Pin Name DescriptionPDIP, QFN, Type Type
SOIC UQFN
2 27 RA0/C12IN0-/AN0
RA0 I/O TTL Digital I/O.
C12IN0- I Analog Comparators C1 and C2 inverting input.
AN0 I Analog Analog input 0.
3 28 RA1/C12IN1-/AN1
4 1 RA2/C2IN+/AN2/DACOUT/VREF-
C2IN+ I Analog Comparator C2 non-inverting input.
DACOUT O Analog DAC Reference output.
VREF- I Analog A/D reference voltage (low) input.
5 2 RA3/C1IN+/AN3/VREF+
VREF+ I Analog A/D reference voltage (high) input.
6 3 RA4/CCP5/C1OUT/SRQ/T0CKI
RA4 I/O ST Digital I/O.
CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output.
C1OUT O CMOS Comparator C1 output.
SRQ O TTL SR latch Q output.
T0CKI I ST Timer0 external clock input.
7 4 RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4
SRNQ O TTL SR latch output.Q
I TTL SPI slave select input (MSSP).SS1
HLVDIN I Analog High/Low-Voltage Detect input.
10 7 RA6/CLKO/OSC2
CLKO O In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
OSC2 O Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels;
I = Input; O = Output; P = Power.
Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
2:Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.

PIC18 LF46K22
TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
SOIC UQFN
9 6 RA7/CLKI/OSC1
CLKI I CMOS External clock source input. Always associated with pin
function OSC1.
OSC1 I ST Oscillator crystal input or external clock source input ST
buffer when configured in RC mode; CMOS otherwise.
21 18 RB0/INT0/CCP4/FLT0/SRI/SS2/AN12
RB0 I/O TTL Digital I/O.
INT0 I ST External interrupt 0.
FLT0 I ST PWM Fault input for ECCP Auto-Shutdown.
SRI I ST SR latch input.
22 19 RB1/INT1/P1C/SCK2/SCL2/C12IN3-/AN10
P1C O CMOS Enhanced CCP1 PWM output.
SCK2 I/O ST Synchronous serial clock input/output for SPI mode
(MSSP).
SCL2 I/O ST Synchronous serial clock input/output for I
2
C™ mode
(MSSP).
23 20 RB2/INT2/CTED1/P1B/SDI2/SDA2/AN8
CTED1 I ST CTMU Edge 1 input.
P1B O CMOS Enhanced CCP1 PWM output.
SDI2 I ST SPI data in (MSSP).
SDA2 I/O ST I
2
C™ data I/O (MSSP).
24 21 RB3/CTED2/P2A/CCP2/SDO2/C12IN2-/AN9
P2A O CMOS Enhanced CCP2 PWM output.
CCP2
(2)
I/O ST Capture 2 input/Compare 2 output/PWM 2 output.
SDO2 O — SPI data out (MSSP).
CCP2MX are set.
CCP2MX are clear.
DS41412F-page 18 2010-2012 Microchip

PIC18 LF46K22
Pin Number
Pin Buffer
SOIC UQFN
25 22 RB4/IOC0/P1D/T5G/AN11
IOC0 I TTL Interrupt-on-change pin.
P1D O CMOS Enhanced CCP1 PWM output.
T5G I ST Timer5 external clock gate input.
26 23 RB5/IOC1/P2B/P3A/CCP3/T3CKI/T1G/AN13
P2B
(1)
O CMOS Enhanced CCP2 PWM output.
P3A(1) O CMOS Enhanced CCP3 PWM output.
CCP3
(1)
T3CKI
(2)
I ST Timer3 clock input.
27 24 RB6/IOC2/TX2/CK2/PGC
TX2 O — EUSART asynchronous transmit.
CK2 I/O ST EUSART synchronous clock (see related RXx/DTx).
PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin.
28 25 RB7/IOC3/RX2/DT2/PGD
RX2 I ST EUSART asynchronous receive.
DT2 I/O ST EUSART synchronous data (see related TXx/CKx).
PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin.
11 8 RC0/P2B/T3CKI/T3G/T1CKI/SOSCO
RC0 I/O TTL Digital I/O.
P2B
(2)
T3CKI
(1)
T1CKI I ST Timer1 clock input.
SOSCO O — Secondary oscillator output.
12 9 RC1/P2A/CCP2/SOSCI
CCP2
(1)
SOSCI I Analog Secondary oscillator input.
CCP2MX are set.
CCP2MX are clear.

PIC18 LF46K22
Pin Number
Pin Buffer
SOIC UQFN
13 10 RC2/CTPLS/P1A/CCP1/T5CKI/AN14
CTPLS O — CTMU pulse generator output.
14 11 RC3/SCK1/SCL1/AN15
SCK1 I/O ST Synchronous serial clock input/output for SPI mode
(MSSP).
2
C™ mode
(MSSP).
15 12 RC4/SDI1/SDA1/AN16
SDA1 I/O ST I
2
16 13 RC5/SDO1/AN17
17 14 RC6/P3A/CCP3/TX1/CK1/AN18
CCP3
(2)
CK1 I/O ST EUSART synchronous clock (see related RXx/DTx).
18 15 RC7/P3B/RX1/DT1/AN19
DT1 I/O ST EUSART synchronous data (see related TXx/CKx).
1 26 RE3/VPP /MCLR
RE3 I ST Digital input.
VPP P Programming voltage input.
I ST Active-Low Master Clear (device Reset) input.MCLR
CCP2MX are set.
PIC18 LF46K22
Pin Number
Pin Buffer
SOIC UQFN

20 17 VDD P — Positive supply for logic and I/O pins.
8, 19 5, 16 VSS P — Ground reference for logic and I/O pins.
CCP2MX are set.
CCP2MX are clear.
TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Name
Pin Buffer
Description
PDIP TQFP QFN UQFN Type Type
2 19 19 17 RA0/C12IN0-/AN0
3 20 20 18 RA1/C12IN1-/AN1
4 21 21 19 RA2/C2IN+/AN2/DACOUT/VREF-
DACOUT O Analog DAC Reference output.
VREF- I Analog A/D reference voltage (low) input.
5 22 22 20 RA3/C1IN+/AN3/VREF+
VREF+ I Analog A/D reference voltage (high) input.
6 23 23 21 RA4/C1OUT/SRQ/T0CKI
RA4 I/O ST Digital I/O.
SRQ O TTL SR latch Q output.
T0CKI I ST Timer0 external clock input.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS
levels; I = Input; O = Output; P = Power.
Note 1: Default pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX, CCP3MX
and CCP2MX are set.
2: Alternate pin assignment for P2B, T3CKI, CCP3/P3A and CCP2/P2A when Configuration bits PB2MX, T3CMX,
CCP3MX and CCP2MX are clear.

PIC18 LF46K22
Pin Number
Pin Name
Pin Buffer
Description
7 24 24 22 RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4
SRNQ O TTL SR latch output.Q
I TTL SPI slave select input (MSSP1).SS1
HLVDIN I Analog High/Low-Voltage Detect input.
14 31 33 29 RA6/CLKO/OSC2
CLKO O — In RC mode, OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
OSC2 O — Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
13 30 32 28 RA7/CLKI/OSC1
CLKI I CMOS External clock source input. Always associated
with pin function OSC1.
OSC1 I ST Oscillator crystal input or external clock source
input ST buffer when configured in RC mode;
CMOS otherwise.
33 8 9 8 RB0/INT0/FLT0/SRI/AN12
FLT0 I ST PWM Fault input for ECCP Auto-Shutdown.
SRI I ST SR latch input.
34 9 10 9 RB1/INT1/C12IN3-/AN10
35 10 11 10 RB2/INT2/CTED1/AN8
36 11 12 11 RB3/CTED2/P2A/CCP2/C12IN2-/AN9
CCP2
(2)
and CCP2MX are set.

PIC18 LF46K22
Pin Number
Pin Name
Pin Buffer
Description
37 14 14 12 RB4/IOC0/T5G/AN11
38 15 15 13 RB5/IOC1/P3A/CCP3/T3CKI/T1G/AN13
P3A
(1)
CCP3
(1)
T3CKI
(2)
39 16 16 14 RB6/IOC2/PGC
PGC I/O ST In-Circuit Debugger and ICSP™ programming
clock pin.
40 17 17 15 RB7/IOC3/PGD
PGD I/O ST In-Circuit Debugger and ICSP™ programming
data pin.
15 32 34 30 RC0/P2B/T3CKI/T3G/T1CKI/SOSCO
RC0 I/O ST Digital I/O.
P2B
(2)
T3CKI
(1)
SOSCO O — Secondary oscillator output.
16 35 35 31 RC1/P2A/CCP2/SOSCI
P2A
(1)
CCP2
(1)
SOSCI I Analog Secondary oscillator input.
17 36 36 32 RC2/CTPLS/P1A/CCP1/T5CKI/AN14
CTPLS O — CTMU pulse generator output.
and CCP2MX are set.

PIC18 LF46K22
Pin Number
Pin Name
Pin Buffer
Description
18 37 37 33 RC3/SCK1/SCL1/AN15
SCK1 I/O ST Synchronous serial clock input/output for SPI
mode (MSSP).
2
C™
mode (MSSP).
23 42 42 38 RC4/SDI1/SDA1/AN16
SDA1 I/O ST I
2
24 43 43 39 RC5/SDO1/AN17
25 44 44 40 RC6/TX1/CK1/AN18
CK1 I/O ST EUSART synchronous clock (see related RXx/
DTx).
26 1 1 1 RC7/RX1/DT1/AN19
DT1 I/O ST EUSART synchronous data (see related TXx/
CKx).
19 38 38 34 RD0/SCK2/SCL2/AN20
RD0 I/O ST Digital I/O.
SCK2 I/O ST Synchronous serial clock input/output for SPI
mode (MSSP).
2
C™
mode (MSSP).
20 39 39 35 RD1/CCP4/SDI2/SDA2/AN21
SDA2 I/O ST I
2
and CCP2MX are set.

Technology Inc.

PIC18 LF46K22
Pin Number
Pin Name
Pin Buffer
Description
21 40 40 36 RD2/P2B/AN22
RD2 I/O ST Digital I/O
P2B(1) O CMOS Enhanced CCP2 PWM output.
22 41 41 37 RD3/P2C/SS2/AN23
27 2 2 2 RD4/P2D/SDO2/AN24
28 3 3 3 RD5/P1B/AN25
29 4 4 4 RD6/P1C/TX2/CK2/AN26
CK2 I/O ST EUSART synchronous clock (see related RXx/
DTx).
30 5 5 5 RD7/P1D/RX2/DT2/AN27
DT2 I/O ST EUSART synchronous data (see related TXx/
CKx).
8 25 25 23 RE0/P3A/CCP3/AN5
RE0 I/O ST Digital I/O.
P3A
(2)
CCP3
(2)
9 26 26 24 RE1/P3B/AN6
and CCP2MX are set.

PIC18 LF46K22
Pin Number
Pin Name
Pin Buffer
Description
10 27 27 25 RE2/CCP5/AN7
CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output
1 18 18 16 RE3/VPP /MCLR
RE3 I ST Digital input.
VPP P Programming voltage input.
I ST Active-low Master Clear (device Reset) input.MCLR
11,32 7, 28 7, 8, 7, 26 VDD P — Positive supply for logic and I/O pins.
28, 29
12,31 6, 29 6,30, 6, 27 VSS P — Ground reference for logic and I/O pins.
31
12,13, 13 NC
33,34
and CCP2MX are set.

PIC18 LF46K22
2.0 OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
2.1 Overview
The oscillator module has a wide variety of clock sources
and selection features that allow it to be used in a wide
range of applications while maximizing perfor-mance and
minimizing power consumption. Figure 2-1 illustrates a
block diagram of the oscillator module.
Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of three
internal oscillators, with a choice of speeds selectable via
software. Additional clock features include:
• Selectable system clock source between
external or internal sources via software.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up
and code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source
(LP, XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures
stability of crystal oscillator sources.
The primary clock module can be configured to
provide one of six clock sources as the primary clock.
1. RC External Resistor/Capacitor
2. LP Low-Power Crystal
3. XT Crystal/Resonator
4. INTOSC Internal Oscillator
5. HS High-Speed Crystal/Resonator
6. EC External Clock
The HS and EC oscillator circuits can be optimized for
power consumption and oscillator speed using
settings in FOSC<3:0>. Additional FOSC<3:0>
selections enable RA6 to be used as I/O or CLKO
(FOSC/4) for RC, EC and INTOSC Oscillator modes.
Primary Clock modes are selectable by the
FOSC<3:0> bits of the CONFIG1H Configuration
register. The primary clock operation is further defined
by these Configuration and register bits:
1. PRICLKEN (CONFIG1H<5>)
2. PRISD (OSCCON2<2>)
3. PLLCFG (CONFIG1H<4>)
4. PLLEN (OSCTUNE<6>)
5. HFOFST (CONFIG3H<3>)
6. IRCF<2:0> (OSCCON<6:4>)
7. MFIOSEL (OSCCON2<4>)
8. INTSRC (OSCTUNE<7>)
The HFINTOSC, MFINTOSC and LFINTOSC are
factory calibrated high, medium and low-frequency
oscillators, respectively, which are used as the
internal clock sources.

PIC18 LF46K22
FIGURE 2-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM
Secondary Oscillator
(1)
SOSCO Secondary
Oscillator
SOSCI
(SOSC)
Primary Clock Module
PRICLKEN
PRISD
EN
OSC2 Primary
Oscillator
(2)
OSC1
(OSC)
Internal Oscillator
IRCF<2:0>
MFIOSEL
3
HFINTOSC
(16 MHz)
INTOSC
Divide
Circuit
MFINTOSC
(500 kHz)
Low-Power Mode
SOSCOUT Event Switch
(SCS<1:0>)
2
Secondary
Oscillator
01
PLL_Select
(3) (4)
FOSC<3:0>
(5)
Clock
Primary Oscillator 0 4xPLL 0 Primary
Switch
Clock 00
INTOSC
1 1
MUX
INTOSC
1x
INTSRC
3
HF-16 MHZ
HF-8 MHZ
HF-4 MHZ
Internal
HF-2 MHZ
HF-1 MHZ
HF-500 kHZ
MUXOscillator
HF-250 kHZ
INTOSCHF-31.25 kHZ
MF-500 kHZ
(
3
MF-250 kHZ
MF-31.25 kHZ
LFINTOSC LF-31.25 kHz
(31.25 kHz)
Note 1: Details in Figure 2-4.
2: Details in Figure 2-2.
3: Details in Figure 2-3.
4: Details in Table 2-1.
5: The Primary Oscillator MUX uses the INTOSC branch when FOSC<3:0> = 100x.

PIC18(L)F2X/4XK22
2.2 Oscillator Control
The OSCCON, OSCCON2 and OSCTUNE registers
(Register 2-1 to Register 2-3) control several aspects
of the device clock’s operation, both in full-power
operation and in power-managed modes.
• Main System Clock Selection (SCS)
• Primary Oscillator Circuit Shutdown (PRISD)
• Secondary Oscillator Enable (SOSCGO)
• Primary Clock Frequency 4x multiplier (PLLEN)
• Internal Frequency selection bits (IRCF, INTSRC)
• Clock Status bits (OSTS, HFIOFS,
MFIOFS, LFIOFS. SOSCRUN, PLLRDY)
• Power management selection (IDLEN)
2.2.1 MAIN SYSTEM CLOCK SELECTION
The System Clock Select bits, SCS<1:0>, select the
main clock source. The available clock sources are
• Primary clock defined by the FOSC<3:0> bits of
CONFIG1H. The primary clock can be the
primary oscillator, an external clock, or the
internal oscillator block.
• Secondary clock (secondary oscillator)
• Internal oscillator block (HFINTOSC,
MFINTOSC and LFINTOSC).
The clock source changes immediately after one or
more of the bits is written to, following a brief clock
transition interval. The SCS bits are cleared to select
the primary clock on all forms of Reset.
2.2.2 INTERNAL FREQUENCY
SELECTION
The Internal Oscillator Frequency Select bits
(IRCF<2:0>) select the frequency output of the internal
oscillator block. The choices are the LFINTOSC source
(31.25 kHz), the MFINTOSC source (31.25 kHz,
250 kHz or 500 kHz) and the HFINTOSC source
(16 MHz) or one of the frequencies derived from the
HFINTOSC postscaler (31.25 kHz to 8 MHz). If the
internal oscillator block is supplying the main clock,
changing the states of these bits will have an immedi-
ate change on the internal oscillator’s output. On
device Resets, the output frequency of the internal
oscillator is set to the default frequency of 1 MHz.
2.2.3 LOW FREQUENCY SELECTION
When a nominal output frequency of 31.25 kHz is
selected (IRCF<2:0> = 000), users may choose
which internal oscillator acts as the source. This is
done with the INTSRC bit of the OSCTUNE register
and MFIOSEL bit of the OSCCON2 register. See
Figure 2-2 and Register 2-1 for specific 31.25 kHz
selection. This option allows users to select a 31.25
kHz clock (MFINTOSC or HFINTOSC) that can be
tuned using the TUN<5:0> bits in OSCTUNE register,
while maintaining power savings with a very low clock
speed. LFINTOSC always remains the clock source
for features such as the Watchdog Timer and the Fail-
Safe Clock Monitor, regardless of the setting of
INTSRC and MFIOSEL bits
This option allows users to select the tunable and more
precise HFINTOSC as a clock source, while maintaining
power savings with a very low clock speed.
2.2.4 POWER MANAGEMENT
The IDLEN bit of the OSCCON register determines
whether the device goes into Sleep mode or one of the
Idle modes when the SLEEP instruction is executed.

PIC18(L)F2X/4XK22
FIGURE 2-2: INTERNAL OSCILLATOR MUX
BLOCK DIAGRAM
IRCF<2:0>
MFIOSEL
INTSRC
3
HF-16 MHZ 111
HF-8 MHZ 110
HF-4 MHZ 101
HF-2 MHZ 100
HF-1 MHZ
011
MF-500 KHZ
1 500 kHZ
HF-500 KHZ
010 INTOSC
0
MF-250 KHZ
1 250 kHZ
HF-250 KHZ
001
0
HF-31.25 KHZ 11
31.25 kHZMF-31.25 KHZ
10 000LF-31.25 KHZ
0X
TABLE 2-1: PLL_SELECT TRUTH TABLE
FIGURE 2-3: PLL_SELECT BLOCK
DIAGRAM
FOSC<3:0> = 100x
PLLCFG
PLLEN PLL_Select
Primary Clock MUX Source FOSC<3:0> PLLCFG PLLEN PLL_Select
FOSC (any source) 0000-1111 0 0 0
OSC1/OSC2 (external source) 0000-0111 1 x 1
1010-1111 0 1 1
INTOSC (internal source) 1000-1001 x 0 0
x 1 1

PIC18(L)F2X/4XK22
FIGURE 2-4: SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS
SOSCEN
SOSCGO
T1SOSCEN
T3SOSCEN
T5SOSCEN
To Clock Switch Module
SOSCI
EN
Secondary SOSCOUT
Oscillator
SOSCO
1T1CKI
T3G SOSCEN T1CLK_EXT_SRC
T3CKI
0
SOSCEN T1SOSCEN
T3G
SOSCEN
0
1
T3CLK_EXT_SRC
T3CKI 1
0
T3SOSCEN
T1G
T3CMX
T1G
1
T5CLK_EXT_SRC
T5CKI 0
T5SOSCEN
T5G T5G

PIC18(L)F2X/4XK22
2.3 Register Definitions: Oscillator Control
REGISTER 2-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R-q R-0 R/W-0 R/W-0
IDLEN IRCF<2:0> OSTS
(1)
HFIOFS SCS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 IRCF<2:0>: Internal RC Oscillator Frequency Select bits
(2)
111 = HFINTOSC – (16 MHz)
110 = HFINTOSC/2 – (8 MHz)
(3)
If INTSRC = 0 and MFIOSEL = 0:
010 = HFINTOSC/32 – (500 kHz)
001 = HFINTOSC/64 – (250 kHz)
000 = LFINTOSC – (31.25 kHz)
010 = HFINTOSC/32 – (500 kHz)
001 = HFINTOSC/64 – (250 kHz)
000 = HFINTOSC/512 – (31.25 kHz)
010 = MFINTOSC – (500 kHz)
001 = MFINTOSC/2 – (250 kHz)
000 = LFINTOSC – (31.25 kHz)
010 = MFINTOSC – (500 kHz)
001 = MFINTOSC/2 – (250 kHz)
000 = MFINTOSC/16 – (31.25 kHz)
bit 3 OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the clock defined by FOSC<3:0> of the CONFIG1H register
0 = Device is running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC)
bit 2 HFIOFS: HFINTOSC Frequency Stable bit
1 = HFINTOSC frequency is stable
0 = HFINTOSC frequency is not stable
bit 1-0 SCS<1:0>: System Clock Select bit
1x = Internal oscillator block
01 = Secondary (SOSC) oscillator
00 = Primary clock (determined by FOSC<3:0> in CONFIG1H).
Note 1: Reset state depends on state of the IESO Configuration bit.
2:INTOSC source may be determined by the INTSRC bit in OSCTUNE and the MFIOSEL bit in OSCCON2.
3:Default output frequency of HFINTOSC on Reset.

PIC18(L)F2X/4XK22
REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2
R-0/0 R-0/q U-0 R/W-0/0 R/W-0/u R/W-1/1 R-x/u R-0/0
PLLRDY SOSCRUN — MFIOSEL SOSCGO
(1)
PRISD MFIOFS LFIOFS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
bit 7 PLLRDY: PLL Run Status bit
1 = System clock comes from 4xPLL
0 = System clock comes from an oscillator, other than 4xPLL
bit 6 SOSCRUN: SOSC Run Status bit
1 = System clock comes from secondary SOSC
0 = System clock comes from an oscillator, other than SOSC
bit 5 Unimplemented: Read as ‘0’.
bit 4 MFIOSEL: MFINTOSC Select bit
1 = MFINTOSC is used in place of HFINTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz
0 = MFINTOSC is not used
bit 3 SOSCGO
(1)
: Secondary Oscillator Start Control bit
1 = Secondary oscillator is enabled.
0 = Secondary oscillator is shut off if no other sources are requesting it.
bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit
1 = Oscillator drive circuit on
0 = Oscillator drive circuit off (zero power)
bit 1 MFIOFS: MFINTOSC Frequency Stable bit
1 = MFINTOSC is stable
0 = MFINTOSC is not stable
bit 0 LFIOFS: LFINTOSC Frequency Stable bit
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
Note 1: The SOSCGO bit is only reset on a POR Reset.

PIC18(L)F2X/4XK22
2.4 Clock Source Modes
Clock Source modes can be classified as external or
internal.
• External Clock modes rely on external circuitry
for the clock source. Examples are: Clock
modules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC mode) circuits.
• Internal clock sources are contained internally
within the Oscillator block. The Oscillator block
has three internal oscillators: the 16 MHz High-
Frequency Internal Oscillator (HFINTOSC), 500
kHz Medium-Frequency Internal Oscillator
(MFINTOSC) and the 31.25 kHz Low-
Frequency Internal Oscillator (LFINTOSC).
The system clock can be selected between external
or internal clock sources via the System Clock Select
(SCS<1:0>) bits of the OSCCON register. See
Section 2.11 “Clock Switching” for additional
information.
TABLE 2-2: OSCILLATOR DELAY EXAMPLES
2.5 External Clock Modes
2.5.1 OSCILLATOR START-UP TIMER (OST)
When the oscillator module is configured for LP, XT or
HS modes, the Oscillator Start -up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and is
providing a stable system clock to the oscillator module.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 2-2.
In order to minimize latency between external
oscillator start-up and code execution, the Two
-Speed Clock Start-up mode can be selected (see
Section 2.12 “Two-Speed Clock Start-up Mode”).
Switch From Switch To Frequency Oscillator Delay
LFINTOSC 31.25 kHz
Sleep/POR MFINTOSC 31.25 kHz to 500 kHz Oscillator Warm-Up Delay (TWARM)
HFINTOSC 31.25 kHz to 16 MHz
Sleep/POR EC, RC DC – 64 MHz 2 instruction cycles
LFINTOSC (31.25 kHz) EC, RC DC – 64 MHz 1 cycle of each
Sleep/POR LP, XT, HS 32 kHz to 40 MHz 1024 Clock Cycles (OST)
Sleep/POR 4xPLL 32 MHz to 64 MHz 1024 Clock Cycles (OST) + 2 ms
LFINTOSC (31.25 kHz) LFINTOSC 31.25 kHz to 16 MHz 1 µs (approx.)
HFINTOSC
2.5.2 EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source.
When operating in this mode, an external clock
source is connected to the OSC1 input and the OSC2
is available for general purpose I/O. Figure 2-5 shows
the pin connections for EC mode.
The External Clock (EC) offers different power
modes, Low Power (ECLP), Medium Power (ECMP)
and High Power (ECHP), selectable by the
FOSC<3:0> bits. Each mode is best suited for a
certain range of frequencies. The ranges are:
• ECLP – below 500 kHz
• ECMP – between 500 kHz and 16 MHz
• ECHP – above 16 MHz
effect of halting the device while leaving all data
intact. Upon restarting the external clock, the device
will resume operation as if no time had elapsed.
FIGURE 2-5: EXTERNAL CLOCK (EC)
MODE OPERATION
Clock from OSC1/CLKIN
Ext. System
PIC
®
MCU
I/O OSC2/CLKOUT
(1)
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC
®
MCU design is fully
static, stopping the external clock input will have the

PIC18(L)F2X/4XK22
2.5.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 2-6) . The mode selects a low,
medium or high gain setting of the internal inverter-
amplifier to support various resonator types and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is best suited
to drive resonators with a low drive level specification, for
example, tuning fork type crystals.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three
modes. This mode is best suited to drive resonators
with a medium drive level specification.
HS Oscillator mode offers a Medium Power (MP) and
a High Power (HP) option selectable by the
FOSC<3:0> bits. The MP selections are best suited
for oscillator frequencies between 4 MHz and 16
MHz. The HP selection has the highest gain setting of
the internal inverter-amplifier and is best suited for
frequencies above 16 MHz. HS mode is best suited
for resonators that require a high drive setting.
FIGURE 2-6: QUARTZ CRYSTAL
OPERATION (LP, XT
OR HS MODE)
PIC
®
MCU
OSC1/CLKIN
C1 To Internal
Logic
Quartz RF(2) Sleep
Crystal
C2 RS(1) OSC2/CLKOUT
Note 1: A series resistor (RS) may be required for quartz
crystals with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 MΩ).
Note 1: Quartz crystal characteristics vary according
to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and
recommended application.
2: Always verify oscillator performance
over the VDD and temperature range
that is expected for the application.
3: For oscillator design assistance, refer to
the following Microchip Application Notes:
•AN826, “Crystal Oscillator Basics
and Crystal Selection for rfPIC
®
and PIC
®
Devices” (DS00826)
•AN849, “Basic PIC
®
Oscillator Design”
(DS00849)
•AN943, “Practical PIC
®
Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
FIGURE 2-7: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC
®
MCU
OSC1/CLKIN
C1 To Internal
Logic
RP(3) RF(2) Sleep
C2 Ceramic RS
(1) OSC2/CLKOUT
Resonator
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 MΩ to 10 MΩ).
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.

PIC18(L)F2X/4XK22
2.5.4 EXTERNAL RC MODES
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is
not required. There are two modes: RC and RCIO.
2.5.4.1 RC Mode
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by four. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 2-8 shows the
external RC mode connections.
FIGURE 2-8: EXTERNAL RC MODES
VDD
PIC
®
MCU
REXT
OSC1/CLKIN Internal
CEXT
Clock
VSS
FOSC/4 or OSC2/CLKOUT
(1)
I/O
(2)
Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
2: Output depends upon RC or RCIO clock mode.
2.5.4.2 RCIO Mode
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes a general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT)
values and the operating temperature. Other factors
affecting the oscillator frequency are:
• input threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation
due to tolerance of external RC components used.
2.6 Internal Clock Modes
The oscillator module has three independent, internal
oscillators that can be configured or selected as the
system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The frequency of the HFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 2-3).
2. The MFINTOSC (Medium-Frequency Internal
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 2-3).
3. The LFINTOSC (Low-Frequency Internal
31.25 kHz. The LFINTOSC cannot be user-
adjusted, but is designed to be stable over
temperature and voltage.
The system clock speed can be selected via software
using the Internal Oscillator Frequency select bits
IRCF<2:0> of the OSCCON register.
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS<1:0>) bits of the OSCCON register. See
Section 2.11 “Clock Switching” for more information.
2.6.1 INTOSC WITH I/O OR CLOCKOUT
Two of the clock modes selectable with the FOSC<3:0>
bits of the CONFIG1H Configuration register configure
the internal oscillator block as the primary oscillator.
Mode selection determines whether OSC2/CLKOUT/
RA7 will be configured as general purpose I/O (RA7) or
FOSC/4 (CLKOUT). In both modes, OSC1/CLKIN/RA7 is
configured as general purpose I/O. See
Section 24.0 “Special Features of the CPU” for
more information.
The CLKOUT signal may be used to provide a clock
for external circuitry, synchronization, calibration, test
or other application requirements.

PIC18(L)F2X/4XK22
2.6.1.1 OSCTUNE Register
The HFINTOSC/MFINTOSC oscillator circuits are
factory calibrated but can be adjusted in software by
writing to the TUN<5:0> bits of the OSCTUNE register
(Register 2-3).
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC/MFINTOSC frequency will begin shifting to
the new frequency. Code execution continues during this
shift. There is no indication that the shift has occurred.
The TUN<5:0> bits in OSCTUNE do not affect the
LFINTOSC frequency. Operation of features that depend
on the LFINTOSC clock source frequency, such as the
Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-
Safe Clock Monitor (FSCM) and peripherals, are not
affected by the change in frequency.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31.25
kHz frequency option is selected. This is covered in
greater detail in Section 2.2.3 “Low Frequency
Selection”.
The PLLEN bit controls the operation of the frequency
multiplier, PLL, for all primary external clock sources
and internal oscillator modes. However, the PLL is
intended for operation with clock sources between 4
MHz and 16 MHz. For more details about the function
of the PLLEN bit, see Section 2.8.2 “PLL in HFIN-
TOSC Modes”
2.7 Register Definitions: Oscillator Tuning
REGISTER 2-3: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC PLLEN
(1)
TUN<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from the MFINTOSC or HFINTOSC source
0 = 31.25 kHz device clock derived directly from LFINTOSC internal oscillator
bit 6 PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit
(1)
1 = PLL enabled
0 = PLL disabled
bit 5-0 TUN<5:0>: Frequency Tuning bits – use to adjust MFINTOSC and HFINTOSC frequencies
011111 = Maximum frequency
011110 =
• • •
000001 =
000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated
frequency.
111111 =
• • •
100000 = Minimum frequency
Note 1: The PLLEN bit is active for all the primary clock sources (internal or external) and is designed to operate
with clock frequencies between 4 MHz and 16 MHz.

PIC18(L)F2X/4XK22
2.7.1 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
a 31.25 kHz internal clock source. The LFINTOSC is
not tunable, but is designed to be stable across
temper-ature and voltage. See Section 27.0
“Electrical Char-acteristics” for the LFINTOSC
accuracy specifications.
The output of the LFINTOSC can be a clock source to
the primary clock or the INTOSC clock (see Figure 2-
1). The LFINTOSC is also the clock source for the
Power-up Timer (PWRT), Watchdog Timer (WDT)
and Fail-Safe Clock Monitor (FSCM).
2.7.2 FREQUENCY SELECT BITS (IRCF)
The HFINTOSC (16 MHz) and MFINTOSC (500 MHz)
outputs connect to a divide circuit that provides
frequencies of 16 MHz to 31.25 kHz. These divide
circuit frequencies, along with the 31.25 kHz
LFINTOSC output, are multiplexed to provide a single
INTOSC clock output (see Figure 2-1). The
IRCF<2:0> bits of the OSCCON register, the
MFIOSEL bit of the OSCCON2 register and the
INTSRC bit of the OSCTUNE register, select the
output frequency of the internal oscillators. One of
eight frequencies can be selected via software:
• 16 MHz
• 8 MHz
• 4 MHz
• 2 MHz
• 1 MHz (default after Reset)
• 500 kHz (MFINTOSC or HFINTOSC)
• 250 kHz (MFINTOSC or HFINTOSC)
• 31 kHz (LFINTOSC, MFINTOSC or HFINTOSC)
2.7.3 INTOSC FREQUENCY DRIFT
The factory calibrates the internal oscillator block outputs
(HFINTOSC/MFINTOSC) for 16 MHz/500 kHz. However,
this frequency may drift as VDD or temperature changes.
It is possible to adjust the HFINTOSC/MFINTOSC fre-
quency by modifying the value of the TUN<5:0> bits in
the OSCTUNE register. This has no effect on the
LFINTOSC clock source frequency.
Tuning the HFINTOSC/MFINTOSC source requires
knowing when to make the adjustment, in which direc-
tion it should be made and, in some cases, how large
a change is needed. Three possible compensation
tech-niques are discussed in the following sections.
However, other techniques may be used.
2.7.3.1 Compensating with the EUSART
An adjustment may be required when the EUSART
begins to generate framing errors or receives data
with errors while in Asynchronous mode. Framing
errors indicate that the device clock frequency is too
high; to adjust for this, decrement the value in
OSCTUNE to reduce the clock frequency. On the
other hand, errors in data may suggest that the clock
speed is too low; to compensate, increment
OSCTUNE to increase the clock frequency.
2.7.3.2 Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
the OSCTUNE register.
2.7.3.3 Compensating with the CCP Module in
Capture Mode
A CCP module can use free running Timer1, Timer3 or
Timer5 clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use later.
When the second event causes a capture, the time of the
first event is subtracted from the time of the second
event. Since the period of the external event is known,
the time difference between events can be calculated.
If the measured time is much greater than the calcu-lated
time, the internal oscillator block is running too fast; to
compensate, decrement the OSCTUNE register. If the
measured time is much less than the calculated time, the
internal oscillator block is running too slow; to
compensate, increment the OSCTUNE register.

PIC18(L)F2X/4XK22
2.8 PLL Frequency Multiplier
A Phase-Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from the crystal oscillator. This may
be useful for customers who are concerned with EMI
due to high-frequency crystals or users who require
higher clock speeds from an internal oscillator.
2.8.1 PLL IN EXTERNAL OSCILLATOR
MODES
The PLL can be enabled for any of the external
oscillator modes using the OSC1/OSC2 pins by either
setting the PLLCFG bit (CONFIG1H<4>), or setting
the PLLEN bit (OSCTUNE<6>). The PLL is designed
for input frequencies of 4 MHz up to 16 MHz. The PLL
then multiplies the oscillator output frequency by four
to produce an internal clock frequency up to 64 MHz.
Oscillator frequencies below 4 MHz should not be
used with the PLL.
2.8.2 PLL IN HFINTOSC MODES
The 4x frequency multiplier can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with the internal
oscillator. When enabled, the PLL multiplies the
HFINTOSC by four to produce clock rates up to 64
MHz.
Unlike external clock modes, when internal clock
modes are enabled, the PLL can only be controlled
through software. The PLLEN control bit of the
OSCTUNE register is used to enable or disable the
PLL operation when the HFINTOSC is used.
The PLL is designed for input frequencies of 4 MHz
up to 16 MHz.

PIC18(L)F2X/4XK22
2.9 Effects of Power-Managed Modes
on the Various Clock Sources
For more information about the modes discussed in this
section see Section 3.0 “Power-Managed Modes”. A
quick reference list is also available in Table 3-1.
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power -managed modes, the oscillator using
the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin,
if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the secondary oscillator (SOSC) is
operating and providing the device clock. The
secondary oscillator may also run in all power-
managed modes if required to clock Timer1, Timer3
or Timer5.
In internal oscillator modes (INTOSC_RUN and
INTOSC_IDLE), the internal oscillator block provides
the device clock source. The 31.25 kHz LFINTOSC
output can be used directly to provide the clock and
may be enabled to support various special features,
regardless of the power-managed mode (see
Section 24.3 “Watchdog Timer (WDT)”, Section 2.12
“Two-Speed Clock Start-up Mode” and Section 2.13
“Fail- Safe Clock Monitor” for more information on
WDT, Fail-Safe Clock Monitor and Two-Speed Start -up).
The HFINTOSC and MFINTOSC outputs may be used
directly to clock the device or may be divided down by
the postscaler. The HFINTOSC and MFINTOSC outputs
are disabled when the clock is provided directly from the
LFINTOSC output.
When the Sleep mode is selected, all clock sources
are stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The LFINTOSC is required to support WDT operation.
Other features may be operating that do not require a
device clock source (i.e., SSP slave, PSP, INTn pins and
others). Peripherals that may add significant current
consumption are listed in Section 27.8 “DC
Characteristics: Input/Output Characteristics,
PIC18(L)F2X/4XK22”.
2.10 Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most
applications. The delays ensure that the device is
kept in Reset until the device power supply is stable
under normal circumstances and the primary clock is
operating and stable. For additional information on
power-up delays, see Section 4.6 “Device Reset
Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up. It is enabled by
clearing (= 0) the PWRTEN Configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes).
The OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the PLL is enabled with external oscillator
modes, the device is kept in Reset for an additional 2
ms, following the OST delay, so the PLL can lock to
the incoming clock frequency.
There is a delay of interval TCSD, following POR, while
the controller becomes ready to execute instructions.
This delay runs concurrently with any other delays.
This may be the only delay that occurs when any of
the EC, RC or INTIOSC modes are used as the
primary clock source.
When the HFINTOSC is selected as the primary
clock, the main system clock can be delayed until the
HFINTOSC is stable. This is user selectable by the
HFOFST bit of the CONFIG3H Configuration register.
When the HFOFST bit is cleared, the main system
clock is delayed until the HFINTOSC is stable. When
the HFOFST bit is set, the main system clock starts
immediately.
In either case, the HFIOFS bit of the OSCCON
register can be read to determine whether the
HFINTOSC is operating and stable.

PIC18(L)F2X/4XK22
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode OSC1 Pin OSC2 Pin
RC, INTOSC with CLKOUT Floating, external resistor should pull high At logic low (clock/4 output)
RC with IO Floating, external resistor should pull high Configured as PORTA, bit 6
INTOSC with IO Configured as PORTA, bit 7 Configured as PORTA, bit 6
EC with IO Floating, pulled by external clock Configured as PORTA, bit 6
EC with CLKOUT Floating, pulled by external clock At logic low (clock/4 output)
LP, XT, HS Feedback inverter disabled at quiescent Feedback inverter disabled at quiescent
voltage level voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
2.11 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS<1:0>) bits of the
OSCCON register.
PIC18(L)F2X/4XK22 devices contain circuitry to pre-
vent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
2.11.1 SYSTEM CLOCK SELECT
(SCS<1:0>) BITS
The System Clock Select (SCS<1:0>) bits of the
OSCCON register select the system clock source that
is used for the CPU and peripherals.
• When SCS<1:0> = 00, the system clock source
is determined by configuration of the FOSC<3:0>
bits in the CONFIG1H Configuration register.
is chosen by the internal oscillator frequency
selected by the INTSRC bit of the OSCTUNE
register, the MFIOSEL bit of the OSCCON2
register and the IRCF<2:0> bits of the OSCCON
register.
is the 32.768 kHz secondary oscillator shared
with Timer1, Timer3 and Timer5.
After a Reset, the SCS<1:0> bits of the OSCCON
register are always cleared.
Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the
SCS<1:0> bits of the OSCCON register.
The user can monitor the SOSCRUN,
MFIOFS and LFIOFS bits of the OSCCON2
register, and the HFIOFS and OSTS bits of
the OSCCON register to determine the
current system clock source.
2.11.2 OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<3:0> bits in the CONFIG1H
Configuration register, or from the internal clock
source. In particular, when the primary oscillator is the
source of the primary clock, OSTS indicates that the
Oscillator Start-up Timer (OST) has timed out for LP,
XT or HS modes.

PIC18(L)F2X/4XK22
2.11.3 CLOCK SWITCH TIMING
When switching between one oscillator and another,
the new oscillator may not be operating which saves
power (see Figure 2-9). If this is the case, there is a
delay after the SCS<1:0> bits of the OSCCON
register are modified before the frequency change
takes place. The OSTS and IOFS bits of the
OSCCON register will reflect the current active status
of the external and HFINTOSC oscillators. The timing
of a frequency selection is as follows:
1. SCS<1:0> bits of the OSCCON register are
mod-ified.
2. The old clock continues to operate until the
new clock is ready.
3. Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
ready signal goes true.
4. The system clock is held low starting at the
next falling edge of the old clock.
5. Clock switch circuitry waits for an additional
two rising edges of the new clock.
6. On the next falling edge of the new clock the
low hold on the system clock is released and
new clock is switched in as the system clock.
7. Clock switch is complete.
See Figure 2-1 for more details.
If the HFINTOSC is the source of both the old and
new frequency, there is no start -up delay before the
new frequency is active. This is because the old and
new frequencies are derived from the HFINTOSC via
the postscaler and multiplexer.
Start-up delay specifications are located in
Section 27.0 “Electrical Characteristics”, under AC
Specifications (Oscillator Module).
2.12 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from Sleep,
perform a few instructions using the HFINTOSC as the
clock source and go back to Sleep without waiting for the
primary oscillator to become stable.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
When the oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 2.5.1 “Oscillator Start-up Timer
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up mode
minimizes the delay in code execution by operating from
the internal oscillator as the OST is counting. When the
OST count reaches 1024 and the OSTS bit of the
OSCCON register is set, program execution switches to
the external oscillator.
2.12.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start- up mode is enabled when all of the
following settings are configured as noted:
• Two-Speed Start-up mode is enabled when the
IESO of the CONFIG1H Configuration register
is set.
• SCS<1:0> (of the OSCCON register) = 00.
• FOSC<2:0> bits of the CONFIG1H Configuration
register are configured for LP, XT or HS mode.
Two-Speed Start-up mode becomes active after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
• Wake-up from Sleep.

PIC18(L)F2X/4XK22
2.12.2 TWO-SPEED START-UP
SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin executing by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
3. OST enabled to count 1024 external clock
cycles.
4. OST timed out. External clock is ready.
5. OSTS is set.
6. Clock switch finishes according to Figure 2-9
2.12.3 CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in CONFIG1H Configuration register,
or the internal oscillator. OSTS = 0 when the external
oscillator is not ready, which indicates that the system
is running from the internal oscillator.
FIGURE 2-9: CLOCK SWITCH TIMING
High Speed Low Speed
Old Clock
-up
New Clock
Start Time
(1)
Clock Sync Running
New Clk Ready
IRCF <2:0> Select Old Select New
System Clock

Low Speed High Speed
Old Clock
New Clock
Start-up Time
(1)
Clock Sync Running
New Clk Ready
IRCF <2:0> S elect Old Select New
System Clock
Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode.

PIC18(L)F2X/4XK22
2.13 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
device to continue operating should the external
oscillator fail. The FSCM can detect oscillator failure
any time after the Oscillator Start -up Timer (OST)
has expired. The FSCM is enabled by setting the
FCMEN bit in the CONFIG1H Configuration register.
The FSCM is applicable to all external oscillator
modes (LP, XT, HS, EC, RC and RCIO).
FIGURE 2-10: FSCM BLOCK DIAGRAM
Clock Monitor
External
Latch
S Q
Clock
LFINTOSC
÷ 64 R QOscillator
31 kHz 488 Hz
(~32 µs) (~2 ms)
Sample Clock Clock
Failure
Detected
2.13.1 FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64 (see Figure 2-10). Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of
the sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
primary clock goes low.
2.13.2 FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSCFIF of the PIR2 register. The OSCFIF flag will
generate an interrupt if the OSCFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be sourced
from the internal clock source until the device firmware
successfully restarts the external oscillator and switches
back to external operation. An automatic transition back
to the failed clock source will not occur.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
2.13.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared by either one of the
following:
• Any Reset
• By toggling the SCS1 bit of the OSCCON register
Both of these conditions restart the OST. While the
OST is running, the device continues to operate from
the INTOSC selected in OSCCON. When the OST
times out, the Fail-Safe condition is cleared and the
device automatically switches over to the external
clock source. The Fail-Safe condition need not be
cleared before the OSCFIF flag is cleared.
2.13.4 RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC
or RC Clock modes so that the FSCM will be active
as soon as the Reset or wake-up has completed. .
Note: Due to the wide range of oscillator start-
up times, the Fail-Safe circuit is not
active during oscillator start-up (i.e., after
exiting Reset or Sleep). After an
appropriate amount of time, the user
should check the OSTS bit of the
OSCCON register to verify the oscillator
start-up and that the system clock
switchover has successfully completed.
Note: When the device is configured for Fail-
Safe clock monitoring in either HS, XT,
or LS Oscillator modes then the IESO
config-uration bit should also be set so
that the clock will automatically switch
from the internal clock to the external
oscillator when the OST times out.

FIGURE 2-11: FSCM TIMING DIAGRAM
Sample Clock
System Oscillator
Clock Failure
Output
Clock Monitor Output
(Q)
OSCFIF PIC18(L)F2X/4XK22
Failure
Detected
Test Test Test
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 2-4: REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116
IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129
OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 32
OSCCON2 PLLRDY SOSCRUN — MFIOSEL SOSCGO PRISD MFIOFS LFIOFS 33
OSCTUNE INTSRC PLLEN TUN<5:0> 37
PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125
PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by clock sources.
TABLE 2-5: CONFIGURATION REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
on Page
CONFIG1H IESO FCMEN PRICLKEN PLLCFG FOSC<3:0> 357
CONFIG2L — — — BORV<1:0> BOREN<1:0> PWRTEN 358
CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for clock sources.

PIC18(L)F2X/4XK22
3.0 POWER-MANAGED MODES
PIC18(L)F2X/4XK22 devices offer a total of seven
operating modes for more efficient power manage-
ment. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery-powered
devices).
There are three categories of power-managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device are
clocked and sometimes, what speed. The Run and Idle
modes may use any of the three available clock sources
(primary, secondary or internal oscillator block). The
Sleep mode does not use a clock source.
The power-managed modes include several power-
saving features offered on previous PIC
®
microcontroller
devices. One of the clock switching features allows the
controller to use the secondary oscillator (SOSC) in place
of the primary oscillator. Also included is the Sleep mode,
offered by all PIC
®
microcontroller devices, where all
device clocks are stopped.
3.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions:
• Whether or not the CPU is to be clocked
• The selection of a clock source
The IDLEN bit (OSCCON<7>) controls CPU clocking,
while the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 3-1.
3.1.1 CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the
FOSC<3:0> Configuration bits
• the secondary clock (the SOSC oscillator)
• the internal oscillator block
3.1.2 ENTERING POWER-MANAGED
MODES
Switching from one power -managed mode to another
begins by loading the OSCCON register. The SCS<1:0>
bits select the clock source and determine which Run or
Idle mode is to be used. Changing these bits causes an
immediate switch to the new clock source, assuming that
it is running. The switch may also be subject to clock
transition delays. Refer to
Section 2.11 “Clock Switching” for more information.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 3-1: POWER-MANAGED MODES
Mode
OSCCON Bits Module Clocking
Available Clock and Oscillator Source
IDLEN
(1)
SCS<1:0> CPU Peripherals
Sleep 0 N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, RC, EC and Internal
Oscillator Block
(2)
.
This is the normal full-power execution mode.
SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator
RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block
(2)
PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 1 01 Off Clocked Secondary – SOSC Oscillator
RC_IDLE 1 1x Off Clocked Internal Oscillator Block
(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2:Includes HFINTOSC and HFINTOSC postscaler, as well as the LFINTOSC source.

PIC18(L)F2X/4XK22
3.1.3 MULTIPLE FUNCTIONS OF THE
SLEEP COMMAND
The power-managed mode that is invoked with the
SLEEP instruction is determined by the value of the
IDLEN bit at the time the instruction is executed. If
IDLEN = 0, when SLEEP is executed, the device
enters the Sleep mode and all clocks stop and
minimum power is consumed. If IDLEN = 1, when
SLEEP is executed, the device enters the IDLE mode
and the system clock continues to supply a clock to
the peripherals but is disconnected from the CPU.
3.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
3.2.1 PRI_RUN MODE
The PRI _RUN mode is the normal, full-power
execution mode of the microcontroller. This is also the
default mode upon a device Reset, unless Two-
Speed Start-up is enabled (see Section 2.12 “Two-
Speed Clock Start-up Mode” for details). In this
mode, the device is operated off the oscillator defined
by the FOSC<3:0> bits of the CONFIG1H
Configuration register.
3.2.2 SEC_RUN MODE
In SEC_RUN mode, the CPU and peripherals are
clocked from the secondary external oscillator. This
gives users the option of lower power consumption
while still using a high accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. When SEC_RUN mode is active, all of the
following are true:
• The device clock source is switched to the
SOSC oscillator (see Figure 3-1)
• The primary oscillator is shut down
• The SOSCRUN bit (OSCCON2<6>) is set
• The OSTS bit (OSCCON2<3>) is cleared
Note: The secondary external oscillator should
already be running prior to entering
SEC_RUN mode. If the SOSCGO bit or
any of the TxSOSCEN bits are not set
when the SCS<1:0> bits are set to ‘01’,
entry to SEC_RUN mode will not occur
until SOSCGO bit is set and secondary
external oscillator is ready.
On transitions from SEC_RUN mode to PRI_RUN mode,
the peripherals and CPU continue to be clocked from the
SOSC oscillator, while the primary clock is started. When
the primary clock becomes ready, a clock switch back to
the primary clock occurs (see
Figure 3-2). When the clock switch is complete, the
SOSCRUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up and the
SOSC oscillator continues to run.
3.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are clocked
from the internal oscillator block using the INTOSC
multiplexer. In this mode, the primary clock is shut down.
When using the LFINTOSC source, this mode provides
the best power conservation of all the Run modes, while
still executing code. It works well for user applications
which are not highly timing-sensitive or do not require
high-speed clocks at all times. If the primary clock source
is the internal oscillator block – either LFINTOSC or
INTOSC (MFINTOSC or HFINTOSC) – there are no
distinguishable differences between the PRI_RUN and
RC_RUN modes during execution. Entering or exiting
RC_RUN mode, however, causes a clock switch delay.
Therefore, if the primary clock source is the internal
oscillator block, using RC_RUN mode is not
recommended.
This mode is entered by setting the SCS1 bit to ‘1’. To
maintain software compatibility with future devices, it
is recommended that the SCS0 bit also be cleared,
even though the bit is ignored. When the clock source
is switched to the INTOSC multiplexer (see Figure 3-
1), the primary oscillator is shut down and the OSTS
bit is cleared. The IRCF<2:0> bits (OSCCON<6:4>)
may be modified at any time to immediately change
the clock speed.
When the IRCF bits and the INTSRC bit are all clear,
the INTOSC output (HFINTOSC/MFINTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LFINTOSC source is providing the device
clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC or
MFIOSEL is set, then the HFIOFS or MFIOFS bit is
set after the INTOSC output becomes stable. For
details, see Table 3-2.
Clocks to the device continue while the INTOSC
source stabilizes after an interval of TIOBST.
If the IRCF bits were previously at a non-zero value,
or if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, then the HFIOFS
or MFIOFS bit will remain set.

PIC18(L)F2X/4XK22
On transitions from RC_ RUN mode to PRI_RUN
mode, the device continues to be clocked from the
INTOSC multiplexer while the primary clock is started.
When the primary clock becomes ready, a clock
switch to the pri-mary clock occurs (see Figure 3-3).
When the clock switch is complete, the HFIOFS or
MFIOFS bit is cleared, the OSTS bit is set and the
primary clock is providing the device clock. The
IDLEN and SCS bits are not affected by the switch.
The LFINTOSC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
SOSCI 1 2 3 n-1 n
OSC1 Clock Transition
(1)
CPU
Clock
Peripheral
Clock
Program
PC PC + 2 PC + 4Counter
Note 1: Clock transition typically occurs within 2-4 TOSC.
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
SOSC
OSC1
TOST
(1)
TPLL
(1)
PLL Clock 1 2 n-1 n
Output
Clock
CPU Clock Transition
(2)
Peripheral
Clock
Program
PC PC + 2 PC + 4
Counter
SCS<1:0> bits Changed OSTS bit Set
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.

PIC18(L)F2X/4XK22
TABLE 3-2: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
IRCF<2:0> INTSRC MFIOSEL Selected Oscillator Selected Oscillator Stable when:
000 0 x LFINTOSC LFIOFS = 1
000 1 0 HFINTOSC HFIOFS = 1
000 1 1 MFINTOSC MFIOFS = 1
010 or 001 x 0 HFINTOSC HFIOFS = 1
010 or 001 x 1 MFINTOSC MFIOFS = 1
011 – 111 x x HFINTOSC HFIOFS = 1
FIGURE 3-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC
Multiplexer
OSC1
TOST
(1)
TPLL
(1)
PLL Clock 1 2 n-1 n
Output
Clock
CPU Clock Transition
(2)
Peripheral
Clock
Program
PC PC + 2 PC + 4
Counter
SCS<1:0> bits Changed OSTS bit Set
2: Clock transition typically occurs within 2-4 TOSC.

PIC18(L)F2X/4XK22
3.3 Sleep Mode
The Power-Managed Sleep mode in the PIC18(L)F2X/
4XK22 devices is identical to the legacy Sleep mode
offered in all other PIC
®
microcontroller devices. It is
entered by clearing the IDLEN bit of the OSCCON
register and executing the SLEEP instruction. This shuts
down the selected oscillator (Figure 3-4) and all clock
source Status bits are cleared.
Entering the Sleep mode from either Run or Idle
mode does not require a clock switch. This is because
no clocks are needed once the controller has entered
Sleep. If the WDT is selected, the LFINTOSC source
will continue to operate. If the SOSC oscillator is
enabled, it will also continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 3-5), or it will be clocked
from the internal oscillator block if either the Two-Speed
Start -up or the Fail-Safe Clock Monitor are enabled (see
Section 24.0 “Special Features of the CPU”). In either
case, the OSTS bit is set when the primary clock is
providing the device clocks. The IDLEN and SCS bits are
not affected by the wake-up.
3.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue
to operate. Selecting a particular Idle mode allows
users to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected by the SCS<1:0> bits; however, the CPU
will not be clocked. The clock source status bits are not
affected. Setting IDLEN and executing a SLEEP instruc-
tion provides a quick method of switching from a given
Run mode to its corresponding Idle mode.
If the WDT is selected, the LFINTOSC source will
con-tinue to operate. If the SOSC oscillator is
enabled, it will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt,
WDT time-out, or a Reset. When a wake event
occurs, CPU execution is delayed by an interval of
TCSD while it becomes ready to execute code. When
the CPU begins executing code, it resumes with the
same clock source for the current Idle mode. For
example, when waking from RC_IDLE mode, the
internal oscillator block will clock the CPU and
peripherals (in other words, RC_ RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run
mode currently specified by the SCS<1:0> bits.
FIGURE 3-4: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
PC PC + 2Counter

PIC18(L)F2X/4XK22
FIGURE 3-5: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
PLL Clock TOST
(1)
TPLL
(1)
Output
CPU Clock
Peripheral
Clock
Program
PC PC + 2 PC + 4 PC + 6
Counter
Wake Event OSTS bit set
3.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its
more accurate primary clock source, since the clock
source does not have to “warm-up” or transition from
another oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified by the FOSC<3:0> Configuration bits. The
OSTS bit remains set (see Figure 3-6).
When a wake event occurs, the CPU is clocked from
the primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS
bits are not affected by the wake-up (see Figure 3-7).
3.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP. When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval of
TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the SOSC oscillator. The
IDLEN and SCS bits are not affected by the wake-up; the
SOSC oscillator continues to run (see Figure 3-7).
Note: The SOSC oscillator should already be
running prior to entering SEC_IDLE mode.
At least one of the secondary oscil-lator
enable bits (SOSCGO, T1SOSCEN,
T3SOSCEN or T5SOSCEN) must be set
when the SLEEP instruction is executed.
Otherwise, the main system clock will con-
tinue to operate in the previously selected
mode and the corresponding IDLE mode
will be entered (i.e., PRI_IDLE or
RC_IDLE).
FIGURE 3-6: TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU Clock
Peripheral
Clock
Program
PC PC + 2
Counter

PIC18(L)F2X/4XK22
FIGURE 3-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1
CPU Clock
TCSD
Peripheral
Clock
Program
PC
Counter
Wake Event
3.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the
periph-erals continue to be clocked from the internal
oscillator block from the HFINTOSC multiplexer
output. This mode allows for controllable power
conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
set the SCS1 bit and execute SLEEP. It is
recommended that SCS0 also be cleared, although its
value is ignored, to maintain software compatibility
with future devices. The HFINTOSC multiplexer may
be used to select a higher clock frequency by
modifying the IRCF bits before executing the SLEEP
instruction. When the clock source is switched to the
HFINTOSC multiplexer, the primary oscillator is shut
down and the OSTS bit is cleared.
If the IRCF bits are set to any non-zero value, or either
the INTSRC or MFIOSEL bits are set, the HFINTOSC
output is enabled. Either the HFIOFS or the MFIOFS bits
become set, after the HFINTOSC output stabilizes after
an interval of TIOBST. For information on the HFIOFS and
MFIOFS bits, see Table 3-2.
Clocks to the peripherals continue while the
HFINTOSC source stabilizes. The HFIOFS and
MFIOFS bits will remain set if the IRCF bits were
previously set at a non-zero value or if INTSRC was
set before the SLEEP instruction was executed and
the HFINTOSC source was already stable. If the
IRCF bits and INTSRC are all clear, the HFINTOSC
output will not be enabled, the HFIOFS and MFIOFS
bits will remain clear and there will be no indication of
the current clock source.
When a wake event occurs, the peripherals continue
to be clocked from the HFINTOSC multiplexer output.
After a delay of TCSD following the wake event, the
CPU begins executing code being clocked by the
HFINTOSC multiplexer. The IDLEN and SCS bits are
not affected by the wake-up. The LFINTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.

PIC18(L)F2X/4XK22
3.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by any one of the following:
• an interrupt
• a Reset
• a Watchdog Time-out
This section discusses the triggers that cause exits from
power -managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).
3.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to a
Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one of
the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
The instruction immediately following the SLEEP
instruction is executed on all exits by interrupt from Idle
or Sleep modes. Code execution then branches to the
interrupt vector if the GIE/GIEH bit of the INTCON
register is set, otherwise code execution continues
without branching (see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD following the wake
event is required when leaving Sleep and Idle modes.
This delay is required for the CPU to prepare for
execution. Instruction execution resumes on the first
clock cycle following this delay.
3.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions
depending on which power-managed mode the
device is in when the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from
the power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the
device is executing code (all Run modes), the time-
out will result in a WDT Reset (see Section 24.3
“Watchdog Timer (WDT)”).
The WDT timer and postscaler are cleared by any
one of the following:
• executing a SLEEP instruction
• executing a CLRWDT instruction
• the loss of the currently selected clock source
when the Fail-Safe Clock Monitor is enabled
• modifying the IRCF bits in the OSCCON
register when the internal oscillator block is the
device clock source
3.5.3 EXIT BY RESET
Exiting Sleep and Idle modes by Reset causes code
execution to restart at address 0. See Section 4.0
“Reset” for more details.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator.
3.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock
source is not stopped and
• the primary clock source is not any of the LP,
XT, HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start- up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval TCSD following the wake event is still required
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution
resumes on the first clock cycle following this delay.

PIC18(L)F2X/4XK22
3.6 Selective Peripheral Module
Control
Idle mode allows users to substantially reduce power
consumption by stopping the CPU clock. Even so,
peripheral modules still remain clocked, and thus, con-
sume power. There may be cases where the applica-tion
needs what IDLE mode does not provide: the allocation
of power resources to the CPU processing with minimal
power consumption from the peripherals.
PIC18(L)F2X/4XK22 family devices address this
requirement by allowing peripheral modules to be
selectively disabled, reducing or eliminating their power
consumption. This can be done with control bits in the
Peripheral Module Disable (PMD) registers. These bits
generically named XXXMD are located in control
registers PMD0, PMD1 or PMD2.
Setting the PMD bit for a module disables all clock
sources to that module, reducing its power
consumption to an absolute minimum. In this state,
power to the control and status registers associated
with the peripheral is removed. Writes to these
registers have no effect and read values are invalid.
Clearing a set PMD bit restores power to the
associated control and status registers, thereby
setting those registers to their default values.
3.7 Register Definitions: Peripheral Module Disable
REGISTER 3-1: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD
bit 7 bit 0
Legend:
bit 7 UART2MD: UART2 Peripheral Module Disable Control bit
1 = Module is disabled, Clock Source is disconnected, module does not draw digital power
0 = Module is enabled, Clock Source is connected, module draws digital power
bit 6 UART1MD: UART1 Peripheral Module Disable Control bit
bit 5 TMR6MD: Timer6 Peripheral Module Disable Control bit
1 = Module is disabled, Clock Source is disconnected, module does not draw digital
power 0 = Module is enabled, Clock Source is connected, module draws digital power

PIC18(L)F2X/4XK22
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD
bit 7 bit 0
Legend:
bit 7 MSSP2MD: MSSP2 Peripheral Module Disable Control bit
bit 6 MSSP1MD: MSSP1 Peripheral Module Disable Control bit
bit 5 Unimplemented: Read as ‘0’
bit 4 CCP5MD: CCP5 Peripheral Module Disable Control bit

PIC18(L)F2X/4XK22
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CTMUMD CMP2MD CMP1MD ADCMD
bit 7 bit 0
Legend:
bit 7-4 Unimplemented: Read as ‘0’
bit 3 CTMUMD: CTMU Peripheral Module Disable Control bit
bit 2 CMP2MD: Comparator C2 Peripheral Module Disable Control bit
bit 1 CMP1MD: Comparator C1 Peripheral Module Disable Control bit
bit 0 ADCMD: ADC Peripheral Module Disable Control bit

PIC18(L)F2X/4XK22
4.0 RESET
The PIC18(L)F2X/4XK22 devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset
(during execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR, POR
and BOR and covers the operation of the various start-up
timers. Stack Reset events are covered in
Section 5.2.0.1 “Stack Full and Underflow
Resets”. WDT Resets are covered in Section 24.3
“Watchdog Timer (WDT)”.
A simplified block diagram of the On-Chip Reset
Circuit is shown in Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1) . The lower five bits of the register
indicate that a specific Reset event has occurred. In most
cases, these bits can only be cleared by the event and
must be set by the application after the event. The state
of these flag bits, taken together, can be read to indicate
the type of Reset that just occurred. This is described in
more detail in
Section 4.7 “Reset State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in Section
4.5 “Brown-out Reset (BOR)”.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack Stack Full/Underflow Reset
Pointer
External Reset
MCLR MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD POR
Detect
VDD
Brown-out
Reset BOREN S
OST/PWRT
OST
(2)
1024 Cycles
10-bit Ripple Counter R
Chip_Reset
Q
OSC1
32 µs PWRT
(2)
65.5 ms
LFINTOSC 11-bit Ripple Counter
Enable PWRT
Enable OST
(1)

Note 1: See Table 4-2 for time-out situations.
2: PWRT and OST counters are reset by POR and BOR. See Sections 4.4 and 4.5.

PIC18(L)F2X/4XK22
4.2 Register Definitions: Reset Control
REGISTER 4-1: RCON: RESET CONTROL REGISTER
R/W-0/0 R/W-q/u U-0 R/W-1/q R-1/q R-1/q R/W-q/u R/W-0/q
IPEN SBOREN
(1)
— RI TO PD POR (2) BOR
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown u = unchanged q = depends on condition
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit
(1)
If BOREN<1:0> = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN<1:0> = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware or Power-on Reset)
0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a
code-executed Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
bit 2
0 = A WDT time-out occurred
PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
(2)
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
(3)
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs)
Note 1: When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’.
2:The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 4.7 “Reset State of Registers” for additional information.
3:See Table 4-1.
Note 1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were
set to ‘1’ by firmware immediately after POR).
2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that
subsequent Power-on Resets may be detected.

PIC18(L)F2X/4XK22
4.3 Master Clear (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter
in the MCLR Reset path which detects and ignores
small pulses. An internal weak pull-up is enabled
when the pin is configured as the MCLR input.
The MCLR pin is not driven low by any internal
Resets, including the WDT.
In PIC18(L)F2X/4XK22 devices, the MCLR input can be
disabled with the MCLRE Configuration bit. When MCLR
is disabled, the pin becomes a digital input. See
Section 10.6 “PORTE Registers” for more
information.
4.4 Power-on Reset (POR)
A Power -on Reset pulse is generated on -chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of t he POR circuitry either leave
the pin floating, or tie the MCLR pin through a resistor
to VDD. This will eliminate external RC components
usually needed to create a Power-on Reset delay. A
minimum rise rate for VDD is specified. For a slow rise
time, see Figure 4-2.
When the device starts normal operation (i.e., exits
the Reset condition), device operating parameters
(volt-age, frequency, temperature, etc.) must be met
to ensure proper operation. If these conditions are not
met, the device must be held in Reset until the operat-
ing conditions are met.
POR events are captured by the POR bit of the RCON
register. The state of the bit is set to ‘0’ whenever a POR
occurs; it does not change for any other Reset event.
POR is not reset to ‘1’ by any hardware event. To
capture multiple events, the user must manually set the
bit to ‘1’ by software following any POR.
FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD VDD
PIC
®
MCU
D
R
R1
MCLR
C
Note 1: External Power -on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: 15 kΩ < R < 40 kΩ is recommended to make
sure that the voltage drop across R does not
violate the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the
event of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).

PIC18(L)F2X/4XK22
4.5 Brown-out Reset (BOR)
PIC18(L)F2X/4XK22 devices implement a BOR circuit
that provides the user with a number of configuration and
power-saving options. The BOR is controlled by the
BORV<1:0> and BOREN<1:0> bits of the CONFIG2L
Configuration register. There are a total of four BOR
configurations which are summarized in Table 4-1.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of VDD below VBOR for greater than
TBOR will reset the device. A Reset may or may not
occur if VDD falls below VBOR for less than TBOR. The
chip will remain in Brown-out Reset until VDD rises
above VBOR.
If the Power-up Timer is enabled, it will be invoked
after VDD rises above VBOR; it then will keep the chip
in Reset for an additional time delay, TPWRT. If VDD
drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power -up Timer will be initialized. Once VDD
rises above VBOR, the Power-up Timer will execute
the additional time delay.
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
The BOR circuit has an output that feeds into the POR
circuit and rearms the POR within the operating range of
the BOR. This early rearming of the POR ensures that
the device will remain in Reset in the event that VDD falls
below the operating range of the BOR circuitry.
4.5.1 DETECTING BOR
When BOR is enabled, the BOR bit always resets to
‘0’ on any BOR or POR event. This makes it difficult
to determine if a BO R event has occurred just by
reading the state of BOR alone. A more reliable
method is to simultaneously check t he state of both
POR and BOR. This assumes that the POR and BOR
bits are reset to ‘1’ by software imme diately after any
POR event. If BOR is ‘0’ while POR is ‘1’, it can be
reliably assumed that a BOR event has occurred.
4.5.2 SOFTWARE ENABLED BOR
When BOREN<1:0> = 01, the BOR can be enabled
or disabled by the user in software. This is done with
the SBOREN control bit of the RCON register. Setting
SBOREN enables the BOR to function as previously
described. Clearing SBOREN disables the BOR
entirely. The SBOREN bit operates only in this mode;
otherwise it is read as ‘0’.
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to the
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by
eliminating the incremental current that the BOR
consumes. While the BOR current is typically very small,
it may have some impact in low-power applications.
Note: Even when BOR is under software
control, the BOR Reset voltage level is
still set by the BORV<1:0> Configuration
bits. It cannot be changed by software.
4.5.3 DISABLING BOR IN SLEEP MODE
When BOREN<1:0> = 10, the BOR remains under
hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When
the device returns to any other operating mode, BOR
is automatically re-enabled.
This mode allows for applications to recover from brown-
out situations, while actively executing code, when the
device requires BOR protection the most. At the same
time, it saves additional power in Sleep mode by
eliminating the small incremental BOR current.
4.5.4 MINIMUM BOR ENABLE TIME
Enabling the BOR also enables the Fixed Voltage
Reference (FVR) when no other peripheral requiring the
FVR is active. The BOR becomes active only after the
FVR stabilizes. Therefore, to ensure BOR protection, the
FVR settling time must be considered when enabling the
BOR in software or when the BOR is automatically
enabled after waking from Sleep. If the BOR is disabled,
in software or by reentering Sleep before the FVR
stabilizes, the BOR circuit will not sense a BOR
condition. The FVRST bit of the VREFCON0 register can
be used to determine FVR stability.

PIC18(L)F2X/4XK22
TABLE 4-1: BOR CONFIGURATIONS
BOR Configuration Status of
SBOREN BOR Operation
BOREN1 BOREN0 (RCON<6>)
0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
0 1 Available BOR enabled by software; operation controlled by SBOREN.
1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode.
1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits.
4.6 Device Reset Timers
PIC18(L)F2X/4XK22 devices incorporate three
separate on-chip timers that help regulate the Power-
on Reset process. Their main function is to ensure
that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.6.1 POWER-UP TIMER (PWRT)
The Power- up Timer (PWRT) of PIC18(L)F2X/4XK22
devices is an 11-bit counter which uses the
LFINTOSC source as the clock input. This yields an
approximate time interval of 2048 x 32 µs = 65.6 ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the LFINTOSC
clock and will vary from chip-to-chip due to
temperature and process variation.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
4.6.2 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or on exit from all
power-managed modes that stop the external oscillator.
4.6.3 PLL LOCK TIME-OUT
With the PLL enabled, the time-out sequence following a
Power-on Reset is slightly different from other oscillator
modes. A separate timer is used to provide a fixed time-
out that is sufficient for the PLL to lock to the main
oscillator frequency. This PLL lock time-out (TPLL) is
typically 2 ms and follows the oscillator start-up time-out.
4.6.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT time-
out is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator
configuration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4- 7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire, after
which, bringing MCLR high will allow program execution
to begin immediately (Figure 4-5). This is useful for
testing purposes or to synchronize more than one PIC
®
MCU device operating in parallel.

PIC18(L)F2X/4XK22
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Power-up
(2)
and Brown-out Exit from
Configuration PWRTEN = 0 PWRTEN = 1 Power-Managed Mode
HSPLL 66 ms
(1)
+ 1024 TOSC + 2 1024 TOSC + 2 ms
(2)
1024 TOSC + 2 ms
(2)
ms(2)
HS, XT, LP 66 ms
(1)
+ 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms
(1)
— —
RC, RCIO 66 ms
(1)
— —
INTIO1, INTIO2 66 ms
(1)
— —
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET

PIC18(L)F2X/4XK22
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V
VDD 0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET

PIC18(L)F2X/4XK22
FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT TPLL
PLL TIME-OUT
INTERNAL RESET
Note: TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.

PIC18(L)F2X/4XK22
4.7 Reset State of Registers
Some registers are unaffected by a Reset. Their
status is unknown on POR and unchanged by all
other Resets. All other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-3.
These bits are used by software to determine the
nature of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. The table identifies
differences between Power-On Reset (POR)/Brown-
Out Reset (BOR) and all other Resets, (i.e., Master
Clear, WDT Resets, STKFUL, STKUNF, etc.).
Additionally, the table identifies register bits that are
changed when the device receives a wake-up from
WDT or other interrupts.
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition Program
RCON Register STKPTR Register
Counter SBOREN RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 1 1 1 0 0 0 0
RESET Instruction 0000h u(2) 0 u u u u u u
Brown-out Reset 0000h u(2) 1 1 1 u 0 u u
during Power-Managed 0000h u(2) u 1 u u u u uMCLR
Run Modes
during Power-Managed 0000h u(2) u 1 0 u u u uMCLR
Idle Modes and Sleep Mode
WDT Time-out during Full Power 0000h u(2) u 0 u u u u u
or Power-Managed Run Mode
during Full Power 0000h u(2) u u u u u u uMCLR
Execution
Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u
Stack Underflow Reset 0000h u(2) u u u u u u 1
(STVREN = 1)
Stack Underflow Error (not an 0000h u(2) u u u u u u 1
actual Reset, STVREN = 0)
WDT Time-out during Power- PC + 2 u(2) u 0 0 u u u u
Managed Idle or Sleep Modes
Interrupt Exit from Power- PC + 2
(1)
u(2) u u 0 u u u u
Managed Modes
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2:Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled
(BOREN<1:0> Configuration bits = 01). Otherwise, the Reset state is ‘0’.
TABLE 4-4: REGISTERS ASSOCIATED WITH RESETS
Register
on Page
RCON IPEN SBOREN — 60RI TO PD POR BOR
STKPTR STKFUL STKUNF — STKPTR<4:0> 72
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.

PIC18(L)F2X/4XK22
TABLE 4-5: CONFIGURATION REGISTERS ASSOCIATED WITH RESETS
Register
on Page
CONFIG2L — — — BORV<1:0> BOREN<1:0> PWRTEN 358
CONFIG2H — — WDPS<3:0> WDTEN<1:0> 359
CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 360
CONFIG4L DEBUG XINST — — — LVP — STRVEN 361
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.

PIC18(L)F2X/4XK22
5.0 MEMORY ORGANIZATION
There are three types of memory in PIC18 Enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and
program memories use separate buses; this allows
for concurrent access of the two memory spaces. The
data EEPROM, for practical purposes, can be
regarded as a peripheral device, since it is addressed
and accessed through a set of control registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 7.0 “Data EEPROM
Memory”.
5.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location
between the upper boundary of the physically
implemented memory and the 2-Mbyte address will
return all ‘0’s (a NOP instruction).
This family of devices contain the following:
• PIC18(L)F23K22, PIC18(L)F43K22: 8 Kbytes of
Flash Memory, up to 4,096 single-word instructions
• PIC18(L)F24K22, PIC18(L)F44K22: 16 Kbytes of
Flash Memory, up to 8,192 single-word instructions
• PIC18(L)F25K22, PIC18(L)F45K22: 32 Kbytes
of Flash Memory, up to 16,384 single-word
instruc-tions
• PIC18(L)F26K22, PIC18(L)F46K22: 64 Kbytes
of Flash Memory, up to 37,768 single-word
instructions
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory map for PIC18(L)F2X/4XK22
devices is shown in Figure 5-1. Memory block details
are shown in Figure 20-2.

PIC18(L)F2X/4XK22
FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/4XK22 DEVICES
PC<20:0>
21CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
•
•
•
Stack Level 31
Reset Vector 0000h
High Priority Interrupt Vector 0008h
Low Priority Interrupt Vector 0018h
On-Chip
Program Memory
On-Chip1FFFh
2000h
Program Memory
3FFFh
On-Chip
PIC18(L)F23K22 Program Memory
4000h
PIC18(L)F43K22
Space
PIC18(L)F24K22
On-Chip
Program Memory
PIC18(L)F44K22
7FFFh
Memory
8000h
PIC18(L)F25K22
User
PIC18(L)F45K22
FFFFh
Read ‘0’ Read ‘0’ Read ‘0’
10000h
PIC18(L)F26K22
PIC18(L)F46K22
Read ‘0’ 1FFFFFh
200000h
5.1.1 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8- bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains the
PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU register
are performed through the PCLATU register.
The contents of PCLATH and PCLATU are
transferred to the program counter by any operation
that writes PCL. Similarly, the upper two bytes of the
program counter are transferred to PCLATH and
PCLATU by an operation that reads PCL. This is
useful for computed offsets to the PC (see Section
5.2.2.1 “Computed GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by two to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2 RETURN ADDRESS STACK
The return address stack allows any combination of
up to 31 program calls and interrupts to occur. The
PC is pushed onto the stack when a CALL or RCALL
instruction is executed or an interrupt is
Acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction.
PCLATU and PCLATH are not affected by any of the
RETURN or CALL instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack
Pointer is readable and writable and the address on
the top of the stack is readable and writable through
the Top-of-Stack (TOS) Special File Registers. Data
can also be pushed to, or popped from the stack,
using these registers.

PIC18(L)F2X/4XK22
A CALL type instruction causes a push onto the stack;
the Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction
causes a pop from the stack; the contents of the
location pointed to by the STKPTR are transferred to
the PC and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘ 00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’;
this is only a Reset value. Status bits indicate if the
stack is full or has overflowed or has underflowed.
5.1.2.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is readable
and writable. A set of three registers, TOSU:TOSH:TOSL,
hold the contents of the stack location pointed to by the
STKPTR register (Figure 5-2). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed value
by reading the TOSU:TOSH:TOSL registers. These values
can be placed on a user defined software stack. At return
time, the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the Global Interrupt Enable
(GIE) bits while accessing the stack to prevent
inadvertent stack corruption.
FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0>
11111
Top-of-Stack Registers
11110
Stack Pointer11101
TOSU TOSH TOSL STKPTR<4:0>
00h 1Ah 34h
00011
00010
Top-of-Stack 00010001A34h
000D58h 00001
00000
5.1.2.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1 ) contains the Stack
Pointer value, the STKFUL (stack full) Status bit and the
STKUNF (Stack Underflow) Status bits. The value of the
Stack Pointer can be 0 through 31. The Stack Pointer
increments before values are pushed onto the stack and
decrements after values are popped off the stack. On
Reset, the Stack Pointer value will be zero. The user may
read and write the Stack Pointer value. This feature can
be used by a Real-Time Operating System (RTOS) for
return stack maintenance.
After the PC is pushed onto the stack 31 times
(without popping any values off the stack), the
STKFUL bit is set. The STKFUL bit is cleared by
software or by a POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) Configuration bit. (Refer to
Section 24.1 “Configuration Bits” for a description
of the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on
the 31st push and the Stack Pointer will increment to
31. Any additional pushes will not overwrite the 31
st
push and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain set
until cleared by software or until a POR occurs.
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.

PIC18(L)F2X/4XK22
5.1.2.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution is
a desirable feature. The PIC18 instruction set includes
two instructions, PUSH and POP, that permit the TOS to
be manipulated under software control. TOSU, TOSH
and TOSL can be modified to place data or a return
address on the stack.
The PUSH instruction places the current PC value
onto the stack. This increments the Stack Pointer and
loads the current PC value onto the stack.
The POP instruction discards the current TOS by
decre-menting the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
5.2 Register Definitions: Stack Pointer
REGISTER 5-1: STKPTR: STACK POINTER REGISTER
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL
(1)
STKUNF
(1)
— STKPTR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
bit 7 STKFUL: Stack Full Flag bit
(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit
(1)
1 = Stack Underflow occurred
0 = Stack Underflow did not occur
bit 4-0 STKPTR<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
5.2.0.1 Stack Full and Underflow Resets
Device Resets on Stack Overflow and Stack Underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full or
underflow will set the appropriate STKFUL or STKUNF
bit and then cause a device Reset. When STVREN is
cleared, a full or underflow condition will set the
appropriate STKFUL or STKUNF bit but not cause a
device Reset. The STKFUL or STKUNF bits are cleared
by the user software or a Power-on Reset.
5.2.1 FAST REGISTER STACK
A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All inter-
rupt sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from low
priority interrupts. If a high priority interrupt occurs while
servicing a low priority interrupt, the stack register values
stored by the low priority interrupt will be overwritten. In
these cases, users must save the key registers by
software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use
the fast register stack for returns from interrupt. If no
interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the Status,
WREG and BSR registers to the fast register stack. A
RETURN, FAST instruction is then executed to restore
these registers from the fast register stack.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.

PIC18(L)F2X/4XK22
EXAMPLE 5-1: FAST REGISTER STACK
CODE EXAMPLE
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
•
;STACK
•
SUB1•
•
;RESTORE VALUES SAVEDRETURN, FAST
;IN FAST REGISTER STACK
5.2.2 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.2.2.1 Computed GOTO
A computed GOTO is accomplished by adding an
offset to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table
before executing a call to that table. The first
instruction of the called routine is the ADDWF PCL
instruction. The next instruction executed will be one
of the RETLW nn instructions that returns the value
‘nn’ to the calling function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of two (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-2: COMPUTED GOTO USING AN
OFFSET VALUE
MOVF OFFSET, W
ORG
CALL TABLE
nn00h
PCLTABLE ADDWF
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
5.2.2.2 Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each
instruction location.
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
contains the data that is read from or written to
program memory. Data is transferred to or from
program memory one byte at a time.
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.

PIC18(L)F2X/4XK22
5.3 PIC18 Instruction Cycle
5.3.1 CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter
is incremented on every Q1; the instruction is fetched
from the program memory and latched into the
instruction register during Q4. The instruction is
decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 5-3.
5.3.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 5-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3 and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 5-3: CLOCK/INSTRUCTION CYCLE
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Internal
Q3 Phase
Q4
Clock
PC PC PC + 2 PC + 4
OSC2/CLKOUT
(RC mode)
Execute INST (PC – 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

PIC18(L)F2X/4XK22
5.3.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes.
Instructions are stored as either two bytes or four
bytes in program memory. The Least Significant Byte
of an instruction word is always stored in a program
memory location with an even address (LSb = 0). To
maintain alignment with instruction boundaries, the
PC increments in steps of two and the LSb will always
read ‘0’ (see Section 5.1.1 “Program Counter”).
Figure 5-4 shows an example of how instruction
words are stored in the program memory.
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction.
Since instructions are always stored on word boundaries,
the data contained in the instruction is a word address.
The word address is written to PC<20:1>, which
accesses the desired byte address in program memory.
Instruction #2 in Figure 5-4 shows how the instruction
GOTO 0006h is encoded in the program memory.
Program branch instructions, which encode a relative
address offset, operate in the same manner. The offset
value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 25.0 “Instruction Set Summary”
provides further details of the instruction set.
FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1 LSB = 0
Word Address
Program Memory
↓
000000h
Byte Locations → 000002h
000004h
Instruction 1: MOVLW 055h
000006h
0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
Instruction 3: MOVFF 123h, 456h
F0h 00h 00000Ch
C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
5.3.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instruction always has
‘1111’ as its four Most Significant bits; the other 12
bits are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
EXAMPLE 5-4: TWO-WORD INSTRUCTIONS
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
Note: See Section 5.8 “PIC18 Instruction
Execution and the Extended Instruc-tion
Set” for information on two-word
instructions in the extended instruction set.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18(L)F2X/4XK22
5.4 Data Memory Organization
Note: The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.7 “Data Memory and the
Extended Instruction Set” for more
information.
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many
as 16 banks that contain 256 bytes each. Figures 5-5
through 5-7 show the data memory organization for
the PIC18(L)F2X/4XK22 devices.
The data memory contains Special Function
Registers (SFRs) and General Purpose Registers
(GPRs). The SFRs are used for control and status of
the controller and peripheral functions, while GPRs
are used for data storage and scratchpad operations
in the user’s application. Any read of an
unimplemented location will read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256- byte
memory space that provides fast access to SFRs and the
lower portion of GPR Bank 0 without using the Bank
Select Register (BSR). Section 5.4.2 “Access Bank”
provides a detailed description of the Access RAM.
5.4.1 BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read
or write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make
use of the Bank Pointer, known as the Bank Select
Register (BSR). This SFR holds the 4 Most Significant
bits of a location’s address; the instruction itself
includes the 8 Least Significant bits. Only the four
lower bits of the BSR are implemented (BSR<3:0>).
The upper four bits are unused; they will always read
‘0’ and cannot be written to. The BSR can be loaded
directly by using the MOVLB instruction.
The value of the BSR indicates the bank in data memory;
the eight bits in the instruction show the location in the
bank and can be thought of as an offset from the bank’s
lower boundary. The relationship between the BSR’s
value and the bank division in data memory is shown in
Figures 5-5 through 5-7.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR is
0Fh will end up resetting the program counter.
While any bank can be selected, only those banks
that are actually implemented can be read or written
to. Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s.
Even so, the STATUS register will still be affected as
if the operation was successful. The data memory
maps in Figures 5-5 through 5-7 indicate which banks
are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores
the BSR completely when it executes. All other
instructions include only the low-order address as an
operand and must use either the BSR or the Access
Bank to locate their target registers.

PIC18(L)F2X/4XK22
FIGURE 5-5: DATA MEMORY MAP FOR PIC18(L)F23K22 AND PIC18(L)F43K22 DEVICES
BSR<3:0>
=0000
=0001
=0010
=0011
=0100
=0101
=0110
=0111
=1000
=1001
=1010
=1011
=1100
=1101
=1110
= 1111
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Data Memory Map
000h
Access RAM 05Fh
060h
GPR 0FFh
100h
GPR
1FFh
200h
2FFh
300h
3FFh
400h
4FFh
500h
5FFh
600h
6FFh
700h
7FFh
800h
Unused
8FFh
900h
Read 00h
9FFh
A00h
AFFh
B00h
BFFh
C00h
CFFh
D00h
DFFh
E00h
EFFh
F00h
Unused F37h
F38h
SFR
(1)
F5Fh
SFR
F60h
FFFh
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose
RAM (from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR specifies the Bank
used by the instruction.
Access Bank
00h
Access RAM Low 5Fh
60hAccess RAM High
(SFRs) FFh
Note 1: Addresses F38h through F5Fh are
also used by SFRs, but are not
part of the Access RAM. Users
must always use the complete
address or load the proper BSR
value to access these registers.

PIC18(L)F2X/4XK22
BSR<3:0>
=0000
=0001
=0010
=0011
=0100
=0101
=0110
=0111
=1000
=1001
=1010
=1011
=1100
=1101
=1110
= 1111
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
Data Memory Map
00h
000h
Access RAM 05Fh
060h
FFh GPR 0FFh
00h 100h
GPR
FFh 1FFh
00h
GPR
200h
FFh 2FFh
00h 300h
FFh 3FFh
00h 400h
FFh 4FFh
00h 500h
FFh 5FFh
00h 600h
FFh 6FFh
00h 700h
FFh 7FFh
00h 800h
FFh
Unused
8FFh
00h 900h
Read 00h
FFh 9FFh
00h A00h
FFh AFFh
00h B00h
FFh BFFh
00h C00h
FFh
CFFh
D00h
00h
FFh DFFh
E00h00h
FFh EFFh
00h Unused F00h
F37h
SFR
(1) F38h
F5Fh
F60h
SFR
FFh FFFh
When ‘a’ = 0:
general purpose
RAM (from Bank 0).
(from Bank 15).
When ‘a’ = 1:
Access Bank
00h
Access RAM Low 5Fh
60hAccess RAM High
(SFRs) FFh

PIC18(L)F2X/4XK22
BSR<3:0>
=0000
=0001
=0010
=0011
=0100
=0101
=0110
=0111
=1000
=1001
=1010
=1011
=1100
=1101
=1110
= 1111
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
Data Memory Map
00h
000h
Access RAM 05Fh
060h
FFh GPR 0FFh
00h 100h
GPR
FFh 1FFh
00h
GPR
200h
FFh 2FFh
00h 300h
GPR
FFh 3FFh
00h 400h
GPR
4FFhFFh
00h 500h
GPR
5FFhFFh
00h 600h
FFh 6FFh
00h 700h
FFh 7FFh
00h 800h
FFh 8FFh
00h 900h
FFh 9FFh
00h Unused A00h
FFh
Read 00h
AFFh
00h B00h
FFh BFFh
00h C00h
FFh
CFFh
D00h
00h
FFh DFFh
E00h00h
FFh EFFh
00h
Unused
F00h
F37h
F38hSFR
(1)
F5Fh
SFR
F60h
FFh FFFh
When ‘a’ = 0:
general purpose
RAM (from Bank 0).
(from Bank 15).
When ‘a’ = 1:
Access Bank
00h
Access RAM Low 5Fh
60hAccess RAM High
(SFRs) FFh

PIC18(L)F2X/4XK22
BSR<3:0>
=0000
=0001
=0010
=0011
=0100
=0101
=0110
=0111
=1000
=1001
=1010
=1011
=1100
=1101
=1110
= 1111
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
Data Memory Map
00h
000h
Access RAM 05Fh
060h
FFh GPR 0FFh
00h 100h
GPR
FFh 1FFh
00h
GPR
200h
FFh 2FFh
00h 300h
GPR
FFh 3FFh
00h 400h
GPR
4FFhFFh
00h 500h
GPR
5FFhFFh
00h
GPR
600h
FFh 6FFh
00h
GPR
700h
FFh 7FFh
00h 800h
GPR
FFh 8FFh
00h
GPR
900h
FFh 9FFh
00h
GPR
A00h
AFFhFFh
00h
GPR
B00h
FFh BFFh
00h
GPR
C00h
FFh
CFFh
D00h
00h
GPR
FFh DFFh
E00h00h
GPR
FFh
F00h00h
GPR F37h
F38hSFR(1)
F5Fh
SFR
F60h
FFh FFFh
When ‘a’ = 0:
general purpose
RAM (from Bank 0).
(from Bank 15).
When ‘a’ = 1:
Access Bank
00h
Access RAM Low 5Fh
60hAccess RAM High
(SFRs) FFh

PIC18(L)F2X/4XK22
FIGURE 5-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
7
BSR(1)
0 000h
Data Memory
7
From Opcode
(2)
00h 0
Bank 00 0 0 0 0 0 1 1
100h
FFh 1 1 1 1 1 1 1 1
00h
Bank 1
Bank Select
(2)
200h
FFh
Bank 2 00h
300h FFh
00h
Bank 3
through
Bank 13
E00h
FFh
00h
Bank 14
F00h
FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

PIC18(L)F2X/4XK22
5.4.2 ACCESS BANK
While the use of the BSR with an embedded 8- bit
address allows users to address the entire range of data
memory, it also means that the user must always ensure
that the correct bank is selected. Otherwise, data may be
read from or written to the wrong location. This can be
disastrous if a GPR is the intended target of an
operation, but an SFR is written to instead. Verifying
and/or changing the BSR for each read or write to data
memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with an
Access Bank, which allows users to access a mapped
block of memory without specifying a BSR. The Access
Bank consists of the first 96 bytes of mem-ory (00h-5Fh)
in Bank 0 and the last 160 bytes of mem-ory (60h-FFh) in
Block 15. The lower half is known as the “Access RAM”
and is composed of GPRs. This upper half is also where
the device’s SFRs are mapped. These two areas are
mapped contiguously in the Access Bank and can be
addressed in a linear fashion by an 8-bit address
(Figures 5-5 through 5-7).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction) . When ‘a’ is equal to ‘1’, the
instruction uses the BSR and the 8-bit address
included in the opcode for the data memory address.
When ‘a’ is ‘0’, however, the instruction is forced to
use the Access Bank address map; the current value
of the BSR is ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and
operate on SFRs more efficiently. The Access RAM
below 60h is a good place for data values that the
user might need to access rapidly, such as immediate
computational results or common program variables.
Access RAM also allows for faster and more code
efficient context saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.7.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.4.3 GENERAL PURPOSE REGISTER
FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by
all instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a Power-
on Reset and are unchanged on all other Resets.
5.4.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of data
memory (FFFh) and extend downward to occupy the top
portion of Bank 15 (F38h to FFFh). A list of these
registers is given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused
SFR locations are unimplemented and read as ‘0’s.

PIC18(L)F2X/4XK22
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F2X/4XK22 DEVICES
Address Name Address Name Address Name Address Name Address Name
FFFh TOSU FD7h TMR0H FAFh SPBRG1 F87h —(2) F5Fh CCPR3H
FFEh TOSH FD6h TMR0L FAEh RCREG1 F86h —(2) F5Eh CCPR3L
FFDh TOSL FD5h T0CON FADh TXREG1 F85h —(2) F5Dh CCP3CON
FFCh STKPTR FD4h —(2) FACh TXSTA1 F84h PORTE F5Ch PWM3CON
FFBh PCLATU FD3h OSCCON FABh RCSTA1 F83h PORTD
(3)
F5Bh ECCP3AS
FFAh PCLATH FD2h OSCCON2 FAAh EEADRH
(4)
F82h PORTC F5Ah PSTR3CON
FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB F59h CCPR4H
FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h CCPR4L
FF7h TBLPTRH FCFh TMR1H FA7h EECON2
(1)
F7Fh IPR5 F57h CCP4CON
FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh PIR5 F56h CCPR5H
FF5h TABLAT FCDh T1CON FA5h IPR3 F7Dh PIE5 F55h CCPR5L
FF4h PRODH FCCh T1GCON FA4h PIR3 F7Ch IPR4 F54h CCP5CON
FF3h PRODL FCBh SSP1CON3 FA3h PIE3 F7Bh PIR4 F53h TMR4
FF2h INTCON FCAh SSP1MSK FA2h IPR2 F7Ah PIE4 F52h PR4
FF1h INTCON2 FC9h SSP1BUF FA1h PIR2 F79h CM1CON0 F51h T4CON
FF0h INTCON3 FC8h SSP1ADD FA0h PIE2 F78h CM2CON0 F50h TMR5H
FEFh INDF0
(1)
FC7h SSP1STAT F9Fh IPR1 F77h CM2CON1 F4Fh TMR5L
FEEh POSTINC0
(1)
FC6h SSP1CON1 F9Eh PIR1 F76h SPBRGH2 F4Eh T5CON
FEDh POSTDEC0
(1)
FC5h SSP1CON2 F9Dh PIE1 F75h SPBRG2 F4Dh T5GCON
FECh PREINC0
(1)
FC4h ADRESH F9Ch HLVDCON F74h RCREG2 F4Ch TMR6
FEBh PLUSW0
(1)
FC3h ADRESL F9Bh OSCTUNE F73h TXREG2 F4Bh PR6
FEAh FSR0H FC2h ADCON0 F9Ah —(2) F72h TXSTA2 F4Ah T6CON
FE9h FSR0L FC1h ADCON1 F99h —(2) F71h RCSTA2 F49h CCPTMRS0
FE8h WREG FC0h ADCON2 F98h —(2) F70h BAUDCON2 F48h CCPTMRS1
FE7h INDF1
(1)
FBFh CCPR1H F97h —(2) F6Fh SSP2BUF F47h SRCON0
FE6h POSTINC1
(1)
FBEh CCPR1L F96h TRISE F6Eh SSP2ADD F46h SRCON1
FE5h POSTDEC1
(1)
FBDh CCP1CON F95h TRISD
(3)
F6Dh SSP2STAT F45h CTMUCONH
FE4h PREINC1
(1)
FBCh TMR2 F94h TRISC F6Ch SSP2CON1 F44h CTMUCONL
FE3h PLUSW1
(1)
FBBh PR2 F93h TRISB F6Bh SSP2CON2 F43h CTMUICON
FE2h FSR1H FBAh T2CON F92h TRISA F6Ah SSP2MSK F42h VREFCON0
FE1h FSR1L FB9h PSTR1CON F91h —(2) F69h SSP2CON3 F41h VREFCON1
FE0h BSR FB8h BAUDCON1 F90h —(2) F68h CCPR2H F40h VREFCON2
FDFh INDF2
(1)
FB7h PWM1CON F8Fh —(2) F67h CCPR2L F3Fh PMD0
FDEh POSTINC2
(1)
FB6h ECCP1AS F8Eh —(2) F66h CCP2CON F3Eh PMD1
FDDh POSTDEC2
(1)
FB5h —(2) F8Dh LATE
(3)
F65h PWM2CON F3Dh PMD2
FDCh PREINC2
(1)
FB4h T3GCON F8Ch LATD
(3)
F64h ECCP2AS F3Ch ANSELE
FDBh PLUSW2
(1)
FB3h TMR3H F8Bh LATC F63h PSTR2CON F3Bh ANSELD
FDAh FSR2H FB2h TMR3L F8Ah LATB F62h IOCB F3Ah ANSELC
FD9h FSR2L FB1h T3CON F89h LATA F61h WPUB F39h ANSELB
FD8h STATUS FB0h SPBRGH1 F88h —(2) F60h SLRCON F38h ANSELA
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3:PIC18(L)F4XK22 devices only.
4:PIC18(L)F26K22 and PIC18(L)F46K22 devices only.

PIC18(L)F2X/4XK22
TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
FFFh TOSU — — — Top-of-Stack, Upper Byte (TOS<20:16>) ---0 0000
FFEh TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000
FFDh TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000
FFCh STKPTR STKFUL STKUNF — STKPTR<4:0> 00-0 0000
FFBh PCLATU — — — Holding Register for PC<20:16> ---0 0000
FFAh PCLATH Holding Register for PC<15:8> 0000 0000
FF9h PCL Holding Register for PC<7:0> 0000 0000
FF8h TBLPTRU — — Program Memory Table Pointer Upper Byte(TBLPTR<21:16>) --00 0000
FF7h TBLPTRH Program Memory Table Pointer High Byte(TBLPTR<15:8>) 0000 0000
FF6h TBLPTRL Program Memory Table Pointer Low Byte(TBLPTR<7:0>) 0000 0000
FF5h TABLAT Program Memory Table Latch 0000 0000
FF4h PRODH Product Register, High Byte xxxx xxxx
FF3h PRODL Product Register, Low Byte xxxx xxxx
FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
FF1h INTCON2 INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1RBPU
FF0h INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00
FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ----
FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ----
FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ----
FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ----
FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – ---- ----
value of FSR0 offset by W
FEAh FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000
FE9h FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx
FE8h WREG Working Register xxxx xxxx
FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) ---- ----
FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ----
FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) ---- ----
FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) ---- ----
FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – ---- ----
FE2h FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000
FE1h FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx
FE0h BSR — — — — Bank Select Register ---- 0000
FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) ---- ----
FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ----
FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ----
FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) ---- ----
FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – ---- ----
FDAh FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000
FD9h FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx
FD8h STATUS — — — N OV Z DC C ---x xxxx
FD7h TMR0H Timer0 Register, High Byte 0000 0000
FD6h TMR0L Timer0 Register, Low Byte xxxx xxxx
FD5h T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 1111 1111
FD3h OSCCON IDLEN IRCF<2:0> OSTS HFIOFS SCS<1:0> 0011 q000
FD2h OSCCON2 PLLRDY SOSCRUN — MFIOSEL SOSCGO PRISD MFIOFS LFIOFS 00-0 01x0
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: PIC18(L)F4XK22 devices only.
2: PIC18(L)F2XK22 devices only.
3: PIC18(L)F23/24K22 and PIC18(L)F43/44K22 devices only.
4: PIC18(L)F26K22 and PIC18(L)F46K22 devices only.

PIC18(L)F2X/4XK22
TABLE 5-2: REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES (CONTINUED)
Value on
POR, BOR
FD1h WDTCON — — — — — — — SWDTEN ---- ---0
FD0h RCON IPEN SBOREN — 01-1 1100RI TO PD POR BOR
FCFh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx
FCEh TMR1L Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx
FCDh T1CON TMR1CS<1:0> T1CKPS<1:0> T1SOSCEN T1RD16 TMR1ON 0000 0000T1SYNC
FCCh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 xx00
DONE
FCBh SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000
FCAh SSP1MSK SSP1 MASK Register bits 1111 1111
FC9h SSP1BUF SSP1 Receive Buffer/Transmit Register xxxx xxxx
FC8h SSP1ADD SSP1 Address Register in I
2
C Slave Mode. SSP1 Baud Rate Reload Register in I
2
C Master Mode 0000 0000
FC7h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000
FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000
FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000
FC4h ADRESH A/D Result, High Byte xxxx xxxx
FC3h ADRESL A/D Result, Low Byte xxxx xxxx
FC2h ADCON0 — CHS<4:0> GO/DONE ADON --00 0000
FC1h ADCON1 TRIGSEL — — — PVCFG<1:0> NVCFG<1:0> 0--- 0000
FC0h ADCON2 ADFM — ACQT<2:0> ADCS<2:0> 0-00 0000
FBFh CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx
FBEh CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx
FBDh CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 0000 0000
FBCh TMR2 Timer2 Register 0000 0000
FBBh PR2 Timer2 Period Register 1111 1111
FBAh T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000
FB9h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001
FB8h BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 0100 0-00
FB7h PWM1CON P1RSEN P1DC<6:0> 0000 0000
FB6h ECCP1AS CCP1ASE CCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 0000 0000
FB4h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS<1:0> 0000 0x00
DONE
FB3h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx
FB2h TMR3L Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx
FB1h T3CON TMR3CS<1:0> T3CKPS<1:0> T3SOSCEN T3RD16 TMR3ON 0000 0000T3SYNC
FB0h SPBRGH1 EUSART1 Baud Rate Generator, High Byte 0000 0000
FAFh SPBRG1 EUSART1 Baud Rate Generator, Low Byte 0000 0000
FAEh RCREG1 EUSART1 Receive Register 0000 0000
FADh TXREG1 EUSART1 Transmit Register 0000 0000
FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
FAAh EEADRH
(5)
— — — — — — EEADR<9:8> ---- --00
FA9h EEADR EEADR<7:0> 0000 0000
FA8h EEDATA EEPROM Data Register 0000 0000
FA7h EECON2 EEPROM Control Register 2 (not a physical register) ---- --00
FA6h EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000
FA5h IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 0000 0000
FA4h PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 0000 0000
FA3h PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 0000 0000

PIC18(L)F2X/4XK22
Value on
POR, BOR
FA2h IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 1111 1111
FA1h PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 0000 0000
FA0h PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 0000 0000
F9Fh IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP -111 1111
F9Eh PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF -000 0000
F9Dh PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE -000 0000
F9Ch HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL<3:0> 0000 0000
F9Bh OSCTUNE INTSRC PLLEN TUN<5:0> 00xx xxxx
F96h TRISE WPUE3 — — — — TRISE2
(1)
TRISE1
(1)
TRISE0
(1)
1--- -111
F95h TRISD
(1)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111
F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111
F8Dh LATE
(1)
— — — — — LATE2 LATE1 LATE0 ---- -xxx
F8Ch LATD
(1)
LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx
F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx
F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx
F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx
F84h
PORTE
(2)
— — — — RE3 — — — ---- x---
PORTE
(1)
— — — — RE3 RE2 RE1 RE0 ---- x000
F83h PORTD
(1)
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000
F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 0000 00xx
F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxx0 0000
F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000
F7Fh IPR5 — — — — — TMR6IP TMR5IP TMR4IP ---- -111
F7Eh PIR5 — — — — — TMR6IF TMR5IF TMR4IF ---- -111
F7Dh PIE5 — — — — — TMR6IE TMR5IE TMR4IE ---- -000
F7Ch IPR4 — — — — — CCP5IP CCP4IP CCP3IP ---- -000
F7Bh PIR4 — — — — — CCP5IF CCP4IF CCP3IF ---- -000
F7Ah PIE4 — — — — — CCP5IE CCP4IE CCP3IE ---- -000
F79h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH<1:0> 0000 1000
F78h CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH<1:0> 0000 1000
F77h CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 0000 0000
F76h SPBRGH2 EUSART2 Baud Rate Generator, High Byte 0000 0000
F75h SPBRG2 EUSART2 Baud Rate Generator, Low Byte 0000 0000
F74h RCREG2 EUSART2 Receive Register 0000 0000
F73h TXREG2 EUSART2 Transmit Register 0000 0000
F72h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
F71h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
F70h BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 01x0 0-00
F6Fh SSP2BUF SSP2 Receive Buffer/Transmit Register xxxx xxxx
F6Eh SSP2ADD SSP2 Address Register in I
2
C Slave Mode. SSP2 Baud Rate Reload Register in I
2
C Master Mode 0000 0000
F6Dh SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000
F6Ch SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000
F6Bh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000
F6Ah SSP2MSK SSP1 MASK Register bits 1111 1111
F69h SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000

PIC18(L)F2X/4XK22
Value on
POR, BOR
F68h CCPR2H Capture/Compare/PWM Register 2, High Byte xxxx xxxx
F67h CCPR2L Capture/Compare/PWM Register 2, Low Byte xxxx xxxx
F66h CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 0000 0000
F65h PWM2CON P2RSEN P2DC<6:0> 0000 0000
F64h ECCP2AS CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0> 0000 0000
F63h PSTR2CON — — — STR2SYNC STR2D STR2C STR2B STR2A ---0 0001
F62h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 1111 ----
F61h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111
F60h
SLRCON
(2)
— — — — — SLRC SLRB SLRA ---- -111
SLRCON
(1)
— — — SLRE SLRD SLRC SLRB SLRA ---1 1111
F5Fh CCPR3H Capture/Compare/PWM Register 3, High Byte xxxx xxxx
F5Eh CCPR3L Capture/Compare/PWM Register 3, Low Byte xxxx xxxx
F5Dh CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 0000 0000
F5Ch PWM3CON P3RSEN P3DC<6:0> 0000 0000
F5Bh ECCP3AS CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0> 0000 0000
F5Ah PSTR3CON — — — STR3SYNC STR3D STR3C STR3B STR3A ---0 0001
F57h CCP4CON — — DC4B<1:0> CCP4M<3:0> --00 0000
F54h CCP5CON — — DC5B<1:0> CCP5M<3:0> --00 0000
F53h TMR4 Timer4 Register 0000 0000
F52h PR4 Timer4 Period Register 1111 1111
F51h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000
F50h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 0000 0000
F4Fh TMR5L Least Significant Byte of the 16-bit TMR5 Register 0000 0000
F4Eh T5CON TMR5CS<1:0> T5CKPS<1:0> T5SOSCEN T5SYNC T5RD16 TMR5ON 0000 0000
F4Dh T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS<1:0> 0000 0x00
DONE
F4Ch TMR6 Timer6 Register 0000 0000
F4Bh PR6 Timer6 Period Register 1111 1111
F4Ah T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000
F49h CCPTMRS0 C3TSEL<1:0> — C2TSEL<1:0> — C1TSEL<1:0> 00-0 0-00
F48h CCPTMRS1 — — — — C5TSEL<1:0> C4TSEL<1:0> ---- 0000
F47h SRCON0 SRLEN SRCLK<2:0> SRQEN SRNQEN SRPS SRPR 0000 0000
F46h SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000
F45h CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0000 0000
F44h CTMUCONL EDG2POL EDG2SEL<1:0> EDG1POL EDG1SEL<1:0> EDG2STAT EDG1STAT 0000 0000
F43h CTMUICON ITRIM<5:0> IRNG<1:0> 0000 0000
F42h VREFCON0 FVREN FVRST FVRS<1:0> — — — — 0001 ----
F41h VREFCON1 DACEN DACLPS DACOE — DACPSS<1:0> — DACNSS 000- 00-0
F40h VREFCON2 — — — DACR<4:0> ---0 0000
F3Fh PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 0000 0000
F3Eh PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 00-0 0000
F3Dh PMD2 — — — — CTMUMD CMP2MD CMP1MD ADCMD ---- 0000
F3Ch ANSELE
(1)
— — — — — ANSE2 ANSE1 ANSE0 ---- -111
F3Bh ANSELD
(1)
ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111

PIC18(L)F2X/4XK22
Value on
POR, BOR
F3Ah ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 1111 11--
F39h ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111
F38h ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111

PIC18(L)F2X/4XK22
5.4.5 STATUS REGISTER
The STATUS register, shown in Register 5-2,
contains the arithmetic status of the ALU. As with any
other SFR, it can be the operand for any instruction.
If the STATUS register is the destination for an
instruc-tion that affects the Z, DC, C, OV or N bits, the
results of the instruction are not written; instead, the
STATUS register is updated according to the
instruction per-formed. Therefore, the result of an
instruction with the STATUS register as its destination
may be different than intended. As an example, CLRF
STATUS will set the Z bit and leave the remaining
Status bits unchanged (‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register, because these instructions do not affect the
Z, C, DC, OV or N bits in the STATUS register.
For other instructions that do not affect Status bits,
see the instruction set summaries in Section 25.2
“Extended Instruction Set” and Table 25-3.
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
5.5 Register Definitions: Status
REGISTER 5-2: STATUS: STATUS REGISTER
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC(1) C(1)
bit 7 bit 0
Legend:
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
(1)
DC: Digit Carry/Borrow
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
(1)
C: Carry/Borrow
1 = A carry-out from the Most Significant bit of the result occurred 0
= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-
order bit of the source register.

PIC18(L)F2X/4XK22
5.6 Data Addressing Modes
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set
is enabled. See Section 5.7 “Data
Memory and the Extended Instruction
Set” for more information.
While the program memory can be addressed in only one
way – through the program counter – information in the
data memory space can be addressed in several ways.
For most instructions, the addressing mode is fixed.
Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal
Offset, is available when the extended instruction set
is enabled (XINST Configuration bit = 1). Its operation
is discussed in greater detail in Section 5.7.1
“Indexed Addressing with Literal Offset”.
5.6.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any argu-
ment at all; they either perform an operation that glob-ally
affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.6.2 DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address
in one of the banks of data RAM (Section 5.4.3
“General Purpose Register File”) or a location in
the Access Bank (Section 5.4.2 “Access Bank”) as
the data source for the instruction.
The Access RAM bit ‘a’ determines how the address
is interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.4.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-
bit address of the register. When ‘a’ is ‘0’, the address
is interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is
determined by the destination bit ‘d’. When ‘d’ is ‘1’,
the results are stored back in the source register,
overwriting its origi-nal contents. When ‘d’ is ‘0’, the
results are stored in the W register. Instructions
without the ‘d’ argument have a destination that is
implicit in the instruction; their destination is either the
target register being operated on or the W register.
5.6.3 INDIRECT ADDRESSING
Indirect addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations which are to be read
or written. Since the FSRs are themselves located in
RAM as Special File Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data struc-tures, such as
tables and arrays in data memory.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value
with auto -incrementing, auto-decrementing or
offsetting with another value. This allows for efficient
code, using loops, such as the example of clearing an
entire RAM bank in Example 5-5.
EXAMPLE 5-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
LFSR FSR0, 100h ;
Clear INDFNEXTCLRF POSTINC0 ;
; register then
BTFSS FSR0H, 1
; inc pointer
; All done with
BRA NEXT
; Bank1?
; NO, clear next
CONTINUE ; YES, continue

PIC18(L)F2X/4XK22
5.6.3.1 FSR Registers and the INDF
Operand
At the core of indirect addressing are three sets of
reg-isters: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. Each FSR
pair holds a 12-bit value, therefore, the four upper bits
of the FSRnH register are not used. The 12-bit FSR
value can address the entire range of the data
memory in a linear fashion. The FSR register pairs,
then, serve as pointers to data memory locations.
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR space but are not physically
implemented. Reading or writing to a particular INDF
register actually accesses its corresponding FSR
register pair. A read from INDF1, for example, reads
the data at the address indicated by FSR1H:FSR1L.
Instructions that use the INDF registers as operands
actually use the contents of their corresponding FSR
as a pointer to the instruction’s target. The INDF
operand is just a convenient way of using the pointer.
Because indirect addressing uses a full 12-bit
address, data RAM banking is not necessary. Thus,
the current contents of the BSR and the Access RAM
bit have no effect on determining the target address.
5.6.3.2 FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register
pair also has four additional indirect operands. Like
INDF, these are “virtual” registers which cannot be
directly read or written. Accessing these registers
actually accesses the location to which the associated
FSR register pair points, and also performs a specific
action on the FSR value. They are:
• POSTDEC: accesses the location to which the
FSR points, then automatically decrements
the FSR by 1 afterwards
• POSTINC: accesses the location to which the
FSR points, then automatically increments
the FSR by 1 afterwards
• PREINC: automatically increments the FSR
by one, then uses the location to which the
FSR points in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and
uses the location to which the result points in the
operation.
In this context, accessing an INDF register uses the
value in the associated FSR register without changing
it. Similarly, accessing a PLUSW register gives the
FSR value an offset by that in the W register;
however, neither W nor the FSR is actually changed
in the operation. Accessing the other virtual registers
changes the value of the FSR register.
FIGURE 5-10: INDIRECT ADDRESSING
Using an instruction with one of the
indirect addressing registers as the
operand....
...uses the 12 -bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair
contains ECCh. This means the
contents of location ECCh will be
added to that of the W register and
stored back in ECCh.
000h
ADDWF, INDF1, 1 Bank 0
100h
Bank 1
200h
Bank 2
300h
FSR1H:FSR1L
7 0 7 0
Bank 3
x x x x 1 1 1 0 1 1 0 0 1 1 00 through
Bank 13
E00h
Bank 14
F00h
Bank 15
FFFh
Data Memory

PIC18(L)F2X/4XK22
Operations on the FSRs with POSTDEC, POSTINC and
PREINC affect the entire register pair; that is, roll-overs
of the FSRnL register from FFh to 00h carry over to the
FSRnH register. On the other hand, results of these
operations do not change the value of any flags in the
STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form of
indexed addressing in the data memory space. By
manipulating the value in the W register, users can reach
addresses that are fixed offsets from pointer addresses.
In some applications, this can be used to implement
some powerful program control structure, such as
software stacks, inside of data memory.
5.6.3.3 Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1 using INDF0 as an operand will
return 00h. Attempts to write to INDF1 using INDF0
as the operand will result in a NOP.
On the other hand, using the virtual registers to write
to an FSR pair may not occur as planned. In these
cases, the value will be written to the FSR pair but
without any incrementing or decrementing. Thus,
writing to either the INDF2 or POSTDEC2 register will
write the same value to the FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all
direct operations. Users should proceed cautiously
when working on these registers, particularly if their
code uses indirect addressing.
Similarly, operations by indirect addressing are generally
permitted on all other SFRs. Users should exercise the
appropriate caution that they do not inadvertently change
settings that might affect the operation of the device.
5.7 Data Memory and the
Extended Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifi-
cally, the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the intro-
duction of a new addressing mode for the data
memory space.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same. Core
PIC18 instructions can still operate in both Direct and
Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing with
FSR0 and FSR1 also remain unchanged.
5.7.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes the
behavior of indirect addressing using the FSR2 register
pair within Access RAM. Under the proper conditions,
instructions that use the Access Bank – that is, most bit
-oriented and byte-oriented instructions – can invoke a
form of indexed addressing using an offset specified in
the instruction. This special addressing mode is known
as Indexed Addressing with Literal Offset, or Indexed
Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0) and
• The file address argument is less than or equal
to 5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in direct addressing), or
as an 8-bit address in the Access Bank. Instead, the
value is interpreted as an offset value to an Address
Pointer, specified by FSR2. The offset and the
contents of FSR2 are added to obtain the target
address of the operation.
5.7.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all byte-
oriented and bit-oriented instructions, or almost one-
half of the standard PIC18 instruction set. Instructions
that only use Inherent or Literal Addressing modes
are unaffected.
Additionally, byte-oriented and bit-oriented
instructions are not affected if they do not use the
Access Bank (Access RAM bit is ‘1’), or include a file
address of 60h or above. Instructions meeting these
criteria will continue to execute as before. A
comparison of the different possible addressing
modes when the extended instruction set is enabled
is shown in Figure 5-11.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 25.2.1
“Extended Instruction Syntax”.

PIC18(L)F2X/4XK22
FIGURE 5-11: COMPARING ADDRESSING OPTIONS FOR BIT -ORIENTED AND BYTE-ORIENTED
INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations F60h to FFFh (Bank
15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a’ = 0 and f ≤ 5Fh:
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The two
are added together to obtain the
address of the target register for
the instruction. The address can
be anywhere in the data
memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank
Select Register (BSR). The
address can be in any
implemented bank in the data
memory space.
000h
060h
Bank 0
100h
Bank 1
through
Bank 14
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
000h
060h
Bank 0
100h
Bank 1
through
Bank 14
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
000h
060h
Bank 0
100h
Bank 1
through
Bank 14
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
00h
60h
Valid range
for ‘f’
Access RAM
FFh
001001da ffffffff
FSR2H FSR2L
BSR
00000000
001001da ffffffff

PIC18(L)F2X/4XK22
5.7.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom section of Bank 0, this
mode maps the contents from a user defined “window”
that can be located anywhere in the data memory space.
The value of FSR2 establishes the lower bound-ary of
the addresses mapped into the window, while the upper
boundary is defined by FSR2 plus 95 (5Fh). Addresses in
the Access RAM above 5Fh are mapped as previously
described (see Section 5.4.2 “Access Bank”). An
example of Access Bank remapping in this addressing
mode is shown in Figure 5-12.
Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode.
Operations that use the BSR (Access RAM bit is ‘1’)
will continue to use direct addressing as before.
5.8 PIC18 Instruction Execution and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 25.2 “Extended Instruction Set”.
FIGURE 5-12: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Example Situation:
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region from
the FSR2 pointer (120h) to
the pointer plus 05Fh
(17Fh) are mapped to the
bottom of the Access RAM
(000h-05Fh).
Special File Registers at
F60h through FFFh are
mapped to 60h through
FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR.
000h
Bank 0
100h
Bank 1
120h
Window
17Fh 00h
Bank 1
200h Bank 1 “Window”
5Fh
60h
Bank 2
SFRs
through
Bank 14
FFh
F00h
Access Bank
Bank 15
F60h
FFFh
SFRs
Data Memory

PIC18(L)F2X/4XK22
6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed one byte at
a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 64 bytes at a time. A bulk erase
operation cannot be issued from user code.
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory
writes and erases.
A value written to program memory does not need to
be a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
The table read operation retrieves one byte of data
directly from program memory and places it into the
TABLAT register. Figure 6-1 shows the operation of a
table read.
The table write operation stores one byte of data from
the TABLAT register into a write block holding
register. The procedure to write the contents of the
holding registers into program memory is detailed in
Section 6.6 “Writing to Flash Program Memory”.
Figure 6-2 shows the operation of a table write with
program memory and data RAM.
Table operations work with byte entities. Tables
containing data, rather than program instructions, are not
required to be word aligned. Therefore, a table can start
and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
FIGURE 6-1: TABLE READ OPERATION
Instruction: TBLRD*
Table Pointer
(1)
Program Memory
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.

PIC18(L)F2X/4XK22
FIGURE 6-2: TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory Holding Registers
Table Pointer
(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR<MSBs>)
Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter-
mine where the write block will eventually be written. The process for writing the holding registers to the
program memory array is discussed in Section 6.6 “Writing to Flash Program Memory”.
6.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register
is not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will
be a program or data EEPROM memory access.
When EEPGD is clear, any subsequent operations
will operate on the data EEPROM memory. When
EEPGD is set, any subsequent operations will
operate on the program memory.
The CFGS control bit determines if the access will be to
the Configuration/Calibration registers or to program
memory/data EEPROM memory. When CFGS is set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 24.0
“Special Features of the CPU”). When CFGS is clear,
memory selection access is determined by EEPGD.
The FREE bit allows the program memory erase
operation. When FREE is set, an erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
The WREN bit is clear on power-up.
The WRERR bit is set by hardware when the WR bit
is set and cleared when the internal programming
timer expires and the write operation is complete.
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The WR control bit initiates write operations. The WR
bit cannot be cleared, only set, by firmware. Then WR
bit is cleared by hardware at the completion of the
write operation.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
The EEIF flag stays set until cleared by
firmware.

PIC18(L)F2X/4XK22
6.3 Register Definitions: Memory Control
REGISTER 6-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
0
(cleared by completion of erase operation)
= Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit
(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
normal operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
0
The WR bit can only be set (not cleared) by software.)
= Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
0
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
= Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.

PIC18(L)F2X/4XK22
6.3.1 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register
mapped into the SFR space. The Table Latch register
is used to hold 8-bit data during data transfers
between program memory and data RAM.
6.3.2 TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-ters
join to form a 22-bit wide pointer. The low-order 21 bits
allow the device to address up to 2 Mbytes of program
memory space. The 22nd bit allows access to the device
ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions
can update the TBLPTR in one of four ways based
on the table operation. These operations on the
TBLPTR affect only the low-order 21 bits.
6.3.3 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
directly into the TABLAT register.
When a TBLWT is executed the byte in the TABLAT
register is written, not to Flash memory but, to a
holding register in preparation for a program memory
write. The holding registers constitute a write block
which varies depending on the device (see Table 6-1)
.The 3, 4, or 5 LSbs of the TBLPTRL register
determine which specific address within the holding
register block is written to. The MSBs of the Table
Pointer have no effect during TBLWT operations.
When a program memory write is executed the entire
holding register block is written to the Flash memory
at the address determined by the MSbs of the
TBLPTR. The 3, 4, or 5 LSBs are ignored during
Flash memory writes. For more detail, see Section
6.6 “Writing to Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register
(TBLPTR<21:6>) point to the 64-byte block that will
be erased. The Least Significant bits (TBLPTR<5:0>)
are ignored.
Figure 6- 3 describes the relevant boundaries of TBLPTR
based on Flash program memory operations.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD* TBLPTR is not modified
TBLWT*
TBLRD*+ TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*- TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+* TBLPTR is incremented before the read/write
TBLWT+*
FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
21 TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0
TABLE ERASE/WRITE TABLE WRITE
TBLPTR<21:n+1>
(1)
TBLPTR<n:0>
(1)
TABLE READ – TBLPTR<21:0>
Note 1: n = 6 for block sizes of 64 bytes.

PIC18(L)F2X/4XK22
6.4 Reading the Flash
Program Memory
The TBLRD instruction retrieves data from program
memory and places it into data RAM. Table reads from
program memory are performed one byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized
by words. The Least Significant bit of the address
selects between the high and low bytes of the word.
Figure 6-4 shows the interface between the internal
program memory and the TABLAT.
FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address) (Odd Byte Address)
TBLPTR = xxxxx1 TBLPTR = xxxxx0
Instruction Register
FETCH TBLRD
TABLAT
(IR) Read Register
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
; read into TABLAT and incrementTBLRD*+
TABLAT, WMOVF ; get data
MOVWF WORD_EVEN
; read into TABLAT and incrementTBLRD*+
TABLAT, WMOVFW ; get data
MOVF WORD_ODD

PIC18(L)F2X/4XK22
6.5 Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes.
Only through the use of an external programmer, or
through ICSP™ control, can larger blocks of program
memory be bulk erased. Word erase in the Flash
array is not supported.
When initiating an erase sequence from the
microcontroller itself, a block of 64 bytes of program
memory is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased. The
TBLPTR<5:0> bits are ignored.
The EECON1 register commands the erase
operation. The EEPGD bit must be set to point to the
Flash program memory. The WREN bit must be set to
enable write operations. The FREE bit is set to select
an erase operation.
The write initiate sequence for EECON2, shown as
steps 4 through 6 in Section 6.5.1 “Flash Program
Memory Erase Sequence”, is used to guard against
accidental writes. This is sometimes referred to as a
long write.
A long write is necessary for erasing the internal
Flash. Instruction execution is halted during the long
write cycle. The long write is terminated by the
internal programming timer.
6.5.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory is:
1. Load Table Pointer register with address of
block being erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the block erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Re-enable interrupts.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_BLOCK
EECON1, EEPGD ; point to Flash program memoryBSF
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable block Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
; write 55hSequence MOVWF EECON2
MOVLW 0AAh
; write 0AAhMOVWF EECON2
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts

PIC18(L)F2X/4XK22
6.6 Writing to Flash Program Memory
The programming block size is 64 bytes. Word or byte
programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory.
There are only as many holding registers as there are
bytes in a write block (64 bytes).
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction needs to be executed 64 times for
each programming operation. All of the table write
operations will essentially be short writes because only
the holding registers are written. After all the holding
registers have been written, the programming operation
of that block of memory is started by configuring the
EECON1 register for a program memory write and
performing the long write sequence.
The long write is necessary for programming the
internal Flash. Instruction execution is halted during a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
Note: The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does
not attempt to change any bit from a ‘0’ to a
‘1’. When modifying individual bytes, it is
not necessary to load all holding registers
before executing a long write operation.
FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8 8 8 8
TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxx02 TBLPTR = xxxxYY
(1)
Holding Register Holding Register Holding Register Holding Register
Program Memory
Note 1: YY = 3F for 64 byte write blocks.
6.6.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the block erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 64-byte block into the holding
registers with auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write
(about 2 ms using internal timer).
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required
code is given in Example 6-3.
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in
the holding registers.

PIC18(L)F2X/4XK22
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64’ ; number of bytes in erase block
MOVWF COUNTER
; point to bufferMOVLW BUFFER_ADDR_HIGH
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
; Load TBLPTR with the baseMOVLW CODE_ADDR_UPPER
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
READ_BLOCK
MOVWF TBLPTRL
TBLRD*+ ; read into TABLAT, and inc
TABLAT, WMOVF ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
MODIFY_WORD
BRA READ_BLOCK ; repeat
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVWF FSR0L
; update buffer wordMOVLW NEW_DATA_LOW
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
ERASE_BLOCK
MOVWF INDF0
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
; point to Flash program memoryBSF EECON1, EEPGD
BSF EECON1, FREE ; enable Erase operation
Required
MOVLW 55h
; write 55hMOVWF EECON2
Sequence MOVLW 0AAh
BSF EECON1, WR ; start erase (CPU stall)
TBLRD*-
BUFFER_ADDR_HIGH
; dummy read decrement
MOVLW ; point to buffer
MOVWF FSR0H
WRITE_BUFFER_BACK
MOVWF FSR0L
MOVLW BlockSize ; number of bytes in holding register
MOVWF COUNTER
; number of write blocks in 64 bytesMOVLW D’64’/BlockSize
MOVWF COUNTER2
WRITE_BYTE_TO_HREGS
POSTINC0, W ; get low byte of buffer dataMOVF
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.

Technology Inc.

PIC18(L)F2X/4XK22
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
DECFSZ COUNTER ; loop until holding registers are full
PROGRAM_MEMORY
BRA WRITE_WORD_TO_HREGS
BSF EECON1, EEPGD ; point to Flash program memory
Required
MOVLW 55h
; write 55hMOVWF EECON2
Sequence MOVLW 0AAh
BSF EECON1, WR ; start program (CPU stall)
DCFSZ COUNTER2 ; repeat for remaining write blocks
BRA WRITE_BYTE_TO_HREGS ;
BCF EECON1, WREN ; disable write to memory
6.6.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.6.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such
as loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. If the write operation is
interrupted by a MCLR Reset or a WDT Time-out
Reset during normal operation, the WRERR bit will be
set which the user can check to decide whether a
rewrite of the location(s) is needed.
6.6.4 PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
6.7 Flash Program Operation
During Code Protection
See Section 24.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on
page
TBLPTRU — — Program Memory Table Pointer Upper Byte (TBLPTR<21:16>) —
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) —
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) —
TABLAT Program Memory Table Latch —
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 116
EECON2 EEPROM Control Register 2 (not a physical register) —
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 97
IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 129
PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 120
PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 125
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access.

PIC18(L)F2X/4XK22
7.0 DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and program memory,
which is used for long-term storage of program data.
It is not directly mapped in either the register file or
program memory space but is indirectly addressed
through the Special Function Registers (SFRs). The
EEPROM is readable and writable during normal
operation over the entire VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
• EEADRH
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR:EEADRH
register pair hold the address of the EEPROM
location being accessed.
The EEPROM data memory is rated for high
erase/write cycle endurance. A byte write
automatically erases the location and writes the new
data (erase-before-write). The write time is controlled
by an on-chip timer; it will vary with voltage and
temperature as well as from chip-to-chip. Please refer
to the Data EEPROM Memory parameters in Section
27.0 “Electrical Characteris-tics” for limits.
7.1 EEADR and EEADRH Registers
The EEADR register is used to address the data
EEPROM for read and write operations. The 8- bit
range of the register can address a memory range of
256 bytes (00h to FFh). The EEADRH register
expands the range to 1024 bytes by adding an
additional two address bits.
7.2 EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the
same registers which control access to the program
memory and are used in a similar manner for the data
EEPROM.
The EECON1 register (Register 7-1) is the control
register for data and program memory access.
Control bit EEPGD determines if the access will be to
program or data EEPROM memory. When the
EEPGD bit is clear, operations will access the data
EEPROM memory. When the EEPGD bit is set,
program memory is accessed.
Control bit, CFGS, determines if the access will be to the
Configuration registers or to program memory/data
EEPROM memory. When the CFGS bit is set,
subsequent operations access Configuration registers.
When the CFGS bit is clear, the EEPGD bit selects either
program Flash or data EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
The WRERR bit is set by hardware when the WR bit
is set and cleared when the internal programming
timer expires and the write operation is complete.
Note: During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset, or a write operation
was attempted improperly.
The WR control bit initiates write operations. The bit can
be set but not cleared by software. It is cleared only by
hardware at the completion of the write operation.
Note: The EEIF interrupt flag bit of the PIR2
register is set when the write is complete.
It must be cleared by software.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by
firmware and cleared by hardware at the completion
of the operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read
using table read instructions. See Section 6.1 “Table
Reads and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.

PIC18(L)F2X/4XK22
REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 4 FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
0
(cleared by completion of erase operation)
= Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit
(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
normal operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
0
The WR bit can only be set (not cleared) by software.)
= Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
0
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
= Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.

93 appendix pic18(l)f2 x4xk22 (1)

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