Design and build a wireless transceiver using nrf24l01p single chip 2.4g hz

Design and build a wireless transceiver using
nRF24L01Psingle chip 2.4GHz module
Project Aims
1. Connecting two laptops using wireless boards
and exchange data
Considerations
2. USB Port has been utilized to Connect boards and laptops
3. Serial protocol has been used to communicate with boards
4. HyperTerminal has been deployed to exchange data
5. Programing Software: Code VisionAVR
Limitations
1. Maximum baud rate is 2 mbps
2. Maximum wireless range is less than 50m outdoor
3. Connection is suitable to exchange any data but video
4. Changing mode RX to TX or TX to Rx lasts 130us
5. Communication channel is half duplex
Requirements
1. Two laptops
2. Two nRF24L01P modules
3. Two USB cables
4. Two boards for communicating between the
laptops and nRF24L01P modules
Project Date: October 2015- January 2016
Partner: Saeed Nasr (https://www.Linkedin.com/in/saeednasr)
Video Tutorial: Available in Persian

nRF24L01P
3
/*****************************************************
This program was produced by the
CodeWizardAVR V1.25.7a Standard
Automatic Program Generator
© Copyright 1998-2007 Pavel Haiduc, HP InfoTech s.r.l.
http://www.hpinfotech.com
Project :
Version :
Date : 1/1/2016
Author : ehsan
Company :
Comments:
sending and recieving character through usart in low speed using hyperterminal
speed=(payload length)/delay;
ach is not active
intrrupt is active and connected to INT0
register writing : possible
register reading : possible
CE enable : possible
Chip type : ATmega16L
Program type : Application
Clock frequency : 8.000000 MHz
Memory model : Small
External SRAM size : 0
Data Stack size : 256
*****************************************************/
#include <mega16.h>
#ifndef __SLEEP_DEFINED__
#define __SLEEP_DEFINED__
.EQU __se_bit=0x40
.EQU __sm_mask=0xB0
.EQU __sm_powerdown=0x20
.EQU __sm_powersave=0x30
.EQU __sm_standby=0xA0
.EQU __sm_ext_standby=0xB0
.EQU __sm_adc_noise_red=0x10
.SET power_ctrl_reg=mcucr
#endif
// Alphanumeric LCD Module functions
#asm
.equ __lcd_port=0x15 ;PORTC
#endasm
#include <lcd.h>
#include <stdint.h>
#include <stdbool.h>
// Standard Input/Output functions
#include <stdio.h>
// SPI functions

nRF24L01P
4
#include <delay.h>
#include "system.h"
#include "hal_nrf.h"
#include "hal_nrf_reg.h"
#include "hal_nrf_mega.h"
#include "radio.h"
#include "sb/radio_sb.h"
#include <spi.h>
interrupt [EXT_INT0] void ext_int0_isr(void);
interrupt [EXT_INT1] void ext_int1_isr(void);
void getcommand(uint8_t *,uint8_t *,uint8_t *);
//-------------------------Define your Parameters here-----------------------------//
typedef enum {
DEVICE_IDLE = 0, /**< The device is idle */
DEVICE_PRX_IDLE, /**< The device will operate in @b PRX mode */
DEVICE_PTX_IDLE, /**< The device will operate in @b PTX mode */
DEVICE_PRX_SB, /**< The device will operate in @b PRX mode with ShockBurst functionailty */
DEVICE_PRX_ESB, /**< The device will operate in @b PRX mode with Enhanced ShockBurst functionailty */
DEVICE_PRX_PL, /**< The device will operate in @b PRX mode with Enhanced ShockBurst functionailty
with Bidirectional data */
DEVICE_PTX_SB, /**< The device will operate in @b PTX mode with ShockBurst functionailty */
DEVICE_PTX_ESB, /**< The device will operate in @b PTX mode with Enhanced ShockBurst functionailty */
DEVICE_PTX_PL, /**< The device will operate in @b PTX mode with Enhanced ShockBurst functionailty
with Bidirectional data */
NO_CHANGE /**< No state change */
} state_t;
//------------------------ Declare your global variables here----------------------//
/** The address of the radio. Parameter to the radio init */
uint8_t address[HAL_NRF_AW_5BYTES] = {0xE7,0xE7,0xE7,0xE7,0xE0},
data[10]={0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A};
uint8_t address1[HAL_NRF_AW_5BYTES] = {0xC7,0xC7,0xC7,0xC7,0xE1},add5=0xE5;
bit flag1=1, flag2=1, bit1=1;
void main(void)
{
// Declare your local variables here
uint8_t data1, comd, value1, mes1[]="enter your register name to write", mes2[]="enter ther value",
mes3[]="WRITE DATA", a, b ,DATA2[20];
uint8_t data[]="!!123456789012345678901234567890",char1;
int i=0, counter=0;
// Port B initialization
// Func7=Out Func6=In Func5=Out Func4=Out Func3=In Func2=In Func1=In Func0=In
// State7=0 State6=T State5=0 State4=0 State3=T State2=T State1=T State0=T
system_init();
radio_sb_init(address,HAL_NRF_PRX);//reciever mode
#asm("sei")
hal_nrf_set_irq_mode( HAL_NRF_TX_DS,1);
hal_nrf_set_irq_mode( HAL_NRF_RX_DR,1);
hal_nrf_set_irq_mode( HAL_NRF_MAX_RT,0);
CE_HIGH();
lcd_clear();
lcd_putsf("ready to get command!!!");

nRF24L01P
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while (1)
{
while(PINB.0==1)
{
if (flag1==1)
{
bit1=~bit1;
char1=getchar();
hal_nrf_set_operation_mode(HAL_NRF_PTX);
CE_LOW();
hal_nrf_write_tx_pload(&char1,1);
//lcd_clear();
//lcd_gotoxy(bit1,0);
//lcd_putsf("data loaded");
flag1=0;
CE_HIGH();
}
}
comd=getchar();
if ( comd==0xee )
{
for ( i=0;mes1[i];i++)
putchar(mes1[i]);
comd=getchar();
putchar(mes2[i]);
value1=getchar();
data1=hal_nrf_write_reg(comd,value1);
putchar(data1);
}
else if (comd==0xaa)
{
putchar(mes3[i]);
getcommand(DATA2,&a,&b);
i=0;
for ( i=0;DATA2[i];i++ );
hal_nrf_write_tx_pload(DATA2,i-1);
lcd_clear();
lcd_putsf("data loaded");
}
else if( comd== RX_ADDR_P0 )
{
i=5;
CSN_LOW();
hal_nrf_rw(RX_ADDR_P0 );
while(i--)
putchar( hal_nrf_rw(0));
CSN_HIGH();
}
else if( comd== TX_ADDR )
{
i=5;
CSN_LOW();
hal_nrf_rw(TX_ADDR );
while(i--)

nRF24L01P
6
putchar( hal_nrf_rw(0));
CSN_HIGH();
}
else if ( comd==0xbb )
CE_HIGH();
else
{
data1=hal_nrf_read_reg(comd);
putchar(data1);
}
};
}
//********************************Function Definition****************************//
//============================== start:1.getcommand ===========================//
void getcommand(uint8_t *a,uint8_t *b,uint8_t *c)
{
//------------------------ Declare your local variables here---------------------//
bit flag=0;
int i=0;
char DATA[19],null1='0';
while (flag==0)
{
if (i<18)
{
DATA[i++]=getchar();
}
else
{
DATA[i]=null1;
flag=1;
}
if (DATA[i-1]==' ')
{
DATA[i-1]=null1;
flag=1;
}
}
*b=DATA[i-3];
*c=DATA[i-2];
DATA[i-3]='0';
i=0;
while( DATA[i] )
{
*a++=DATA[i++];
}
*a='0';
}
//=============================== End:1.getcommand ============================//
//----------------------------------------------------------------------------//
// External Interrupt 0 service routine

nRF24L01P
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interrupt [EXT_INT0] void ext_int0_isr(void)
{
uint8_t interrupt1, data;
#asm("cli");
interrupt1=hal_nrf_get_irq_flags();;
if ( interrupt1==0X20 )
{
//CE_LOW();
hal_nrf_clear_irq_flag(HAL_NRF_TX_DS);
//lcd_gotoxy(bit1,1);
//lcd_putsf("data sent");
flag1=1;
hal_nrf_set_operation_mode(HAL_NRF_PRX);
}
else if ( interrupt1==0X40 )
{
flag2=~flag2;
hal_nrf_read_rx_pload(&data);
hal_nrf_clear_irq_flag(HAL_NRF_RX_DR);
// lcd_clear();
// lcd_gotoxy(bit1,flag2);
// lcd_putsf("data recieved");
putchar(data);
}
GIFR=GIFR | 0x40;
#asm("sei");
}
interrupt [EXT_INT1] void ext_int1_isr(void)
{
uint8_t status1, i;
#asm("cli");
GIFR=GIFR | 0x80;
#asm("sei");
}
#include <mega16.h>
.EQU __se_bit=0x40
.EQU __sm_mask=0xB0
#endif
#include <delay.h>
#include "system.h"
void system_init (void)

nRF24L01P
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{
//================== step.1: SPI initialization =====================//
// SPI initialization
/* SPI { Type: Master, Clock Rate: 2000.000 kHz,Clock Phase: Cycle Half
Clock Polarity: Low, Data Order: MSB First*/
//PORTB.4: SS (OUTPUT) PORTB.5: MOSI (OUTPUT)
//PORTB.6: MISO (INPUT) PORTB.7: SCK (OUTPUT
SPCR=0x50;
SPSR=0x00;
//================= step.2: Ports initialization ====================//
PORTB=0x03;
DDRB=0XBC;
PORTD=0X30;//0X10 RECIEVER 0X20 TRANSMITER
PORTD.2=1;//INTERUPT0 FALLING EGG
PORTD.3=0;//INTERUPT1 RISING EGG
DDRD=0XF2;
//============== step.3: Interupts initialization ===================//
// INT { INT0: On, Mode: low level,INT1: on, falling egg, INT2: OFF }
//PORTD.2: INT0 (INPUT) PORTD.3: INT1 (INPUT)
GICR|=0xC0;
MCUCR=0x08;
MCUCSR=0x00;
GIFR=0xC0;
//================= step.4: ADC initialization ======================//
//================= step.5: USART initialization ====================//
/*Communication Parameters:{ 8 Data, 1 Stop, No Parity,Receiver On...
Transmitter On, USART Mode Asynchronous, Baud Rate: 56000*/
UCSRA=0x00;
UCSRB=0x18;
UCSRC=0x86;
UBRRH=0x00;
UBRRL=0x08;
//================== step.6: LCD initialization =====================//
lcd_init(16);
lcd_clear();
lcd_gotoxy(5,0);
lcd_putsf("USART");
lcd_gotoxy(1,1);
lcd_putsf("Initialization");
delay_ms(500);
}

nRF24L01P
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.EQU __se_bit=0x40
.EQU __sm_mask=0xB0
#endif
#include "radio.h"
#include "hal_nrf_mega.h"
#define RADIO_ACTIVITY() ( (GIFR && 0X40)== 1) /**< The register on the radio indicating
* activity on the radio */
/** How to reset the activity register */
#define RESET_RADIO_ACTIVITY() (GIFR=0X3A)
/** The payload sent over the radio. Also contains the recieved data.
* Should be read with radio_get_pload_byte(). */
static uint8_t pload[RF_PAYLOAD_LENGTH];//changed :static xdata uint8_t pload[RF_PAYLOAD_LENGTH];
/** The current status of the radio. Should be set with radio_set_status(),
* and read with radio_get_status().
*/
static radio_status_t status;
void radio_send_packet(uint8_t *packet, uint8_t length)
{
hal_nrf_write_tx_pload(packet, length); // load message into radio
CE_PULSE(); // send packet
radio_set_status (RF_BUSY); // trans. in progress; RF_BUSY
}
radio_status_t radio_get_status (void)
{
return status;
}
uint8_t radio_get_pload_byte (uint8_t byte_index)
{
return pload[byte_index];
}
void radio_set_status (radio_status_t new_status)
{
status = new_status;
}
void radio_irq(void)
{
if (RADIO_ACTIVITY()) // Check if an interupt is

nRF24L01P
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{ // triggered
switch(hal_nrf_get_clear_irq_flags ())
{
case (1<<HAL_NRF_MAX_RT): // Max retries reached
hal_nrf_flush_tx(); // flush tx fifo, avoid fifo jam
radio_set_status (RF_MAX_RT);
break;
case (1<<HAL_NRF_TX_DS): // Packet sent
radio_set_status (RF_TX_DS);
break;
case (1<<HAL_NRF_RX_DR): // Packet received
while (!hal_nrf_rx_fifo_empty ())
{
hal_nrf_read_rx_pload(pload);
}
radio_set_status (RF_RX_DR);
break;
case ((1<<HAL_NRF_RX_DR)|(1<<HAL_NRF_TX_DS)): // Ack payload recieved
while (!hal_nrf_rx_fifo_empty ())
{
hal_nrf_read_rx_pload(pload);
}
radio_set_status (RF_TX_AP);
break;
default:
break;
}
RESET_RADIO_ACTIVITY();
}
}
/* Copyright (c) 2007 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC*/
#include "hal_nrf_reg.h"
.EQU __se_bit=0x40
.EQU __sm_mask=0xB0
#endif
#include "radio_sb.h"
#include "system.h"
#include "radio.h"

nRF24L01P
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void radio_sb_init ( uint8_t *address, hal_nrf_operation_mode_t operational_mode)
{
int tw=500;
uint8_t info1,info2;
hal_nrf_close_pipe(HAL_NRF_ALL); // First close all radio pipes
// Pipe 0 and 1 open by default
lcd_clear();
lcd_putsf("all pipes closed");
delay_ms(tw);
hal_nrf_open_pipe(HAL_NRF_PIPE0, false); // Open pipe0, without/autoack
hal_nrf_open_pipe(HAL_NRF_PIPE1, false); // Open pipe1, without/autoack
//hal_nrf_open_pipe(HAL_NRF_PIPE2, false); // Open pipe5, without/autoack
lcd_clear();
lcd_putsf("pipe0 opened NAK");
/* info1=hal_nrf_read_reg(EN_RXADDR);
info2=hal_nrf_read_reg(EN_AA);
lcd_gotoxy(0,1);
if ( info1==0X01 && info2==0X00 )
lcd_putsf("command valid");
else
lcd_putsf("command Not vali");*/
delay_ms(tw);
hal_nrf_set_crc_mode(HAL_NRF_CRC_16BIT); // Operates in 16bits CRC mode
hal_nrf_set_auto_retr(0, RF_RETRANS_DELAY); // Disables auto retransmit
lcd_clear();
lcd_putsf("CRC 16,ART off");
delay_ms(tw);
hal_nrf_set_address_width(HAL_NRF_AW_5BYTES); // 5 bytes address width
hal_nrf_set_address(HAL_NRF_TX, address1); // Set device's addresses
hal_nrf_set_address(HAL_NRF_PIPE0, address); // Sets recieving address on
hal_nrf_set_address(HAL_NRF_PIPE1, address1); // Sets recieving address on
//hal_nrf_set_address(HAL_NRF_PIPE2, &add5); // Sets recieving address on
lcd_clear();
lcd_putsf("Address Loaded");
// pipe0
if(operational_mode == HAL_NRF_PTX) // Mode depentant settings
{
hal_nrf_set_operation_mode(HAL_NRF_PTX); // Enter TX mode
lcd_clear();
lcd_putsf("TX Mode Active");
delay_ms(tw);
}
else
{
hal_nrf_set_operation_mode(HAL_NRF_PRX); // Enter RX mode
hal_nrf_set_rx_pload_width((uint8_t)HAL_NRF_PIPE0, RF_PAYLOAD_LENGTH);
hal_nrf_set_rx_pload_width((uint8_t)HAL_NRF_PIPE1, RF_PAYLOAD_LENGTH);
//hal_nrf_set_rx_pload_width((uint8_t)HAL_NRF_PIPE2, RF_PAYLOAD_LENGTH);

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// Pipe0 expect
// PAYLOAD_LENGTH byte payload
// PAYLOAD_LENGTH in radio.h
lcd_clear();
lcd_putsf("RX Mode Active");
delay_ms(tw);
}
hal_nrf_set_rf_channel(RF_CHANNEL); // Operating on static channel
// Defined in radio.h.
// Frequenzy =
// 2400 + RF_CHANNEL
hal_nrf_set_power_mode(HAL_NRF_PWR_UP); // Power up device
//hal_nrf_set_datarate(HAL_NRF_1MBPS); // Uncomment this line for
// compatibility with nRF2401
// and nRF24E1
//start_timer(RF_POWER_UP_DELAY); // Wait for the radio to
//wait_for_timer(); // power up
delay_ms(RF_POWER_UP_DELAY);
lcd_clear();
lcd_putsf("system power up");
delay_ms(tw);
radio_set_status (RF_IDLE); // Radio now ready
}
#include "nordic_common.h"
.EQU __se_bit=0x40
.EQU __sm_mask=0xB0
#endif
#include <mega16.h>
#include <spi.h>
#define SET_BIT(pos) ((uint8_t) (1<<( (uint8_t) (pos) )))
#define UINT8(t) ((uint8_t) (t))
//1)
void hal_nrf_set_irq_mode(hal_nrf_irq_source_t int_source, bool irq_state)
{
if(irq_state)
{
hal_nrf_write_reg(CONFIG, hal_nrf_read_reg(CONFIG) & ~SET_BIT(int_source));
}
else
{
hal_nrf_write_reg(CONFIG, hal_nrf_read_reg(CONFIG) | SET_BIT(int_source));

nRF24L01P
13
}
}
//2)
uint8_t hal_nrf_get_clear_irq_flags(void)
{
return hal_nrf_write_reg(STATUS, (BIT_6|BIT_5|BIT_4)) & (BIT_6|BIT_5|BIT_4);
}
//3)
void hal_nrf_clear_irq_flag(hal_nrf_irq_source_t int_source)
{
hal_nrf_write_reg(STATUS, SET_BIT(int_source));
}
//4)
bool hal_nrf_get_irq_mode(uint8_t int_type)
{
if(hal_nrf_read_reg(CONFIG) & SET_BIT(int_type))
return false;
else
return true;
}
//5)
uint8_t hal_nrf_get_irq_flags(void)
{
return hal_nrf_nop() & (BIT_6|BIT_5|BIT_4);
}
//6)
void hal_nrf_set_crc_mode(hal_nrf_crc_mode_t crc_mode)
{
hal_nrf_write_reg(CONFIG, (hal_nrf_read_reg(CONFIG) & ~(BIT_3|BIT_2)) | (UINT8(crc_mode)<<2));
}
//7
void hal_nrf_open_pipe(hal_nrf_address_t pipe_num, bool auto_ack)
{
switch(pipe_num)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_PIPE2:
case HAL_NRF_PIPE3:
case HAL_NRF_PIPE4:
case HAL_NRF_PIPE5:
hal_nrf_write_reg(EN_RXADDR, hal_nrf_read_reg(EN_RXADDR) | SET_BIT(pipe_num));
if(auto_ack)
hal_nrf_write_reg(EN_AA, hal_nrf_read_reg(EN_AA) | SET_BIT(pipe_num));
else
hal_nrf_write_reg(EN_AA, hal_nrf_read_reg(EN_AA) & ~SET_BIT(pipe_num));
break;
case HAL_NRF_ALL:

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hal_nrf_write_reg(EN_RXADDR, ~(BIT_7|BIT_6));
if(auto_ack)
hal_nrf_write_reg(EN_AA, ~(BIT_7|BIT_6));
else
hal_nrf_write_reg(EN_AA, 0);
break;
default:
break;
}
}
//8
void hal_nrf_close_pipe(hal_nrf_address_t pipe_num)
{
switch(pipe_num)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_PIPE2:
case HAL_NRF_PIPE3:
case HAL_NRF_PIPE4:
case HAL_NRF_PIPE5:
hal_nrf_write_reg(EN_RXADDR, hal_nrf_read_reg(EN_RXADDR) & ~SET_BIT(pipe_num));
hal_nrf_write_reg(EN_AA, hal_nrf_read_reg(EN_AA) & ~SET_BIT(pipe_num));
break;
case HAL_NRF_ALL:
hal_nrf_write_reg(EN_RXADDR, 0);
hal_nrf_write_reg(EN_AA, 0);
break;
default:
break;
}
}
//9)
void hal_nrf_set_address(hal_nrf_address_t address, uint8_t *addr)
{
switch(address)
{
case HAL_NRF_TX:
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
hal_nrf_write_multibyte_reg((uint8_t) address, addr, 0);
break;
case HAL_NRF_PIPE2:
case HAL_NRF_PIPE3:
case HAL_NRF_PIPE4:
case HAL_NRF_PIPE5:
hal_nrf_write_reg(RX_ADDR_P0 + (uint8_t) address, *addr);
break;

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default:
break;
}
}
//10)
void hal_nrf_set_auto_retr(uint8_t retr, uint16_t delay)
{
hal_nrf_write_reg(SETUP_RETR, (((delay/250)-1)<<4) | retr);
}
//11)
void hal_nrf_set_address_width(hal_nrf_address_width_t address_width)
{
hal_nrf_write_reg(SETUP_AW, (UINT8(address_width) - 2));
}
//12)
void hal_nrf_set_rx_pload_width(uint8_t pipe_num, uint8_t pload_width)
{
hal_nrf_write_reg(RX_PW_P0 + pipe_num, pload_width);
}
//13)
uint8_t hal_nrf_get_crc_mode(void)
{
return (hal_nrf_read_reg(CONFIG) & (BIT_3|BIT_2)) >> CRCO;
}
uint8_t hal_nrf_get_pipe_status(uint8_t pipe_num)
{
uint8_t en_rx, en_aa;
en_rx = hal_nrf_read_reg(EN_RXADDR) & (1<<pipe_num);
en_aa = hal_nrf_read_reg(EN_AA) & (1<<pipe_num);
en_rx >>= pipe_num;
en_aa >>= pipe_num;
return (en_aa << 1) + en_rx;
}
uint8_t hal_nrf_get_address(uint8_t address, uint8_t *addr)//////////////////
{
switch(address)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_TX:
return hal_nrf_read_multibyte_reg(address, addr);
default:
*addr = hal_nrf_read_reg(RX_ADDR_P0 + address);
return hal_nrf_get_address_width();
}
}

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uint8_t hal_nrf_get_auto_retr_status(void)
{
return hal_nrf_read_reg(OBSERVE_TX);
}
uint8_t hal_nrf_get_packet_lost_ctr(void)
{
return (hal_nrf_read_reg(OBSERVE_TX) & (BIT_7|BIT_6|BIT_5|BIT_4)) >> 4;
}
uint8_t hal_nrf_get_address_width(void)
{
return (hal_nrf_read_reg(SETUP_AW) + 2);
}
uint8_t hal_nrf_get_rx_pload_width(uint8_t pipe_num)
{
return hal_nrf_read_reg(RX_PW_P0 + pipe_num);
}
void hal_nrf_set_operation_mode(hal_nrf_operation_mode_t op_mode)
{
if(op_mode == HAL_NRF_PRX)
{
hal_nrf_write_reg(CONFIG, (hal_nrf_read_reg(CONFIG) | (1<<PRIM_RX)));
}
else
{
hal_nrf_write_reg(CONFIG, (hal_nrf_read_reg(CONFIG) & ~(1<<PRIM_RX)));
}
}
void hal_nrf_set_power_mode(hal_nrf_pwr_mode_t pwr_mode)
{
if(pwr_mode == HAL_NRF_PWR_UP)
{
hal_nrf_write_reg(CONFIG, (hal_nrf_read_reg(CONFIG) | (1<<PWR_UP)));
}
else
{
hal_nrf_write_reg(CONFIG, (hal_nrf_read_reg(CONFIG) & ~(1<<PWR_UP)));
}
}
void hal_nrf_set_rf_channel(uint8_t channel)
{
hal_nrf_write_reg(RF_CH, channel);
}
void hal_nrf_set_output_power(hal_nrf_output_power_t power)
{
hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) & ~((1<<RF_PWR1)|(1<<RF_PWR0))) |
(UINT8(power)<<1));
}

nRF24L01P
17
void hal_nrf_set_datarate(hal_nrf_datarate_t datarate)
{
if(datarate == HAL_NRF_1MBPS)
{
hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) & ~(1<<RF_DR)));
}
else
{
hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) | (1<<RF_DR)));
}
}
uint8_t hal_nrf_get_operation_mode(void)
{
return (hal_nrf_read_reg(CONFIG) & (1<<PRIM_RX)) >> PRIM_RX;
}
uint8_t hal_nrf_get_power_mode(void)
{
return (hal_nrf_read_reg(CONFIG) & (1<<PWR_UP)) >> PWR_UP;
}
uint8_t hal_nrf_get_rf_channel(void)
{
return hal_nrf_read_reg(RF_CH);
}
uint8_t hal_nrf_get_output_power(void)
{
return (hal_nrf_read_reg(RF_SETUP) & ((1<<RF_PWR1)|(1<<RF_PWR0))) >> RF_PWR0;
}
uint8_t hal_nrf_get_datarate(void)
{
return (hal_nrf_read_reg(RF_SETUP) & (1<<RF_DR)) >> RF_DR;
}
bool hal_nrf_rx_fifo_empty(void)
{
if(hal_nrf_get_rx_data_source()==7)
{
return true;
}
else
{
return false;
}
}
bool hal_nrf_rx_fifo_full(void)
{
return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> RX_EMPTY) & 1);
}
bool hal_nrf_tx_fifo_empty(void)
{

nRF24L01P
18
return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> TX_EMPTY) & 1);
}
bool hal_nrf_tx_fifo_full(void)
{
return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> TX_FIFO_FULL) & 1);
}
uint8_t hal_nrf_get_tx_fifo_status(void)
{
return ((hal_nrf_read_reg(FIFO_STATUS) & ((1<<TX_FIFO_FULL)|(1<<TX_EMPTY))) >> 4);
}
uint8_t hal_nrf_get_rx_fifo_status(void)
{
return (hal_nrf_read_reg(FIFO_STATUS) & ((1<<RX_FULL)|(1<<RX_EMPTY)));
}
uint8_t hal_nrf_get_fifo_status(void)
{
return hal_nrf_read_reg(FIFO_STATUS);
}
uint8_t hal_nrf_get_transmit_attempts(void)
{
return hal_nrf_read_reg(OBSERVE_TX) & (BIT_3|BIT_2|BIT_1|BIT_0);
}
bool hal_nrf_get_carrier_detect(void)
{
return hal_nrf_read_reg(CD) & 1;
}
void hal_nrf_write_tx_pload(uint8_t *tx_pload, uint8_t length)////////////////
{
hal_nrf_write_multibyte_reg(UINT8(HAL_NRF_TX_PLOAD), tx_pload, length);
}
void hal_nrf_setup_dyn_pl(uint8_t setup)
{
hal_nrf_write_reg(DYNPD, setup & ~0xC0);
}
void hal_nrf_enable_dynamic_pl(void)
{
hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) | 0x04));
}
void hal_nrf_disable_dynamic_pl(void)
{
hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) & ~0x04));
}
void hal_nrf_enable_ack_pl(void)
{

nRF24L01P
19
}
void hal_nrf_disable_ack_pl(void)
{
}
void hal_nrf_enable_dynamic_ack(void)
{
}
void hal_nrf_disable_dynamic_ack(void)
{
}
void hal_nrf_write_ack_pload(uint8_t pipe, uint8_t *tx_pload, uint8_t length)
{
CSN_LOW();
hal_nrf_rw(WR_ACK_PLOAD | pipe);
while(length--)
{
hal_nrf_rw(*tx_pload++);
}
CSN_HIGH();
}
uint8_t hal_nrf_read_rx_pl_w()
{
uint8_t temp;
CSN_LOW();
hal_nrf_rw(RD_RX_PLOAD_W);
temp = hal_nrf_rw(0);
CSN_HIGH();
return temp;
}
void hal_nrf_lock_unlock()
{
CSN_LOW();
hal_nrf_rw(LOCK_UNLOCK);
hal_nrf_rw(0x73);
CSN_HIGH();
}
uint8_t hal_nrf_get_rx_data_source(void)
{
return ((hal_nrf_nop() & (BIT_3|BIT_2|BIT_1)) >> 1);

nRF24L01P
20
}
// Fixed: returns length==0 and pipe==7 means FIFO empty
uint16_t hal_nrf_read_rx_pload(uint8_t *rx_pload)
{
return hal_nrf_read_multibyte_reg(UINT8(HAL_NRF_RX_PLOAD), rx_pload);
}
void hal_nrf_reuse_tx(void)
{
hal_nrf_write_reg(REUSE_TX_PL, 0);
}
bool hal_nrf_get_reuse_tx_status(void)
{
return (bool)((hal_nrf_get_fifo_status() & (1<<TX_REUSE)) >> TX_REUSE);
}
void hal_nrf_flush_rx(void)
{
hal_nrf_write_reg(FLUSH_RX, 0);
}
void hal_nrf_flush_tx(void)
{
hal_nrf_write_reg(FLUSH_TX, 0);
}
uint8_t hal_nrf_nop(void)
{
return hal_nrf_write_reg(NOP,0);
}
void hal_nrf_set_pll_mode(hal_nrf_pll_mode_t pll_mode)
{
if(pll_mode == HAL_NRF_PLL_LOCK)
{
hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) | (1<<PLL_LOCK)));
}
else
{
hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) & ~(1<<PLL_LOCK)));
}
}
hal_nrf_pll_mode_t hal_nrf_get_pll_mode(void)
{
return (hal_nrf_pll_mode_t)((hal_nrf_read_reg(RF_SETUP) & (1<<PLL_LOCK)) >> PLL_LOCK);
}
void hal_nrf_set_lna_gain(hal_nrf_lna_mode_t lna_gain)
{
if(lna_gain == HAL_NRF_LNA_HCURR)
{
hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) | (1<<LNA_HCURR)));

nRF24L01P
21
}
else
{
hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) & ~(1<<LNA_HCURR)));
}
}
hal_nrf_lna_mode_t hal_nrf_get_lna_gain(void)
{
return (hal_nrf_lna_mode_t) ( (hal_nrf_read_reg(RF_SETUP) & (1<<LNA_HCURR)) >> LNA_HCURR );
}
uint8_t hal_nrf_read_reg(uint8_t reg)
{
uint8_t temp;
CSN_LOW();
hal_nrf_rw(reg);
temp = hal_nrf_rw(0);
CSN_HIGH();
return temp;
}
uint8_t hal_nrf_write_reg(uint8_t reg, uint8_t value)
{
uint8_t retval;
CSN_LOW();
if(reg < WRITE_REG) // i.e. this is a register access
{
retval = hal_nrf_rw(WRITE_REG + reg);
hal_nrf_rw(value);
}
else // single byte cmd OR future command/register access
{
if(!(reg == FLUSH_TX) && !(reg == FLUSH_RX) && !(reg == REUSE_TX_PL) && !(reg == NOP))
{
retval = hal_nrf_rw(reg);
hal_nrf_rw(value);
}
else // single byte L01 command
{
retval = hal_nrf_rw(reg);
}
}
CSN_HIGH();
return retval;
}
uint16_t hal_nrf_read_multibyte_reg(uint8_t reg, uint8_t *pbuf)
{
uint8_t ctr, length;
switch(reg)
{
case HAL_NRF_PIPE0:

nRF24L01P
22
case HAL_NRF_PIPE1:
case HAL_NRF_TX:
length = ctr = hal_nrf_get_address_width();
CSN_LOW();
hal_nrf_rw(RX_ADDR_P0 + reg);
break;
case HAL_NRF_RX_PLOAD:
if( (reg = hal_nrf_get_rx_data_source()) < 7)
{
length = ctr = hal_nrf_read_rx_pl_w();
CSN_LOW();
hal_nrf_rw(RD_RX_PLOAD);
}
else
{
ctr = length = 0;
}
break;
default:
ctr = length = 0;
break;
}
while(ctr--)
{
*pbuf++ = hal_nrf_rw(0);
}
CSN_HIGH();
return (((uint16_t) reg << 8) | length);
}
void hal_nrf_write_multibyte_reg(uint8_t reg, uint8_t *pbuf, uint8_t length)
{
switch(reg)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_TX:
length = hal_nrf_get_address_width();
CSN_LOW();
hal_nrf_rw(WRITE_REG + RX_ADDR_P0 + reg);
break;
case HAL_NRF_TX_PLOAD:
CSN_LOW();
hal_nrf_rw(WR_TX_PLOAD);
break;
default:
break;
}

nRF24L01P
23
while(length--)
{
hal_nrf_rw(*pbuf++);
}
CSN_HIGH();
}
uint8_t hal_nrf_rw(uint8_t value)//write date to SPI
{
uint8_t ret;
ret=spi(value);
return (ret); // return SPI read value.
}

Design and build a wireless transceiver using nrf24l01p single chip 2.4g hz

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