Tutorial at the European Nanoelectronics Applications, Design & Technology Conference 2016
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The document discusses electronic system modeling and design beyond Moore's law. It proposes the Contrex modeling methodology which uses UML profiles like MARTE for model-driven design of embedded systems. The methodology supports mixed-criticality modeling, design space exploration, performance analysis, and software synthesis from a single model. It also discusses how system design needs to evolve beyond Moore's law as chip scaling slows, focusing on programming platforms for the Internet of Everything.
![CONTREX Modeling MethodologyCONTREX Modeling Methodology
C iti lit Criticality
Integer Level of importance
Functional & Extra-Functional Requirements
Implications on analysis and development
In-lined with usual definitions
Level of assurance against failure [Burns&Davis, 2015]g
Safety Standards
IEC/EN 61508 (SIL)
DO-178B
ISO 26262 (ASIL)
June 20, 2016 16Nanoelectronics, Applications, Design & Technology Conference](https://image.slidesharecdn.com/evtutorial-160704101027/85/Tutorial-at-the-European-Nanoelectronics-Applications-Design-Technology-Conference-2016-16-320.jpg)
![Performance Analysis
N ti Si l ti
Performance Analysis
Native Simulation
…
Overflow = 0;
Global variable
int Sim_Time = 0;
TB() is a function of
# of binary instructions
type of instructions
# f h i
;
s = 1L;
for (i = 0; i < L_subfr; i++) {
Carry = 0;
s L macNs(s xn[i] y1[i]);
Sim_Time += TB();
# of cache misses
frequency
evens = L_macNs(s, xn[i], y1[i]);
if (Overflow != 0) {
break; }}
if (Overflow == 0) {
Sim_Time += TB();
Sim_Time += TB();
even
data dependencies
( ) {
exp_xy = norm_l(s);
if (exp_xy<=0)
xy = round(L_shr (s, -exp_xy));
else
Sim_Time += TB();
Sim Time += TB();
TSYS() is a function of
preemptions
else
xy = round(L_shl (s, exp_xy)); }
mutex_lock(mutex_name);
…
_ B();
Sim_Time += TB();
wait included
Sim Time += T ();
conflicts in the bus
Sim_Time += TSYS();
June 20, 2016 25Nanoelectronics, Applications, Design & Technology Conference](https://image.slidesharecdn.com/evtutorial-160704101027/85/Tutorial-at-the-European-Nanoelectronics-Applications-Design-Technology-Conference-2016-25-320.jpg)
Tutorial at the European Nanoelectronics Applications, Design & Technology Conference 2016
- 1. Electronic System Modeling, Analysis and Design beyond Moore’s Law: A proposalDesign beyond Moore s Law: A proposal Eugenio Villar Schedulablity Analysis Simulation Verification Reusability Embedded Systems Lab University of Cantabria Spain Performance AnalysisOptimization Reusability p Design-Space Exploration Architectural Mapping HW Synthesis SW Synthesis
- 2. AgendaAgenda M ti ti & I t d ti Motivation & Introduction Contrex Modeling Methodology Contrex Modeling Methodology Single-Source Design Approach Performance analysis SW Synthesis System Design beyond Moore’s Law Conclusions June 20, 2016 2Nanoelectronics, Applications, Design & Technology Conference
- 3. AgendaAgenda M ti ti & I t d ti Motivation & Introduction Contrex Modeling Methodology Contrex Modeling Methodology Single-Source Design Approach Performance analysis SW Synthesis System Design beyond Moore’s Law Conclusions June 20, 2016 3Nanoelectronics, Applications, Design & Technology Conference
- 4. MotivationMotivation D i d ti it Design productivity gap More powerful design technologies I i th b t ti l l Increasing the abstraction level Increasing reusability June 20, 2016 4Nanoelectronics, Applications, Design & Technology Conference
- 5. MotivationMotivation D i d ti it H-MPSoC Design productivity gap ?? C/C++ OpenCL/MPC/C++ MPSoC SoC UML C/C++ OpenCL/MP ASIC p SystemC Verilog C/C++ SystemC VerilogC/C++ Verilog SoC p SystemC Verilog Verilog Mapping SW Synthesis Compilation HW/SW CoDesign Compilation Verilog Compilation RTLSynthesis … Compilation Behavioral Synthesis … Compilation Behavioral Synthesis … Compilation RTLSynthesis … June 20, 2016 5Nanoelectronics, Applications, Design & Technology Conference
- 6. IntroductionIntroduction M d l D i D i (MDD) Model-Driven Design (MDD) High-abstraction level Mature SW engineering methodology State-of-the-Art Matlab-Simulink Proprietary, only one MoC, M languagey y g g Co-Fluent Proprietary, a few MoCs, C language Ptolemy II Academic, any MoC, C/C++ inside a Java block … June 20, 2016 6Nanoelectronics, Applications, Design & Technology Conference
- 7. IntroductionIntroduction UML UML Standard, any MoC, any language Natural way to capture system architecture M A B M A Semantics lacks Domain-specific profiles N2 BN1 p p MetaMorph OpenSource any MoC any (skeleton) OpenSource, any MoC, any (skeleton) June 20, 2016 7Nanoelectronics, Applications, Design & Technology Conference
- 8. IntroductionIntroduction UML UML UML UMLUML HPC DSLs UML DC DSLs UML ES DSLs UML SmartPhone DSLs ForTran,… Python,… MPI,… Java,… MPI,… ADA,… C/C++,… MCAPI,… HTML5,… Java,… , , June 20, 2016 8Nanoelectronics, Applications, Design & Technology Conference
- 9. IntroductionIntroduction MARTE MARTE Standard UML profile for real-time embedded tsystems Platform-Independent Model (PIM) Platform Description Model (PDM) Platform Description Model (PDM) Platform-Specific Model (PSM) Rich semantics content S h d l bilit Rich semantics content Single-source approach Schedulability Analysis Simulation Verification Reusability Performance Analysis Design-SpaceArchitectural Optimization Design Space Exploration Architectural Mapping HW Synthesis SW Synthesis June 20, 2016 9Nanoelectronics, Applications, Design & Technology Conference
- 10. AgendaAgenda M ti ti & I t d ti Motivation & Introduction Contrex Modeling Methodology Contrex Modeling Methodology Single-Source Design Approach Performance analysis SW Synthesis System Design beyond Moore’s Law Conclusions June 20, 2016 10Nanoelectronics, Applications, Design & Technology Conference
- 11. CONTREX Modeling MethodologyCONTREX Modeling Methodology M i f t Main features MDD support Component-Based Engineering approach SW centric Standard MARTE profile Supporting Mixed-Criticality Modeling Supporting Design-Space Exploration System Performance Analysis SW Synthesis June 20, 2016 11Nanoelectronics, Applications, Design & Technology Conference
- 12. CONTREX Modeling Methodology A hit t l D i CONTREX Modeling Methodology Architectural Design Code reuse and/or developmentp platform independent HW/SW platform Architectural mapping Architectural mapping June 20, 2016 12Nanoelectronics, Applications, Design & Technology Conference
- 13. CONTREX Modeling MethodologyCONTREX Modeling Methodology Mi d C iti lit Cl i l h Mixed-Criticality: Classical approach Data Flight C Camera C t l Logging Mining P di t bl P f Control Control Logging Platform Predictable Performance June 20, 2016 13Nanoelectronics, Applications, Design & Technology Conference
- 14. CONTREX Modeling MethodologyCONTREX Modeling Methodology Mi d C iti lit h Mixed-Criticality approach Data Flight C Camera C t l Logging Mining Control Control Logging Predictable Performance Low-Cost June 20, 2016 14Nanoelectronics, Applications, Design & Technology Conference
- 15. CONTREX Modeling MethodologyCONTREX Modeling Methodology Mi d C iti lit Mixed-Criticality Mixed-Criticality Application Sh dShared Resources June 20, 2016 15Nanoelectronics, Applications, Design & Technology Conference
- 16. CONTREX Modeling MethodologyCONTREX Modeling Methodology C iti lit Criticality Integer Level of importance Functional & Extra-Functional Requirements Implications on analysis and development In-lined with usual definitions Level of assurance against failure [Burns&Davis, 2015]g Safety Standards IEC/EN 61508 (SIL) DO-178B ISO 26262 (ASIL) June 20, 2016 16Nanoelectronics, Applications, Design & Technology Conference
- 17. CONTREX Modeling MethodologyCONTREX Modeling Methodology C iti lit f A li ti C t Criticality of Application Components For imposing conditions on the software development Associate criticality to all the related constraints and sub- components June 20, 2016 17Nanoelectronics, Applications, Design & Technology Conference
- 18. CONTREX Modeling MethodologyCONTREX Modeling Methodology C iti lit f Pl tf C t Criticality of Platform Components HW constraints derived from the criticality level Imposing conditions on the hardware development Coherence of application to platform component mapping June 20, 2016 18Nanoelectronics, Applications, Design & Technology Conference
- 19. CONTREX Modeling MethodologyCONTREX Modeling Methodology D i S E l ti Design Space Exploration A single model for describing the Design Space DSE parameters: declared as VSL expressions within an attribute of t d l ti Through a constraint associated a component declaration to a component instance June 20, 2016 19Nanoelectronics, Applications, Design & Technology Conference
- 20. CONTREX Modeling MethodologyCONTREX Modeling Methodology D i S E l ti Design Space Exploration Mapping Exploration June 20, 2016 20Nanoelectronics, Applications, Design & Technology Conference
- 21. CONTREX Modeling MethodologyCONTREX Modeling Methodology D i S Design Space a N-dimensional cube (36 = 729) June 20, 2016 21Nanoelectronics, Applications, Design & Technology Conference
- 22. CONTREX Modeling MethodologyCONTREX Modeling Methodology DSE l DSE rules Constrain the N-dimensional cube June 20, 2016 22Nanoelectronics, Applications, Design & Technology Conference
- 23. AgendaAgenda M ti ti & I t d ti Motivation & Introduction Contrex Modeling Methodology Contrex Modeling Methodology Single-Source Design Approach Performance analysis SW Synthesis System Design beyond Moore’s Law Conclusions June 20, 2016 23Nanoelectronics, Applications, Design & Technology Conference
- 24. Performance Analysis P bl St t t Performance Analysis Problem Statement Fast Simulation & Performance Analysis before full SW Development Native Simulation Host-Compiled Host Compiled June 20, 2016 24Nanoelectronics, Applications, Design & Technology Conference
- 25. Performance Analysis N ti Si l ti Performance Analysis Native Simulation … Overflow = 0; Global variable int Sim_Time = 0; TB() is a function of # of binary instructions type of instructions # f h i ; s = 1L; for (i = 0; i < L_subfr; i++) { Carry = 0; s L macNs(s xn[i] y1[i]); Sim_Time += TB(); # of cache misses frequency evens = L_macNs(s, xn[i], y1[i]); if (Overflow != 0) { break; }} if (Overflow == 0) { Sim_Time += TB(); Sim_Time += TB(); even data dependencies ( ) { exp_xy = norm_l(s); if (exp_xy<=0) xy = round(L_shr (s, -exp_xy)); else Sim_Time += TB(); Sim Time += TB(); TSYS() is a function of preemptions else xy = round(L_shl (s, exp_xy)); } mutex_lock(mutex_name); … _ B(); Sim_Time += TB(); wait included Sim Time += T (); conflicts in the bus Sim_Time += TSYS(); June 20, 2016 25Nanoelectronics, Applications, Design & Technology Conference
- 26. SW SynthesisSW Synthesis F ti l th i Functional synthesis ‘main’ functions DSP optimized C code OpenCL/GL code for GPU Platform- Independent C code Static concurrency Platform-Specific code C codeGPUC code Optimized C code for DSPs OpenCL/GL for GPUs C/C++ & OpenMP for SMPs C3 C/C++ & OpenMP for SMPs… Memory Space OS GPUGPU SMP node DSP Communication Infrastructure June 20, 2016 26Nanoelectronics, Applications, Design & Technology Conference
- 27. SW SynthesisSW Synthesis C i ti th i Communication synthesis Architectural mapping Memory space OS Processing node Processing node Benefits / Drawbacks Benefits / Drawbacks Communication Speed Memory protection Memory/cache use Scheduling P ll li Parallelism… June 20, 2016 27Nanoelectronics, Applications, Design & Technology Conference
- 28. AgendaAgenda M ti ti & I t d ti Motivation & Introduction Contrex Modeling Methodology Contrex Modeling Methodology Single-Source Design Approach Performance analysis SW Synthesis System Design beyond Moore’s Law Conclusions June 20, 2016 28Nanoelectronics, Applications, Design & Technology Conference
- 29. System Design beyond Moore’s LawSystem Design beyond Moore s Law M ’ L i i Moore’s Law is passing away Long live to Moore’s Law! No party lasts forever June 20, 2016 29Nanoelectronics, Applications, Design & Technology Conference
- 30. System Design beyond Moore’s LawSystem Design beyond Moore s Law Th t h ld ti The party should continue Equivalent scaling => Vertical nanowires => Graphene => Quantum computing => … Pragmatic position opens competitive advantages in new technologies =>p p g g June 20, 2016 30Nanoelectronics, Applications, Design & Technology Conference
- 31. System Design beyond Moore’s LawSystem Design beyond Moore s Law Design Automation Tools El t i V l Ch i ‘Fabless’ Chip DesignIP Provider Today Electronics Value Chain Silicon Foundry Semiconductor Equipment Manufacturer Integrated Device Manufacturer (IDM) Original Design Manufacturer (ODM) Electronic Manufacturing Services (EMS) Original Equipment Manufacturer (OEM) Service ProviderRetail SW Provider Industrial End User Consumer End User June 20, 2016 31Nanoelectronics, Applications, Design & Technology Conference
- 32. System Design beyond Moore’s LawSystem Design beyond Moore s Law Design Automation Tools El t i V l Ch i ‘Fabless’ Chip DesignIP Provider Electronics Value Chain Tomorrow Silicon Foundry Semiconductor Equipment Manufacturer Integrated Device Manufacturer (IDM) Original Design Manufacturer (ODM) Electronic Manufacturing Services (EMS) Original Equipment Manufacturer (OEM) Service ProviderRetail SW Provider Industrial End User Consumer End User June 20, 2016 32Nanoelectronics, Applications, Design & Technology Conference
- 33. System Design beyond Moore’s LawSystem Design beyond Moore s Law I t l i t t i li ti Intel investment in applications Wearables, drones… Google & Microsoft investing in HW Google X Catapult Google X, Catapult… The end of technological obsolescence? June 20, 2016 33Nanoelectronics, Applications, Design & Technology Conference
- 34. System Design beyond Moore’s LawSystem Design beyond Moore s Law P i th I t t f E thi Programming the Internet of Everything Services provided on computing platforms of many kind June 20, 2016 34Nanoelectronics, Applications, Design & Technology Conference
- 35. System Design beyond Moore’s LawSystem Design beyond Moore s Law P i th I t t f E thi Programming the Internet of Everything Services provided on computing platforms of many kind S i UML HPC DSLs UML DC DSLs UML ES DSLs UML SmartPhone DSLs Service ForTran J HTML5 DSLs ForTran,… Python,… MPI,… Java,… MPI,… C/C++,… MCAPI,… HTML5,… Java,… June 20, 2016 35Nanoelectronics, Applications, Design & Technology Conference
- 36. System Design beyond Moore’s LawSystem Design beyond Moore s Law P i th I t t f E thi Programming the Internet of Everything Services provided on computing platforms of many kind Schedulability S ForTran, Python, Java, HTML5 Concerns Performance, safety, cost, security size Schedulability Analysis Simulation Verification P fD i S Optimization Service UML CPSoS DSL HWSW (RT)OSCorba TCT/IP HTML5, C/C++,… security, size, … Performance Analysis Design-Space Exploration CPSoS DSL SynthesisSynthesis (RT)OS, Runtime,… Corba, TCT/IP, MPI, MCAPI,… June 20, 2016 36Nanoelectronics, Applications, Design & Technology Conference
- 37. AgendaAgenda M ti ti & I t d ti Motivation & Introduction Contrex Modeling Methodology Contrex Modeling Methodology Single-Source Design Approach Performance analysis SW Synthesis System Design beyond Moore’s Law Conclusions June 20, 2016 37Nanoelectronics, Applications, Design & Technology Conference
- 38. ConclusionsConclusions C t UML/MARTE M d li M th d l Contrex UML/MARTE Modeling Methodology Reusability Component-Based Engineering approach SW centric DSE-oriented Supporting Mixed-Criticality Design Performance Analysis SW synthesis Powerful Single-Source approach June 20, 2016 38Nanoelectronics, Applications, Design & Technology Conference
- 39. ConclusionsConclusions CPS S th i i ti CPSoS as the main innovation area Holistic, single-source approach to CPSoS Design Services over the IoE Understanding complex interactions among devices Facing heterogeneity Detecting emergent behaviors Adapted to the human behavior Adapted to the human behavior Design framework beyond Moore’s Lawg y June 20, 2016 39Nanoelectronics, Applications, Design & Technology Conference