Programming the Network Data Plane
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The document discusses the evolution and possibilities of programmable networking, focusing on the Protocol Independent Switch Architecture (PISA) and the P4 programming language designed for protocol-independent packet processing. It highlights the challenges of traditional networking and advocates for a more flexible, efficient, and developer-friendly approach to network configuration and programming. The presentation outlines various innovative applications and improvements achievable through these technologies, emphasizing the transformative potential they hold for software-defined networking.
![Buffer
M M
17
Programmable
Parser
PISA: Protocol Independent Switch Architecture
Match Logic
(Mix of SRAM and TCAM for lookup tables,
counters, meters, generic hash tables)
Action Logic
(ALUs for standard boolean and arithmetic operations,
header modification operations, hashing operations, etc.)
Recirculation
Programmable
Packet Generator
CPU (Control plane)
A
…
A
…
Ingress match-action stages (pre-switching) Egress match-action stages (post-switching)
Generalization of RMT [sigcomm’13]](https://image.slidesharecdn.com/untitled-180320124229/85/Programming-the-Network-Data-Plane-19-320.jpg)
![Log, Analyze
Replay
Add: SwitchID, Arrival Time,
Queue Delay, Matched Rules, …
Original Packet
Visualize
In-band Network Telemetry (INT)
A read-only version of Tiny Packet Programs [sigcomm’14]](https://image.slidesharecdn.com/untitled-180320124229/85/Programming-the-Network-Data-Plane-30-320.jpg)
![What we have seen so far:
Offloading part of computing to network
1. DNS cache
2. Key-value cache [ACM SOSP’17]
3. Chain replication
4. Paxos [ACM CCR’16] and RAFT
5. Parameter service for DNN training
35](https://image.slidesharecdn.com/untitled-180320124229/85/Programming-the-Network-Data-Plane-37-320.jpg)
![Example: NetCache
Clients
Key-Value
Cache
Query
Statistics
High-performance Storage Servers
Key-Value Storage RackController
L2/L3
Routing
ToR Switch Data plane
• Non-goal
– Maximize the cache hit rate
• Goal
– Balance the workloads of backend servers by serving
only O(NlogN) hot items -- N is the number of
backend servers
– Make the “fast, small-cache” theory viable for
modern in-memory KV servers [Fan et. al., SOCC’11]
• Data plane
– Unmodified routing
– Key-value cache built with on-chip SRAM
– Query statistics to detect hot items
• Control plane
– Update cache with hot items to handle dynamic
workloads](https://image.slidesharecdn.com/untitled-180320124229/85/Programming-the-Network-Data-Plane-38-320.jpg)
Programming the Network Data Plane
- 2. InfoQ.com: News & Community Site • Over 1,000,000 software developers, architects and CTOs read the site world- wide every month • 250,000 senior developers subscribe to our weekly newsletter • Published in 4 languages (English, Chinese, Japanese and Brazilian Portuguese) • Post content from our QCon conferences • 2 dedicated podcast channels: The InfoQ Podcast, with a focus on Architecture and The Engineering Culture Podcast, with a focus on building • 96 deep dives on innovative topics packed as downloadable emags and minibooks • Over 40 new content items per week Watch the video with slide synchronization on InfoQ.com! https://www.infoq.com/presentations/ pisa-asic-p4
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- 4. Beautiful ideas: What if you could … • Realize a small, but super-fast DNS cache • Perform TCP SYN authentication for billions of SYNs per sec • Build a replicated key-value store ensuring RW ops in a few usecs • Improve your consensus service performance by ~100x • Boost your Memcached cluster’s throughput by ~10x • Speed up your DNN training dramatically by realizing parameter servers 2 … using switches in your network?
- 5. You couldn’t do any of those so far because … • No DIY – must work with vendors at feature level • Excruciatingly complicated and involved process to build consensus and pressure for features • Painfully long and unpredictable lead time • To use new features, you must get new switches • What you finally get != what you asked for 3
- 6. This is very unnatural to developers • Because you all know how to realize your own ideas by “programming” CPUs – Programs used in every phase (implement, test, and deploy) – Extremely fast iteration and differentiation – You own your own ideas – A sustainable ecosystem where all participants benefit 4 Can we replicate this healthy, sustainable ecosystem for networking?
- 7. Reality: Packet forwarding speeds 0.1 1 10 100 1000 10000 100000 1990 1995 2000 2005 2010 2015 2020 Switch Chip CPU 5 Gb/s (per chip) 6.4Tb/s
- 8. Reality: Packet forwarding speeds 0.1 1 10 100 1000 10000 100000 1990 1995 2000 2005 2010 2015 2020 Switch Chip CPU 6 80x Gb/s (per chip) 6.4Tb/s
- 9. 7 What does a typical switch look like? Chip Driver Run-time API Protocol Daemons (BGP, OSPF, etc.) Other Mgmt Apps Data plane Control plane Switch OS (Linux variant) PCIe … L2 Forwarding Table L3 Routing Table ACL Table … A switch is just a Linux box with a high-speed switching chip packets packets Just S/W -- You can freely change this Fixed-function H/W -- There’s nothing you can change here
- 16. PISA: An architecture for high-speed programmable packet forwarding 14
- 17. 15 Programmable Parser Match Memory Action ALU PISA: Protocol Independent Switch Architecture
- 18. 16 Programmable Parser PISA: Protocol Independent Switch Architecture Ingress EgressBuffer
- 19. Buffer M M 17 Programmable Parser PISA: Protocol Independent Switch Architecture Match Logic (Mix of SRAM and TCAM for lookup tables, counters, meters, generic hash tables) Action Logic (ALUs for standard boolean and arithmetic operations, header modification operations, hashing operations, etc.) Recirculation Programmable Packet Generator CPU (Control plane) A … A … Ingress match-action stages (pre-switching) Egress match-action stages (post-switching) Generalization of RMT [sigcomm’13]
- 20. Why we call it protocol-independent packet processing 18
- 21. Logical Data-plane View (your P4 program) Switch Pipeline Device does not understand any protocols until it gets programmed Queues Programmable Parser Fixed Action MatchTable MatchTable MatchTable MatchTable L2 IPv4 IPv6 ACL ActionALUs ActionALUs ActionALUs ActionALUs packetpacket packetpacket CLK 19
- 22. MatchTable ActionALUs Mapping logical data-plane design to physical resources Queues MatchTable MatchTable MatchTable L2Table IPv4Table IPv6Table ACLTable ActionALUs ActionALUs ActionALUs L2 IPv4 IPv6 ACL Logical Data-plane View (your P4 program) Switch Pipeline L2 IPv6 ACL IPv4 L2ActionMacro v4ActionMacro v6ActionMacro ACLActionMacro Programmable Parser CLK 20
- 23. Re-program in the field L2Table IPv4Table ACLTable IPv6Table My Encap L2 IPv4 IPv6 ACL MyEncap L2ActionMacro v4ActionMacro ACLActionMacro Action MyEncap v6ActionMacro IPv4 Action IPv4 Action IPv6 Action IPv6 Programmable Parser CLK Logical Data-plane View (your P4 program) Switch Pipeline Queues 21
- 24. P4: Programming Protocol-Independent Packet Processors Pat Bosshart† , Dan Daly* , Glen Gibb† , Martin Izzard† , Nick McKeown‡ , Jennifer Rexford** , Cole Schlesinger** , Dan Talayco† , Amin Vahdat¶ , George Varghese§ , David Walker** † Barefoot Networks * Intel ‡ Stanford University ** Princeton University ¶ Google § Microsoft Research ABSTRACTP4 is a high-level language for programming protocol-inde- pendent packet processors. P4 works in conjunction with SDN control protocols like OpenFlow. In its current form, OpenFlow explicitly specifies protocol headers on which it operates. This set has grown from 12 to 41 fields in a few years, increasing the complexity of the specification while still not providing the flexibility to add new headers. In this paper we propose P4 as a strawman proposal for how Open- Flow should evolve in the future. We have three goals: (1) Reconfigurability in the field: Programmers should be able to change the way switches process packets once they are deployed. (2) Protocol independence: Switches should not be tied to any specific network protocols. (3) Target inde- pendence: Programmers should be able to describe packet- processing functionality independently of the specifics of the underlying hardware. As an example, we describe how to use P4 to configure a switch to add a new hierarchical label. 1. INTRODUCTION Software-Defined Networking (SDN) gives operators pro- grammatic control over their networks. In SDN, the con- trol plane is physically separate from the forwarding plane, and one control plane controls multiple forwarding devices. While forwarding devices could be programmed in many ways, having a common, open, vendor-agnostic interface (like OpenFlow) enables a control plane to control forward- ing devices from di↵erent hardware and software vendors. Version Date Header Fields OF 1.0 Dec 2009 12 fields (Ethernet, TCP/IPv4) OF 1.1 Feb 2011 15 fields (MPLS, inter-table metadata) OF 1.2 Dec 2011 36 fields (ARP, ICMP, IPv6, etc.) OF 1.3 Jun 2012 40 fields OF 1.4 Oct 2013 41 fields Table 1: Field multiple stages of rule tables, to allow switches to expose more of their capabilities to the controller. The proliferation of new header fields shows no signs of stopping. For example, data-center network operators in- creasingly want to apply new forms of packet encapsula- tion (e.g., NVGRE, VXLAN, and STT), for which they re- sort to deploying software switches that are easier to extend with new functionality. Rather than repeatedly extending the OpenFlow specification, we argue that future switches should support flexible mechanisms for parsing packets and matching header fields, allowing controller applications to leverage these capabilities through a common, open inter- face (i.e., a new “OpenFlow 2.0” API). Such a general, ex- tensible approach would be simpler, more elegant, and more future-proof than today’s OpenFlow 1.x standard. Figure 1: P4 is a language t Recent ch
- 25. What does a P4 program look like? L2 IPv4 ACLMyEncap IPv6 header_type ethernet_t { fields { dstAddr : 48; srcAddr : 48; etherType : 16; } } parser parse_ethernet { extract(ethernet); return select(latest.etherType) { 0x8100 : parse_vlan; 0x800 : parse_ipv4; 0x86DD : parse_ipv6; } } TCP IPv4 IPv6 MyEncapEth header_type my_encap_t { fields { foo : 12; bar : 8; baz : 4; qux : 4; next_protocol : 4; } } 23
- 26. What does a P4 program look like? L2 IPv4 ACLMyEncap IPv6 table ipv4_lpm { reads { ipv4.dstAddr : lpm; } actions { set_next_hop; drop; } } action set_next_hop(nhop_ipv4_addr, port) { modify_field(metadata.nhop_ipv4_addr, nhop_ipv4_addr); modify_field(standard_metadata.egress_port, port); add_to_field(ipv4.ttl, -1); } control ingress { apply(l2); apply(my_encap); if (valid(ipv4) { apply(ipv4_lpm); } else { apply(ipv6_lpm); } apply(acl); } 24
- 27. P4.org (http://p4.org) § Open-source community to nurture the language § Open-source software – Apache license § A common language: P416 § Support for various types of devices and targets § Enable a wealth of innovation § Diverse “apps” (including proprietary ones) running on commodity targets § With no barrier to entry § Free of membership fee, free of commitment, and simple licensing 25
- 29. The network should answer these questions 1. “Which path did my packet take?” 2. “Which rules did my packet follow?” 3. “How long did it queue at each switch?” 4. “Who did it share the queues with?” PISA + P4 can answer all four questions for the first time. At full line rate. Without generating any additional packets! 1 2 3 4
- 32. 30
- 33. What does this mean to you? • Improve your distributed apps’ performance with telemetry data • Ask the four key questions regarding your packets to network admins or cloud providers • Huge opportunities for Big-data processing and machine-learning experts • “Self-driving” network is not hyperbole 31
- 34. PISA: An architecture for high-speed programmable packet forwarding 32 event processing
- 35. What we have seen so far: Adding new networking features 1. New encapsulations and tunnels 2. New ways to tag packets for special treatment 3. New approaches to routing: e.g., source routing in data- center networks 4. New approaches to congestion control 5. New ways to manipulate and forward packets: e.g. splitting ticker symbols for high-frequency trading 33
- 36. What we have seen so far: World’s fastest middle boxes 1. Layer-4 load connection balancing at Tb/s – Replace 100s of servers or 10s of dedicated appliances with one PISA switch – Track and maintain mappings for 5 ~ 10 million HTTP connections 2. Stateless firewall or DDoS detector – Add/delete and track 100s of thousands of new connections per second – Include other stateless line-rate functions (e.g., TCP SYN authentication, sketches, or Bloomfilter-based whitelisting) 34
- 37. What we have seen so far: Offloading part of computing to network 1. DNS cache 2. Key-value cache [ACM SOSP’17] 3. Chain replication 4. Paxos [ACM CCR’16] and RAFT 5. Parameter service for DNN training 35
- 38. Example: NetCache Clients Key-Value Cache Query Statistics High-performance Storage Servers Key-Value Storage RackController L2/L3 Routing ToR Switch Data plane • Non-goal – Maximize the cache hit rate • Goal – Balance the workloads of backend servers by serving only O(NlogN) hot items -- N is the number of backend servers – Make the “fast, small-cache” theory viable for modern in-memory KV servers [Fan et. al., SOCC’11] • Data plane – Unmodified routing – Key-value cache built with on-chip SRAM – Query statistics to detect hot items • Control plane – Update cache with hot items to handle dynamic workloads
- 39. The “boring life” of a NetCache switch lue an ead age the m. one We or- ipf kes ck. .e., 0 32 64 96 128 9alue 6ize (Byte) 0.0 0.5 1.0 1.5 2.0 2.5 ThroughSut(B436) (a) Throughput vs. value size. (b) Throughput vs. cache size. Figure 9: Switch microbenchmark (read and update). one switch are organized to a snake structure. The switch is configured to provide 62 100Gbps ports, and two 40Gbps . The value et passes an ing for read egress stage l verify the ted to them. We use one server. We a full stor- ng to a Zipf server takes in the rack. titions (i.e., (a) Throughput vs. value size. 0 16. 32. 48. 64. CacKe 6ize 0.0 0.5 1.0 1.5 2.0 2.5 TKrougKSut(B436) (b) Throughput vs. cache size. Figure 9: Switch microbenchmark (read and update). one switch are organized to a snake structure. The switch is configured to provide 62 100Gbps ports, and two 40Gbps One can further increase the value sizes with more stages, recirculation, or mirroring. Yes, it’s Billion Queries Per Sec, not a typo J
- 40. And its “not so boring” benefits NetCache provides 3-10x throughput improvements. Throughput of a key-value storage rack with one Tofino switch and 128 storage servers. uQiforP ziSf-0.9 ziSf-0.95 ziSf-0.99 WorNloDd DisWribuWioQ 0.0 0.5 1.0 1.5 2.0 ThroughSuW(BQPS) 1oCDche 1eWCDche(servers) 1eWCDche(cDche)
- 41. NetCache is a key-value store that leverages &Billions of queries/sec a few usec latency even under workloads. &highly-skewed rapidly-changing in-network caching to achieve
- 43. Why data-plane programming? 1. New features: Realize your beautiful ideas very quickly 2. Reduce complexity: Remove unnecessary features and tables 3. Efficient use of H/W resources: Achieve biggest bang for buck 4. Greater visibility: New diagnostics, telemetry, OAM, etc. 5. Modularity: Compose forwarding behavior from libraries 6. Portability: Specify forwarding behavior once; compile to many devices 7. Own your own ideas: No need to share your ideas with others “Protocols are being lifted off chips and into software” – Ben Horowitz 41
- 44. • PISA and P4: The first attempt to define a machine architecture and programming models for networking in a disciplined way • Network is becoming yet another programmable platform • It’s fun to figure out the best workloads for this new machine architecture 42 My observations
- 45. Want to find more resources or follow up? • Visit http://p4.org and http://github.com/p4lang – P4 language spec – P4 dev tools and sample programs – P4 tutorials • Join P4 workshops and P4 developers’ days • Participate in P4 working group activities – Language, target architecture, runtime API, applications • Need more expertise across various fields in computer science – To enhance PISA, P4, dev tools (e.g., for formal verification, equivalence check, and many more …) 43
- 47. Watch the video with slide synchronization on InfoQ.com! https://www.infoq.com/presentations/ pisa-asic-p4