How to design your own chip?

How to design your own chip?
LibreCores
Free and Open Digital Hardware
Philipp Wagner
FrOSCon 2016

How to design your own chip? 22016-08-20
The story of
Ton Lear

The story of
Ton LearNot Real

Digital Hardware Design
Free and Open Source Silicon (FOSSi)
maker
open (source) hardware
What's the difference?

Design Entry: HDL

The Digital Hardware Design Flow
HDL Sources simulation
3rd
-party libraries
IP Cores
design
project

Simulation

HDL Sources
synthesis
simulation
3rd
-party libraries
IP Cores
FPGA
implementation
design
project

Chips?
Image source: https://deliciousgf.wordpress.com/2012/04/29/gluten-free-and-vegan-veggie-chips/

HDL Sources
synthesis
simulation
3rd
-party libraries
IP Cores
ASIC backend
FPGA
implementation
design
project

Chips!
image from https://pixabay.com/en/chips-potato-chips-unhealthy-thick-448746/, CC0 (public domain)

FOSSi Reality Check 1
The Simulation Check

Simulation: Required Ingredients
●
code to simulate
●
a simulator
●
testing

Write your code
●
Choose from the incumbents
– Verilog/SystemVerilog
– VHDL
●
or one of the new contenders
– Bluespec SystemVerilog
– Chisel (UC Berkely)
– MyHDL

Simulation
●
The “big 3” commercial simulators
– Incisive Enterprise Simulator/ NCSim (Cadence)
– ModelSim (Mentor)
– VCS (Synopsys)
●
FOSS solutions
– Icarus Verilog
– GHDL
– Verilator
●
Add a good waveform viewer
– gtkview

Testing & Verification
●
cocotb: Python-based test
●
vunit: VHDL unit testing
●
Open Source VHDL Verification Methodology
(OS-VVM)

“The Simulation Check”: Results
●
Hobbyist-Accessibility-Score: 4/5
●
FOSS score: 4/5
●
Fun score: 2/5

The FPGA Check

FPGA Design: Required Ingredients
●
code to simulate
●
a simulator
●
testing
●
a synthesis tool
●
an implementation tool
●
an FPGA board

FPGA Synthesis
●
Commercial
– Synopsys Synplify
– vendor tools (Xilinx, Altera, …)
●
free alternatives
– Verilog-to-Routing (VTR)
– Yosys

FPGA Implementation
●
Mostly vendor tools
– Xilinx ISE/Vivado, Altera Quartus, …
●
free alternatives
– IceStorm for Lattice iCE40
something to watch: Clifford @ FOSDEM 2016
https://archive.fosdem.org/2016/schedule/event/icestorm/

FPGA Boards: student (< 100 $)
DE0-Nano
$79
22,320 cells
Artix-7 35T
$99
33,280 cells
iCEstick
$20
1280 cells
All board pictures (c) by the manufacturers.

FPGA Boards: amateur (~ 500 $)
Nexys 4 DDR
ZTEX 2.1x
Altera DE2-115

FPGA Board: pro (> 1000 $)
Xilinx KC705
Xilinx VC707
Altera Cyclone V SoC
Development Kit

“The FPGA Check”: Results
●
Hobbyist-Accessibility-Score: 3/5
●
FOSS score: 2/5
●
Fun score: 4/5

The ASIC Check

ASIC Production: Required Ingredients
●
code to simulate
●
a simulator
●
a synthesis tool
●
really good testing & verification
●
a design kit
●
an implementation tool
●
money

The Design Kit
●
standard cell libraries, design rules, electrical
parameters, ...
●
get it from the foundry
●
bad: requires pretty tough NDA
●
good: it's usually for free (again, as in beer)

ASIC Implementation
●
Commercial options
– Synopsys Design Compiler
– Cadence Encounter Toolset
●
FOSS options
– qflow
– Coriolis2

Got Money?
[[user:]]viaWikimediaCommons,CCBY-SA

Need Money
●
Multi-Project Wafer
– available from multiple vendors, e.g. Europractice
– example
●
50 pcs Globalfoundries 40 nm
●
4 750 €/mm² (at least 9 mm² = 42 750 €) + packaging, etc.
●
up to 1500 KGates/mm²
– cheaper in older technologies (65nm + up)
●
eASIC
– pre-characterized ASICs “configured” with one custom
layer

“The ASIC Check”: Results
●
Hobbyist-Accessibility-Score: 0.1/5
●
FOSS score: 1/5
●
Fun score: 1-5/5
●
Satisfaction score: 10/5
let's do it
anyways?

Don't celebrate alone.
PicturebyWeI-chiehChiu(flickr),CCBY-SA

Join the party!
The bachelor party. Signed Louis Wain. Oil on canvas, 29.5 x 60 cm (public domain, via Wikimedia Commons)

The Community Check

Required ingredients
●
Let others participate
●
Build on existing work
●
Learn, teach and exchange ideas

How to live together?
photobyPrskavka(WikimediaCommons),publicdomain

Choose a license
●
Permissive
●
Weak Copyleft
●
Strong Copyleft

Licensing: Permissive
●
without patent clause
– MIT and BSD widely used
– example project: RISC V
●
with patent clause
– new: SolderPad License by Andrew Katz

Licensing: Weak Copyleft
●
File-based copyleft
– OHDL: Julius Baxter for mor1kx, based on MPLv2
●
library copyleft
– LGPL
●
commonly used on opencores.org
●
what's “linking” in a hardware context?

Licensing: Strong Copyleft
●
GPL
– GPLv3 uses “hardware-friendly” language
●
lesson learned from open sourcing SPARC
– example user: Gaisler LEON3 (GPLv2+)
– implications not fully understood
●
ASIC (design kit)?
●
FPGA (built-in primitives)?

OpenCores.org
photobyAndreGlechikoff(Flickr),CCBY-SA

Community hub needed
●
publish your work
●
find code to re-use
●
learn, teach, inspire

Introducing LibreCores

LibreCores Goals
●
Documentation
– How to get started?
– Best practices
– Success stories
●
News & Discussion
– Planet LibreCores
●
Project repository
– a directory of FOSSi projects
– with quality indicators

LibreCores: Where are we today?
●
Documentation
– How to get started?
– Best practices
– Success stories
●
News & Discussion
– Planet LibreCores
●
Project repository
– a directory of FOSSi projects
– with quality indicators
First content online
online!
to be released
in October!

Who's behind all that?
●
OpenRISC community
●
Group formed ~2 years ago
●
First plans presented at ORCONF
2015 at CERN
●
since end of 2015: FOSSi
Foundation, CiC (UK) to provide
shared legal entity

So: How to design your own chip?
●
join an existing project: OpTiMSoC, lowrisc, …
●
fire up your editor: most tools are free (as in
beer)
●
FPGA designs are within reach
●
ASICs only for some of us

Conference Announcement
●
October 7 – 9
●
University of Bologna, in Bologna, Italy
●
No admission fee (but please register)
visit www.orconf.org for more info & registration

me
Philipp Wagner
mail@philipp-wagner.com
www.philipp-wagner.com
let's talk!
FOSSi Foundation
discussion@lists.librecores.org
www.fossi-foundation.org
#librecores on freenode
You can freely remix this presentation under the
terms of the Creative Commons BY-SA 4.0 license.

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