Project ACRN GPIO mediator introduction
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This document introduces GPIO and GPIO virtualization in ACRN. It discusses: 1. GPIO hardware consists of pin configuration logic, GPIO logic blocks, and multiplexers that allow pins to take on different functions like GPIO, SPI, I2C. 2. GPIO virtualization in ACRN follows the virtio specification and allows each VM to access a virtual GPIO chip with a configured number of pins mapped to physical pins. 3. GPIO IRQ virtualization allows VMs to request, apply, and be notified of IRQ events on their virtual GPIO pins, which are forwarded by the hypervisor to the corresponding physical pins.
![virtio-gpio how to access
GPIO from userspace
sysfs:
For example :
cd /sys/class/gpio
echo 9 > export
echo 0 > gpio9/value
cat gpio9/value
echo 9 > unexport
char device
For example :
void write_value(unsigned offset, int value) {
struct gpiohandle_request req;
int ret, fd;
âŠ
fd = open(â/dev/gpiochip0â, O_RDWR);
memset(&req, 0, sizeof(req));
req.lineoffsets[0] = offset;
req.default_values[0] = value;
req.flags = GPIOHANDLE_REQUEST_OUTPUT;
req.lines = 1;
ret = ioctl(line->chip->fd, GPIO_GET_LINEHANDLE_IOCTL, &req);
âŠ
}](https://image.slidesharecdn.com/projectacrngpiomediatorintroduction-200605184000/85/Project-ACRN-GPIO-mediator-introduction-13-320.jpg)
![Usage
â« <gpio resources>
<@controller_name{offset|name[=mapping_name]:offset|name[=mapping_name]:âŠ}@controller_name{âŠ}âŠ]>
E.g.
1. Map native gpio numbers are 1 and 6, plus one gpio its name is âresetâ to frontend, all of them are defined in
GPIO controller 0
<@gpiochip0{1:6:reset}>
2. Map native gpio numbers are 1 and 6, which are in gpio controller 0, and native gpio numbers are 2 and 7, which
are in gpio controller 1.
<@gpiochip0{1:6}@gpiochip1{2:7}>
â« [ | acpi resources]
[|@device_name{gpio_identifier[=apci name]:gpio_identifier[=apci name]âŠ@device_name{âŠ}âŠ}]
E.g.
1. Usb FE driver wants to access âresetâ gpio, and it is GPIO controller 0âs âresetâ GPIO in native.
<@gpiochip0{reset}|@usb{gpiochip0_reset}
2. Usb FE driver wants to access âresetâ gpio, and its offset is 2 in the native GPIO controller 0.
<@gpiochip0{2}|@usb{gpiochip0_2=reset}
âą](https://image.slidesharecdn.com/projectacrngpiomediatorintroduction-200605184000/85/Project-ACRN-GPIO-mediator-introduction-15-320.jpg)
Project ACRN GPIO mediator introduction
- 1. ACRN GPIO Mediator Introduction LIU Long Liu, Long <Long.Liu@intel.com> 05/27/2020
- 2. Table of Contents PART 1: GPIO Overview PART 2: GPIO Virtualization PART 3: GPIO IRQ Virtualization PART 4: Q & A
- 3. PIN & GPIO âą PINs are equal to pads, fingers, balls or whatever packaging input or output line you want to control. PINs can sometimes be software-configured in various ways, mostly related to their electronic properties, such as biasing and drive strength, when used as inputs or outputs. PINs also support multiplexing, it means device can set PINs to one specific function, such as GPIO, SPI or I2C. âą GPIO stands for âGeneral Purpose Input/Outputâ, is a flexible software-controlled digital signal. Each GPIO represents a bit connected to a particular pin, or "ball" on Ball Grid Array(BGA) packages and it supports some capabilities including GPIO enabled/disabled, input values are readable(typically high or low), output values are writable/readable and input values can often be used as IRQs (typically for wakeup events). https://en.wikipedia.org/wiki/General-purpose_input/output
- 4. GPIO hardware logic block SOC Pin Configuration Logic Block SPI Logic Block I2C Logic Block Multiplexer Physical Pin GPIO Logic Block âą Type1 - GPIO, Multiplexer and Pin Configuration are isolated, and each model has its own MMIO. âą Type 2 - GPIO, Multiplexer and Pin Configuration are merged into single controller, all of them has same MMIO range. GPIO Logic Block Type 2 Type 1
- 5. GPIO subsystem architecture static struct pinmux_ops foo_pmxops = { .get_functions_count = foo_get_functions_count, .get_function_name = foo_get_fname, .get_function_groups = foo_get_groups, .set_mux = foo_set_mux, .strict = true, }; static struct pinconf_ops foo_pconf_ops = { .pin_config_get = foo_pin_config_get, .pin_config_set = foo_pin_config_set, .pin_config_group_get = foo_pin_config_group_get, .pin_config_group_set = foo_pin_config_group_set, }; static struct gpio_chip foo_gpio_chip = { .get_direction= foo_get_direction, .direction_input = foo_direction_input, .direction_output = foo_direction_output, .get = foo_get, .set = foo_set, .base = 0, .ngpio = 64, ⊠};
- 6. GPIO virtualization âą Full virtualization solution needs to provide full functionality registers to UOS, but lots of them have no real functionality due to only assigned virtual GPIO links to physical GPIO, and another risk is that there is no common physical GPIO controller as reference for all UOS platforms. âą Para virtualization solution can be as one common solution for all future platforms. âą GPIO virtualization follows the Virtual I/O Device (virtio) specification. âą The virtual pins information and the number of pins can be configured through acrn-dm command line. âą No kernel space mediator support due to high risk for SOS kernel stability.
- 8. Native GPIO
- 10. virtio-gpio virtual gpio chip âą Each UOS has only one GPIO chip instance, its number of GPIOs is based on acrn-dm command line and GPIO base always start from 0. âą Each acrn-dm may be able to access one or more native GPIO chips and all GPIOs are exclusive.
- 11. virtio-gpio how to access GPIO in UOS int xx_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) { struct gpio_desc *desc; int ret, val; ⊠desc = gpiod_get_index(dev->dev, "reset-gpios", 0,GPIOD_IN); or desc = gpiod_get_index(dev->dev, NULL, 0, GPIOD_IN); if (!desc || gpiod_direction_input(desc)) goto err; val = gpiod_get_value(desc); ... }
- 12. virtio-gpio gpio mapping GPIO Description table Native GPIO name Native GPIO chip Native GPIO offset Virtual GPIO offset reset 0 10 2 shutdown 0 100 0
- 13. virtio-gpio how to access GPIO from userspace sysfs: For example : cd /sys/class/gpio echo 9 > export echo 0 > gpio9/value cat gpio9/value echo 9 > unexport char device For example : void write_value(unsigned offset, int value) { struct gpiohandle_request req; int ret, fd; ⊠fd = open(â/dev/gpiochip0â, O_RDWR); memset(&req, 0, sizeof(req)); req.lineoffsets[0] = offset; req.default_values[0] = value; req.flags = GPIOHANDLE_REQUEST_OUTPUT; req.lines = 1; ret = ioctl(line->chip->fd, GPIO_GET_LINEHANDLE_IOCTL, &req); ⊠}
- 14. GPIO IRQ Virtualization /dev/gpiochipN Virtio-GPIO DM Virtio-GPIO FE driver UOS IRQ consumer Request IRQ Request IRQ Apply the IRQ IRQ event notification Send IRQ information Invoke consumerâs IRQ handler Free IRQ Release IRQ Free the IRQ line event Send IRQ information Return fd Start to poll IRQ event IRQ event notification IRQ event notification Invoke consumerâs IRQ handler ⊠Allocate buff Allocate buff ⊠âŠ
- 15. Usage â« <gpio resources> <@controller_name{offset|name[=mapping_name]:offset|name[=mapping_name]:âŠ}@controller_name{âŠ}âŠ]> E.g. 1. Map native gpio numbers are 1 and 6, plus one gpio its name is âresetâ to frontend, all of them are defined in GPIO controller 0 <@gpiochip0{1:6:reset}> 2. Map native gpio numbers are 1 and 6, which are in gpio controller 0, and native gpio numbers are 2 and 7, which are in gpio controller 1. <@gpiochip0{1:6}@gpiochip1{2:7}> â« [ | acpi resources] [|@device_name{gpio_identifier[=apci name]:gpio_identifier[=apci name]âŠ@device_name{âŠ}âŠ}] E.g. 1. Usb FE driver wants to access âresetâ gpio, and it is GPIO controller 0âs âresetâ GPIO in native. <@gpiochip0{reset}|@usb{gpiochip0_reset} 2. Usb FE driver wants to access âresetâ gpio, and its offset is 2 in the native GPIO controller 0. <@gpiochip0{2}|@usb{gpiochip0_2=reset} âą
- 16. Q & A