![VLSI Design
VLSI Design
Dynamic CMOS
[Adapted from Rabaey’s Digital Integrated Circuits ©2002 J Rabaey et al ]
Dynamic CMOS.1
[Adapted from Rabaey s Digital Integrated Circuits, ©2002, J. Rabaey et al.]](https://image.slidesharecdn.com/dynamiccmos-221104191913-5eb450c7/85/Dynamic-CMOS-pdf-1-320.jpg)
Dynamic CMOS.pdf
- 1. VLSI Design VLSI Design Dynamic CMOS [Adapted from Rabaey’s Digital Integrated Circuits ©2002 J Rabaey et al ] Dynamic CMOS.1 [Adapted from Rabaey s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
- 2. Dynamic CMOS ( ‰ In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. z fan-in of N requires 2N devices ‰ Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. i l N 2 t i t z requires only N + 2 transistors z takes a sequence of precharge and conditional evaluation phases to realize logic functions Dynamic CMOS.2
- 3. Dynamic Gate M CLK CLK M In1 Mp CLK Out CL Out CLK Mp In1 In2 PDN In3 CL A B C Me CLK CLK Me Two phase operation Precharge (CLK = 0) Dynamic CMOS.3 Precharge (CLK 0) Evaluate (CLK = 1)
- 4. Dynamic Gate M CLK CLK M off In1 Mp CLK Out CL Out CLK Mp on 1 !((A&B)|C) In1 In2 PDN In3 CL A B C Me CLK CLK Me off on Two phase operation Precharge (CLK = 0) Dynamic CMOS.4 g ( ) Evaluate (CLK = 1)
- 5. Conditions on Output O f ‰ Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. ‰ Inputs to the gate can make at most one transition during evaluation. ‰ Output can be in the high impedance state during and p g p g after evaluation (PDN off), state is stored on CL Dynamic CMOS.5
- 6. Properties of Dynamic Gates ‰ Logic function is implemented by the PDN only ‰ Logic function is implemented by the PDN only z number of transistors is N + 2 (versus 2N for static complementary CMOS) z should be smaller in area than static complementary CMOS z should be smaller in area than static complementary CMOS ‰ Full swing outputs (VOL = GND and VOH = VDD) ‰ Nonratioed - sizing of the devices is not important for proper functioning (only for performance) F t it hi d ‰ Faster switching speeds z reduced load capacitance due to lower number of transistors per gate (Cint) so a reduced logical effort z reduced load capacitance due to smaller fan-out (Cext) z no Isc, so all the current provided by PDN goes into discharging CL z Ignoring the influence of precharge time on the switching speed of Dynamic CMOS.6 z Ignoring the influence of precharge time on the switching speed of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL
- 7. Properties of Dynamic Gates, con’t ‰ Power dissipation should be better ‰ Power dissipation should be better z consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating z lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two) z by construction can have at most one transition per cycle no z by construction can have at most one transition per cycle – no glitching ‰ But power dissipation can be significantly higher due to p p g y g z higher transition probabilities z extra load on CLK ‰ PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn z low noise margin (NM ) Dynamic CMOS.7 z low noise margin (NML) ‰ Needs a precharge clock
- 8. Dynamic Behavior 2.5 CLK Out Evaluate 1.5 In1 In2 Out Evaluate 0.5 In3 In4 In & CLK Out -0.5 0 0.5 1 CLK 4 Out Time ns Precharge Time, ns #Trns VOH VOL VM NMH NML tpHL tpLH tp Dynamic CMOS.8 6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps
- 9. Cascading Dynamic Gates CLK V CLK CLK Out1 I Mp Mp CLK Out2 In CLK In Me Me CLK Out1 VTn t Out2 ΔV t Only a single 0 → 1 transition allowed at the Dynamic CMOS.9 inputs during the evaluation period!
- 10. Domino Logic Mp CLK Out1 Mp CLK Out2 1 → 1 1 → 0 In1 In2 PDN In4 PDN In 1 → 0 0 → 0 0 → 1 In3 Me CLK In5 Me CLK Dynamic CMOS.10
- 11. Why Domino? CLK In1 Ini PDN Inj Ini Inj PDN Ini PDN Inj Ini PDN Inj CLK j j j j Dynamic CMOS.11
- 12. Properties of Domino Logic ‰ Only non-inverting logic can be implemented, fixes include z can reorganize the logic using Boolean transformations z use differential logic (dual rail) z use np-CMOS (zipper) p ( pp ) ‰ Very high speed z tpHL = 0 pHL z static inverter can be optimized to match fan-out (separation of fan-in and fan-out capacitances) Dynamic CMOS.12
- 13. Differential (Dual Rail) Domino M CLK M CLK M M on off A Mp CLK !Out = !(AB) Mkp CLK Out = AB Mkp Mp 1 0 1 0 A B !A !B Me CLK Due to its high-performance, differential domino is very popular and is used in several commercial Dynamic CMOS.13 very popular and is used in several commercial microprocessors!
- 14. np-CMOS (Zipper) Mp CLK Out1 Me !CLK 1 → 1 1 0 In1 In2 PDN In4 PUN In5 1 → 0 0 0 In3 Me CLK Mp !CLK Out2 (to PDN) 0 → 0 0 → 1 to other PDN’s to other PUN’s Only 0 → 1 transitions allowed at inputs of PDN O l 1 0 t iti ll d t i t f PUN Dynamic CMOS.14 Only 1 → 0 transitions allowed at inputs of PUN
- 15. How to Choose a Logic Style f ( ) ‰ Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing Style # Trans Ease Ratioed? Delay Power 4-input NAND Comp Static 8 1 no 3 1 CPL* 12 + 2 2 no 4 3 domino 6 + 2 4 no 2 2 + clk DCVSL* 10 3 yes 1 4 * Dual Rail ‰ Current trend is towards an increased use of complementary static CMOS: design support through DA t l b t bl t lt li Dynamic CMOS.15 tools, robust, more amenable to voltage scaling.