Analog, IO Test Chip Validation

Editor's Notes

• #6: What happens if we apply high voltage ? If voltages higher than the core voltage are applied at input pad, then it may cause damage to device or failure to power up, where comes the need to interface through Ios Current technology trends demands more functionality and hence more IO pads are necessited
• #8: in order to keep the core safe , there should be something which observes the behavior of current that is supplied to core in order to avoid the damages. To do so we have IO Rings design in between the external world and core so these leads to validate the IO design Validation and testing of the Input-Output frame functionality in terms of timing parameters, signal strength in order to meet the design specs listed below Duty cycle rise / fall times propagation delays Slew rates Hysteresis matching pull-up / pull-down resistance It also involves simulation and characterization of different technologies and their corresponding Library cells IPs ADC Crystal oscillator IO pads Voltage regulator
• #11: Compensation cell role and definition is here -  These are cells used in the I/O periphery for the slew rate control. Compensation block has only an enable pin and the output pins. This block senses the change and generates a common code for all the slew rate controlling devices.
• #13: ESD ESD protection is very crucial in order to save on-chip from unwanted surges that gets developed on the pins due to unprecedented external sources such as human contact, etc. with the pin An external off-chip signal can have voltage ranges much beyond and higher than the normal CMOS operating voltages, an input ESD (electrostatic discharge) protection is required for the buffers. After passing through the ESD Protection block, the signal is subjected to the Input buffer These largely accumulated charges can destroy and hamper the normal functioning of transistors, therefore a mechanism is needed which can quickly and effectively discharge unwanted charges Schmitt Sometimes an input signal to a digital circuit doesn't fit directly as per the digital signal constraints in a given specified voltage range. Due to unwanted jitters, the input signal may have slow rise and/or fall times, delayed input response, or may have acquired some noise that could be sensed by further input circuitry Schmitt trigger has an inverter-like voltage transfer characteristics curve, but with two different logic threshold voltages for increasing and decreasing input signals. With this noise cancellation property, the Schmitt Trigger circuit can be utilized for the detection of low-to-high and high-to-low switching events even in noisy environments Level shifter I/O buffers are operated with different voltage levels than the core voltage level, so in order to shift the voltage level up or down as per the signal routing from core to I/O or vice-versa, special type of level shifter circuits are implemented for low power and proper functioning of the circuit The dc level converter needs some design consideration in the sense that it has to prevent the static power dissipation and leakage current A simple cross coupled inverter is used as level converter in order to prevent any unnecessary static current path when both PMOS and NMOS are simultaneously ON
• #14: To limit switching noise (L * dI/dt), for all the buffers (Slow / Medium / Fast / Very Fast), the impedance of the driver is controlled through control bits which are generated by compensation cell The impedance control feature makes the output current drive relatively constant and helps to match output impedance of the bidirectional cells with transmission line (or interconnect) across variations of temperature, power supply and process The drive capability of an output buffer should be such that it can achieve the pre-requisite rise and fall times under varying capacitive load conditions. Normally the drive capability of I/O buffers is as high as 8mA or 9mA Test pin Test-pin block is used at the output section of the core chip and is connected between the core and pre-driver (where, pre-driver block is basically used for slew rate control and corresponding rise and fall time calculation) The Test-pin block consists of a multiplexer, to select the test mode or normal operating mode, a series of inverters to generate two signals NIN and PIN at the output of this block for slew rate control measurements The signal at NIN rises faster than PIN while signal at PIN falls faster than NIN Pre-Driver A fast transition of the signal at the output pad tends to introduce frequencies in Ultra High Frequency (UHF) range into the off chip load being fed. This sometimes becomes undesirable in applications such as if the signal is fed to a Television chip, cellular phones, radios, etc. The signals in the UHF range appear as noise to the driving section A pre-driver block is used for controlled switching of current signal at the output pad, thereby acting as an active slew rate control circuitry. A controlled switching results in reduced dI/dt power supply noise. The source of this noise is the inductive voltage drop, i.e. V = L(dI/dt) at the power rails where inductance is introduced by the package pins   This Pre-driver block acts as Slew rate control circuits which artificially limit the rate of current switching thereby limiting the UHF interference. Basic approach for achieving controlled slew rate is to break the output driving transistors into different parallel transistors and switch the stages sequentially one after the other with some delay Output driver An Output buffer must have sufficient drive capability to achieve adequate rise and fall times into a given capacitive load. To achieve a specified functionality of the output buffer, different types of output stages are used at the output section Push Pull stage Open Drain output stage Usually, a plain inverter stage at the output of buffer stages is avoided. The Miller capacitance associated between the Gates (G) and the Source (S)-Drain (D) diffusion regions of ‘p’ and ‘n’ transistors can result in oscillations at the output in series with the load inductance causing Short circuit power dissipation Output stage: A push pull stage consists of p and n transistors at the output pad for sourcing and sinking respectively , where each of transistors is controlled through a different chain of tapered inverters fed after buffering Often the tristated output is put to a particular logic level instead of letting the bus float .Either logic low or high can be made at the output using the pull up or pull down transistors Normally the NMOS transistor is used for pull down and PMOS transistor for pull up