Hsien-Hsin Sean Lee, Ph.D.

computer architecture logic design sram dram risc logic synthesis caches memory hierarchy combinational logic logic minimization cmos nor nand inverter coherence cmp disk prefetch p6 microarchitecture vliw epic cisc sequential logic fsm program execution state machine finite state machine netburst mips instruction set architecture isa rom memory architecture bit cells memory raid pentium pro pentium 4 multicore registers many core chip multiprocessors symmetric multiprocessor chip multiprocessor smp parallel architecture program control instruction level parallelism ilp performance data path microcode control flow speculation instruction execution branch predictors processor instruction fetch unit ibm360/91 tomasulo algorithm scoreboard cdc6600 reorder buffer register renaming rat rob program counter directory based protocol demorgan law pos sop canonical function k-map karaugh map quinn-mccluskey algorithm shifter mixed logic multiplexor mux timing diagram decoder encoder gate comparator parity checker adder subtractor barrel shifter multiplier snoop protocol toggle celled multiprocessor snooping coherence directory-based cohference static scheduling data speculation explicit parallel instruction computing counter computer engineering binary number conversion hex flip-flops register switches and switch logic gates xor boolean algebra