The document summarizes key aspects of the P6 microarchitecture used in processors like the Pentium Pro, Pentium II, and Pentium III. It describes the system architecture with separate front-side and back-side buses. It then details the instruction fetch, decode, register renaming, out-of-order execution, memory handling, and retirement stages of the processor pipeline. Diagrams illustrate the branch prediction, reservation stations, reorder buffer, and memory order buffer components that enable speculative and out-of-order execution in the P6.
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