High-Level Synthesis Skill Development Needs - IEDEC

Editor's Notes

• #3: The advances in silicon capacity on a chip are far outpacing advances in the ability to utilize that silicon. This is extremely costly, in that teams are faced with the choice of compromising on either schedule, engineering costs, or silicon capabilities in order to meet their primary goals. Causes of this growing gap can be found in design, verification, and implementation. However one key root cause can be traced to the abstraction at which design is performed.
• #6: This chart depicts the approximately ten-fold hardware design productivity increase per decade, from the roughly one gate-equivalent per day of the early 70's to the roughly one thousand gate-equivalent per day at the turn of the century. To continue this trajectory requires transitioning design to yet another higher level of abstraction; system-level synthesis.
• #7: Cadence enables TLM design with its C-to-Silicon Compiler. C-to-S enables a single specification of functional intent – both control and datapath together – using industry standard TLM. It embeds RTL Compiler, production-proven global synthesis, to ensure that the optimizations it makes will hold up during synthesis and implementation. It also provides intuitive graphical feedback that utilizes this information to guide you to make better implementation decisions in order to meet the goals of your target device. Finally, because it is linked to the Cadence Silicon Realization flow, ECOs are automated throughout the entire flow.
• #8: Design results from:“Building a NAND flash controller with high-level synthesis”http://www.eetimes.com/design/memory-design/4238287/Building-a-NAND-flash-controller-with-high-level-synthesisInitially used a software implementation of BCH code. The decoder was taking up 99% of the area because values were being stored in huge look-up tables that were implemented in hardware as arrays.Encodermanually performed unfolding for the parity calculation and shortened the path length for a sequence of XOR operations. Decoder: reduced the array size of the logarithm and anti-logarithm values of GF. Only a small part of the logarithm values were kept, dedicated arithmetic hardware for multiplication and addition operationsThe Berlekamp iterative algorithm was replaced by the Berlekamp tree algorithm with a set of formulas. For the Chien search algorithm, we skipped unnecessary attempts at the root to improve the latency of decoding operations.
• #9: Polytechnic University of Turin in Italy.“Modeling and optimization of embedded systems,” taught by Professor LucianoLavagno. Part of their curriculum towards a degree in Electronic Engineering.Columbia University. CSEE 6868E: System-on-Chip Platforms, led by Professor Luca Carloni and Dr. Michele Petracca. Targeted toward utilizing SystemC and TLM to design SoC hardwareUniversity of Aizu in Japan. SYA08 – Electronic Design Automation for System-Level Design, led by Professor Hiroshi Saito [11]. First course offered in Japan that teaches high-level synthesis for hardware design, and the goal is to nurture the next generation of system-level engineers
• #10: Polytechnic University of Turin in Italy.“Modeling and optimization of embedded systems,” taught by Professor LucianoLavagno. Part of their curriculum towards a degree in Electronic Engineering.Columbia University. CSEE 6868E: System-on-Chip Platforms, led by Professor Luca Carloni and Dr. Michele Petracca. Targeted toward utilizing SystemC and TLM to design SoC hardwareUniversity of Aizu in Japan. SYA08 – Electronic Design Automation for System-Level Design, led by Professor Hiroshi Saito [11]. First course offered in Japan that teaches high-level synthesis for hardware design, and the goal is to nurture the next generation of system-level engineers
• #11: Polytechnic University of Turin in Italy.“Modeling and optimization of embedded systems,” taught by Professor LucianoLavagno. Part of their curriculum towards a degree in Electronic Engineering.Columbia University. CSEE 6868E: System-on-Chip Platforms, led by Professor Luca Carloni and Dr. Michele Petracca. Targeted toward utilizing SystemC and TLM to design SoC hardwareUniversity of Aizu in Japan. SYA08 – Electronic Design Automation for System-Level Design, led by Professor Hiroshi Saito [11]. First course offered in Japan that teaches high-level synthesis for hardware design, and the goal is to nurture the next generation of system-level engineers