11. Input-Output Organization.pdf
- 1. 11-4 Modes of Transfer Data transfer to and from peripherals 1) Programmed I/O 2) Interrupt-initiated I/O 3) Direct Memory Access (DMA) 4) I/O Processor (IOP) Example of Programmed I/O Interrupt-initiated I/O 1) Non-vectored : fixed branch address 2) Vectored : interrupt source supplies the branch address (interrupt vector)
- 2. Initial Operation of ISR 1) Clear lower-level mask register bit 2) Clear interrupt status bit IST 3) Save contents of processor registers 4) Set interrupt enable bit IEN 5) Proceed with service routine Final Operation of ISR 1) Clear interrupt enable bit IEN 2) Restore contents of processor registers 3) Clear the bit in the interrupt register belonging to the source that has been serviced 4) Set lower-level priority bits in the mask register 5) Restore return address into PC and set IEN 11-6 Direct Memory Access (DMA) DMA DMA controller takes over the buses to manage the transfer directly between the I/O device and memory (Bus Request/Grant) CPU BR BG DBUS WR ABUS RD Bus request Bus grant Address bus Write Read Data bus High-impedance (disable) when BG is enabled DMA Controller BR BG
- 3. Transfer Modes 1) Burst transfer : Block 2) Cycle stealing transfer : Byte DMA Controller ( Intel 8237 DMAC ) : DMA Initialization Process 1) Set Address register : memory address for read/write 2) Set Word count register : the number of words to transfer 3) Set transfer mode : read/write, burst/cycle stealing, I/O to I/O, I/O to Memory, Memory to Memory Memory search I/O search 4) DMA transfer start : next section 5) EOT (End of Transfer) : Interrupt Control logic CS Data bus buffers Control register Data bus DMA select Internal bus RS Interrupt BG BR RD WR Register select Read Write Bus request Bus grant Interrupt Address register Word count register Address bus buffers Address bus DMA request DMA Acknowledge to I/O device
- 4. DMA Transfer (I/O to Memory) 1) I/O Device sends a DMA request 2) DMAC activates the BR line 3) CPU responds with BG line 4) DMAC sends a DMA acknowledge to the I/O device 5) I/O device puts a word in the data bus (for memory write) 6) DMAC write a data to the address specified by Address register 7) Decrement Word count register 8) Word count register = 0 EOT interrupt CPU 9) Word count register 0 DMAC checks the DMA request from I/O device I/O Peripheral device DMA acknowledge Address select CPU Interrupt Address Data BG BR RD WR Random access memory (RAM) Address Data RD WR Direct memory access (DAM) controller Interrupt Address Data RD WR BG RS DS BR DMA request Read control Write control Address bus Data bus