2. DIRECT MEMORY ACCESS(DMA)
In DMA there is direct communication between
memory and the peripheral devices.
CPU is idle and has no control over the memory
buses.
DMA controller uses buses and transfer the
data directly between I/O devices and memory.
4. BR(Bus Request) signal is used by DMA controller to
request CPU for the buses.
When this input is active, the CPU terminates the execution of
the current instruction and places the address bus, data bus
and read write lines into a high Impedance state. High
Impedance state means that the output is disconnected(open
circuit)
CPU then activates BG(Bus Grant) signal to
acknowledge BR signal.
DMA now has full control over the buses and
perform the transfer.
When the DMA terminates the transfer, it disables the
Bus Request (BR) line. The CPU disables the Bus Grant
(BG), takes control of the buses and return to its
normal operation.
5. TRANSFER CAN BE PERFORMED IN TWO WAYS:
Burst Transfer
Cycle Stealing
In burst transfer, a number of memory word is
transfer in a continuous burst. It is done while
communicating with fast devices and can’t be
stopped or slow down.
• Cycle stealing allows the DMA controller to transfer one
data word at a time, after which it must returns control of the
buses to the CPU.
CPU delays it operation for one cycle during which DMA
transfer takes place.
7. DMA CONTROLLER
It communicates with CPU through data bus and
control lines.
Registers in DMA are selected by CPU by enabling DS
and RS.
RD and WR signals are for read and write
operation.
The CPU initializes the DMA through the data bus. Once the
DMA receives the start control command, it can transfer
between the peripheral and the memory
When BG=0 CPU can communicate with DMA
register for read or write operation.
When BG=1 DMA communicate directly with the
8. DMA CONTROLLER
It has three register: address, word count and control
register.
Address register contain address which specify the
location of memory to read or write.
It is incremented after each word is transferred into
memory.
Word count register holds the number of words to be
transferred.
It is decremented by one after each word is
transferred into memory and regularly check for
zero.
9. CONTROL REGISTER SPECIFY THE MODE OF
TRANSFER.
DMA is first initialized by CPU. After that DMA
continue to transfer data.
CPU initialize the DMA by sending the following
information through the data bus:
Starting address of memory block for read or write.
The word count or number of words to read or write.
Control to specify mode such as read or write.
Control to start DMA
10. ONCE DMA IS INITIALIZED, CPU STOP
COMMUNICATING WITH DMA
UNLESS IT RECEIVE INTERRUPT
SIGNAL OR IF IT WANTS TO CHECK
HOW MANY WORDS HAS BEEN
TRANSFERRED.
![DIRECT MEMORY ACCESS
[DMA]](https://image.slidesharecdn.com/directmemoryaccessdma-250326150415-c07251ec/85/Direct-Memory-Access-DMA-pptx-ppt-ppt-ppt-1-320.jpg)
