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논리회로 설계실험담당교수 : 전재욱담당조교 : 석민식, 송지호
2
1 Analog & digitalSub. Contents.1.1 Analog & Digital1.2 Analog1.3 Digital3
1.1 Analog & Digital4AnalogDigitalVVTT00
1.2 Analog5Input SignalOutput Signal양적인 비례 관계
1.3 Digital6Input SignalOutput Signal논리적인 비례 관계
2 Binary digit operationSub. Contents.2.1 Binary System2.2 Boolean Algebra2.3 Venn Diagram7
2.1 Binary System Binary System0과 1로 이루어진 수표기법 : 10001001(2)Decimal to Binary Conversion826532   … 1216   … 02128 64 32 16   8   4   2  11000001208   … 00   1   0   0    0   0   0  1Binary :204   … 0202   … 001   … 0
2.2 Boolean Algebra Logical Sum : +► A + B = Y 0 + 0 = 0 0 + 1 = 1 1 + 1 = 1 Logical Product : •► A • B = Y 0 • 0 = 0 0 • 1 = 0 1 • 1 = 1 Logical Not : /, ‾,n,`► A ( /A, nA, A`) = Y 0 = 1 1 = 09Truth Table
2.2 Boolean Algebra – Single Variable AND  X • 0 = 0  X • 1 = X  X • 0 = 0  X • X = 0 NOT  X = X OR  X + 0 = X  X + 1 = 1  X + X = X  X + X = 110
2.2 Boolean Algebra – Multi Variable Commutative Law X + Y = Y + X X • Y = Y • X Associative Law X + (Y + Z) = (X + Y) + Z = X + Y + ZX(Y • Z) = X • Y • Z = XYZ Distributive LawX(Y+Z) = X • Y + X • Z = XY + XZ(X + W)(Y + Z) = X • Y + X • Z + W • Y + W • Z = XY + XZ + WY + WZOther LawX + XY = XX + XY = X + Y11
2.3 Venn Diagram12XYXYXY
2.4 De-Morgan Law13A + B = A • BA • B = A + B
3 Gate symbolSub. Contents.3.1 Buffer & NOT Gate3.2 AND & NAND Gate3.3 OR & NOR Gate3.4 XOR & ExOR Gate3.5 Relativity Theorem14
3.1 Buffer & NOT Gate15NOT GateBufferInputOutputInputOutput
3.1 Buffer & NOT Gate                          - Analog Not Gate Circuit16B = 0COutputInputBEB = 1
3.2 AND & NAND Gate17AND GateNAND GateInput AInput AOutputOutputInput BInput B
3.2 AND & NAND Gate                         - Analog AND Gate Circuit18BC=>CEBE< TR >< Switch >Input AInput BOutput
3.3 OR & NOR Gate19OR GateNOR GateInput AInput AOutputOutputInput BInput B
3.3 OR & NOR Gate                           - Analog OR Gate Circuit20Input AInput BOutput
3.4 XOR & ExOR Gate21ExOR(XOR) GateExNORGateInput AInput AOutputOutputInput BInput BA ⊙ B = YA   B = Y
3.5 Relativity TheoremA + B = B + AA+(B+C) = (A+B)+CA(B+C) = A•B+A•CA+0=AA+1=1A+A=AA+A=1A=AA+B=A•BA+A•B=AA+A•B=A+BA•B=B•AA(B•C)=(A•B)CA+B•C=(A+B)(A+C)A•1=AA•0=0A•A=AA•A=0A=AA•B=A+BA(A+B)=AA(A+B)=A•B22
4 Combinational Logic CircuitSub. Contents.4.1 Combinational Logic4.2 Half-Adder4.3 Full-Adder4.4 Half-Subtracter4.5 Full-Subtracter4.6 Subtraction4.7 Adder-Subtracter23
4.1 Combinational Logic24Input AInput BOutputInput CInput D(A+B) (CD) = Output
4.2 Half-Adder25Input ASUMInput BCARRY(A    B) = SUMA • B = CARRY
4.2 Half-Adder26   0+000   1+001   0+101   1+111HalfAdderInput ASUMInput BCARRYHalfAdderHalfAdderHalfAdderHalfAdderHalfAdderHalfAdderHalfAdder0010011+10000011010010CARRY ?
4.3 Full-Adder27SUMInput AHalfAdderHalfAdderInput BCARRYInput C
4.3 Full-Adder28Input ASUMInput BCarryCarryInput
4.3 Full-Adder29A1A2A3A4A5A6A7A8B1B2B3B4B5B6B7B8SUM1SUM2SUM3SUM4SUM5SUM6SUM7SUM8CARRYFullAdderFullAdderFullAdderFullAdderFullAdderFullAdderFullAdderHalfAdder10010011+10010001100100100
4.4 Half-Subtracter30Input ADataHalfSubtracter(HS)Input B1-1001-0010-1110-000BorrowInput ASUMInput BBorrow
4.5 Full-Subtracter31DataInput AHSHSInput BBorrowInput C
4.5 Full-Subtracter32Input ADataInput BBorrowBorrowInput
4.5 Full-Subtracter33A1A2A3A4A5A6A7A8B1B2B3B4B5B6B7B8D1D2	D3D4D5D6D7D8BorrowFSFSFSFSFSFSFSHS10011001-01000001101011000
4.6 Subtraction3410011001-01000001?One’s complementTwo’s complement101111111011111010011001+1011111110101100010011001 = 15301000001 = 65153 - 65 = 8888
4.7 Adder-Subtracter35A1A2A3A4A5A6A7A8B1B2B3B4B5B6B7B8SelFAFAFAFAFAFAFAFAD1D2	D3D4D5D6D7D810011001+1011111100101100010011001-01000001?Plus & Minus Code
36End of Page

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2 Combinational Logic Circuit 01