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Introduction to ARM Architecture

Racharla Rohit Varma, profile picture
Racharla Rohit Varma

This document provides an introduction and overview of ARM processors. It discusses the background and concepts of ARM, including that ARM is a RISC architecture designed for efficiency. It describes key ARM architectural features like the Harvard architecture and conditional execution. The document also covers ARM memory organization, registers, instruction set, programming model, and exceptions.

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Introduction to ARM Processors
2 OUTLINE -Background -ARM Microprocessor •ARM Architecture, •Assembly Language Programming •Instruction Set
3 BACKGROUND • Architectural features of embedded processor • General rules (with exceptions): 1. Designed for efficiency (vs. ease of programming) 2. Huge variety of processors (resulting from 1.) 3. Harvard architecture 4. Heterogeneous register sets 5. Limited instruction-level parallelism or VLIW ISA 6. Different operation modes (saturating arithmetic, fixed point) 7. Specialised microcontroller & DSP instructions (bit-field addressing, multiply/accumulate, bit-reversal, modulo addressing) 8. Multiple memory banks • 9. No “fat”(MMU, caches, memory protection, target buffers, complex pipeline logic, ...) • These features have to be known to the compiler!
4 ARM Concept •What is ARM? –Advanced RISC Machine –Acorn and VLSI Technology built in 1990/11 –RISC –IP Core –T.I. ，PHILIPS，INTEL…… –RISC Microcontroller •ARM7、ARM9、ARM9E-S、StrongARM ARM10….. ARM的產品是 IP Core, 業務是銷 售晶片系統的核心技術IP，全球有 許多大型IT公司採用ARM的技術， 如TI, Intel。 ARM的專利收入主要來 自專利授權金以及按比例 收取產品的專利使用費
5 ARM Concept •Why ARM? –Low power、Low cost、Tiny –8/16/32 bit microprocessor –Thumb mode –Namely •T：Thumb Mode •D：Debug interface (JTAG) •M：Multiplier •I：ICE interface (Trace、Break point)
6 Why ARM here? •ARM is one of the most licensed and thus widespread processor cores in the world •Used especially in portable devices due to low power consumption and reasonable performance (MIPS / watt) •Several interesting extensions available or in development like Thumb instruction set and Jazelle Java machine –http://www.arm.com/armtech/jazelle?OpenDocument
7 ARM processor •ARM is a family of RISC architectures. •“ARM”is the abbreviation of “Advanced RISC Machines”. •ARM does not manufacture its own VLSI devices. –linceses •ARM7- von Neuman Architecture •ARM9 –Harvard Architecture
8 ARM vs. SoC •Architecture of ARM and SoC ARM核心就是個CPU， SoC則是把系統要的功 能全放到CPU內，可以 提供特定用途的單晶片 IC。以個人電腦為例， 將一部電腦除了電源 外，皆轉變到一顆IC 中。 Ex: LAN controller， LCD controller
9
10 Intel Xscale
11 ARM single-cycle instruction 3- stage pipeline operation fetch decode execute time 1 fetch decode execute fetch decode execute 2 3 instruction
12 ARM busses •AMBA: –Open standard. –Many external devices. •Two varieties: –AMBA High- Performance Bus (AHB). –AMBA Peripherals Bus (APB). CPU bridge memory I/O AHB APB
13 ARM instruction set •ARM processor (operating) states •ARM memory organization. •ARM programming model. •ARM assembly language. •ARM data operations. •ARM flow of control. •C to assembly examples •Exceptions •Coprocessor instructions •Summary
14 Processor Operating States •The ARM7TDMI processor has two operating states: –ARM - 32-bit, word-aligned ARM instructions are executed in this state. –Thumb -16-bit, halfword-aligned Thumb instructions are executed in this state.
15 •The operating state of the ARM7TDMI core can be switched between ARM state and Thumb state using the BX (branch and exchange) instructions
16 The Memory System •4 G address space –8-bit bytes, 16-bit half-words, 32-bit words –Support both little-endian and big-endian half-word4 word16 0123 4567 891011 byte0 byte 12131415 16171819 20212223 byte1byte2 half-word14 byte3 byte6 address bit 31 bit 0 half-word12 word8
17 Operating Modes • The ARM7TDMI processor has seven modes of operations: –User mode(usr) - Normal program execution mode –Fast Interrupt mode(fiq) - Supports a high-speed data transfer or channel process. –Interrupt mode(irq) - Used for general-purpose interrupt handling. –Supervisor mode(svc) - Protected mode for the operating system. –Abort mode(abt) - implements virtual memory and/or memory protection –System mode(sys) - A privileged user mode for the operating system. (runs OS tasks) –Undefined mode(und) - supports a software emulation of hardware coprocessors • Except user mode, all are known as privileged mode.
18 ARM programming model r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC) CPSR 31 0 N Z C V CPSR: Current Program Status Register SPSR: Saved Program Status Register
19 Registers •37 registers – 31 general 32 bit registers, including PC – 6 status registers – 15 general registers (R0 to R14), and one status registers and program counter are visible at any time –when you write user-level programs •R13 (SP) •R14 (LR) •R15 (PC) •The visible registers depend on the processor mode •The other registers (the banked registers) are switched in to support IRQ, FIQ, Supervisor, Abort and Undefined mode processing
20 ARM Registers (1) r13_und r14_undr14_irq r13_irq SPSR_und r14_abtr14_svc user mode fiq mode svc mode abort mode irq mode undefined mode usable in user mode system modes only r13_abt r13_svc r8_fiq r9_fiq r10_fiq r11_fiq SPSR_irqSPSR_abt SPSR_svcSPSR_fiqCPSR r14_fiq r13_fiq r12_fiq r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC)
21 Registers •R0 to R15 are directly accessible •R0 to R14 are general purpose •R13: Stack point (sp) (in common) –Individual stack for each processor mode •R14: Linked register (lr) •R15 holds the Program Counter (PC) •CPSR - Current Program Status Register contains condition code flags and the current mode bits •5 SPSRs (Saved Program Status Registers) which are loaded with CPSR when an exceptions occurs
22 The Program Counter (R15) • When the processor is executing in ARM state: –All instructions are 32 bits in length –All instructions must be word aligned –Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to zero (as instruction cannot be halfword or byte aligned). • R14 is used as the subroutine link register (LR) and stores the return address when Branch with Link (BL) operations are performed, calculated from the PC. • Thus to return from a linked branch MOV r15,r14 MOV pc,lr
23 Program Status Registers •The ARM contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. •These register’s functions are: –Hold information about the most recently performed ALU operation. –Control the enabling and disabling of interrupts. –Set the processor operating mode
24 Program Status Registers –The N, Z, C and V are condition code flags •may be changed as a result of arithmetic and logical operations in the processor •may be tested by all instructions to determine if the instruction is to be executed •N : Negative. Z : Zero. C : Carry. V : oVerflow –The I and F bits are the interrupt disable bits –The T bit is thumb bit –The M0, M1, M2, M3 and M4 bits are the mode bits
25 Program Counter (r15) •When the processor is executing in ARM state: –All instructions are 32 bits wide –All instructions must be word aligned –The PC value is stored in bits [31:2] with bits [1:0] undefined –Instructions cannot be halfword or byte aligned
26 ARM Memory Organization half-word4 word16 0123 4567 891011 byte0 byte 12131415 16171819 20212223 byte1byte2 half-word14 byte3 byte6 address bit 31 bit 0 half-word12 word8
27 Big Endian and Little Endian Big endian Little endian
28 Exceptions •Exceptions are usually used to handle unexpected events which arise during the execution of a program 執行系統任務之 計算與處理工作 系統任務 (Task) 初始化處理 處理事件(Event) 或設定旗號(Flag) 中斷服務程式 (ISR) 自中斷服務程式返回 中斷信號處理 與啟動中斷服 務程式 系 統 運 作 中 斷 處 理 回復(繼續) 執行任務 From 黃悅民等嵌入式系統設計-以ARM 處理器為基礎之 SoC平台
29 Exception •System Exception –CPU在執行時，愈到特殊的狀況而產生的例 外，使用者完全無法對例外進行初始化、停 止、或啟動 •Interrupt Exception –ARM CPU預留給系統建置者使用的中斷入口
30 Exception Groups •Direct effect of executing an instruction –SWI –Undefined instructions –Prefetch aborts (memory fault occurring during fetch) •A side-effect of an instruction –Data abort (a memory fault during a load or store data access) •Exceptions generated externally –Reset –IRQ –FIQ
31 Exception Entry •Change to the corresponding mode •Save the address of the instruction following the exception instruction in r14 of the new mode •Save the old value of CPSR in the SPSR of the new mode •Disable IRQ •If the exception is a FIQ, disables further FIQ •Force PC to execute at the relevant vector address
32 Exception Vector Addresses Exception Mode Vector address Reset SVC 0x00000000 Undefinedinstruction UND 0x00000004 Software interrupt (SWI) SVC 0x00000008 Prefetch abort (instruction fetch memory fault) Abort 0x0000000C Data abort (data access memory fault) Abort 0x00000010 IRQ(normal interrupt) IRQ 0x00000018 FIQ(fast interrupt) FIQ 0x0000001C Intel x86 –0x00000 ~ 0x003FF (4 x 256) ARM –0x000000 ~ 0x00001F
33 Exception Return •Any modified user registers must be restored •Restore CPSR •Resume PC in the correct instruction stream
34 Exception Priorities •Reset •Data abort •FIQ •IRQ •Prefetch abort •SWI, undefined instruction Highest priority
35 Naming Rule of ARM •ARM {x} {y} {z} {T} {D} {M} {I} {E} {J} {F} {-S} –x: series –y: memory management / protection unit –z: cache –T: Thumb decoder –D: JTAG debugger –M: fast multiplier –I: support hardware debug –E: enhance instructions (based on TDMI) –J: Jazelle –F: vector floating point unit –S: synthesiable, suitable for EDA tools
Development of the ARM Architecture SA-110 ARM7TDMI 4T 1 Halfword and signed halfword / byte support System mode Thumb instruction set 2 4 ARM9TDMI SA-1110 ARM720T ARM940T Improved ARM/Thumb Interworking CLZ 5TE Saturated maths DSP multiply- accumulate instructions XScale ARM1020E ARM9E-S ARM966E-S 3 Early ARM architectures ARM9EJ-S 5TEJ ARM7EJ-S ARM926EJ-S Jazelle Java bytecode execution 6 ARM1136EJ-S ARM1026EJ-S SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support reference: http://www.intel.com/education/highered/modelcurriculum.htm
37 ARM assembly language •Fairly standard assembly language: LDR r0,[r8] ; a comment label ADD r4,r0,r1
38 ARM data types •32-bit word. •Word can be divided into four 8-bit bytes. •ARM addresses can be 32 bits long. •Address refers to byte. –Address 4 starts at byte 4. •Can be configured at power-up as either little- or bit-endian mode.
39 Instruction Set •The ARM processor is very easy to program at the assembly level •In this part, we will –Look at ARM instruction set and assembly language programming at the user level
40 Notable Features of ARM Instruction Set •The load-store architecture •3-address data processing instructions •Conditional execution of every instruction •The inclusion of every powerful load and store multiple register instructions •Single-cycle execution of all instruction •Open coprocessor instruction set extension
41 Conditional Execution (1) •One of the ARM's most interesting features is that each instruction is conditionally executed •In order to indicate the ARM's conditional mode to the assembler, all you have to do is to append the appropriate condition to a mnemonic CMP r0, #5 BEQ BYPASS ADD r1, r1, r0 SUB r1, r1, r2 BYPASS … CMP r0, #5 ADDNE r1, r1, r0 SUBNE r1, r1, r2 …
42 Conditional Execution (2) •The conditional execution code is faster and smaller ; if ((a==b) && (c==d)) e++; ; ; a is in register r0 ; b is in register r1 ; c is in register r2 ; d is in register r3 ; e is in register r4 CMP r0, r1 CMPEQ r2, r3 ADDEQ r4, r4, #1
43 The ARM Condition Code Field cond 31 28 27 0 •Every instruction is conditionally executed •Each of the 16 values of the condition field causes the instruction to be executed or skipped according to the values of the N, Z, C and V flags in the CPSR N: Negative Z: Zero C: Carry V: oVerflow
44 ARM Condition Codes Opco de [3 1 :2 8 ] Mnemo ni c ex tens i o n Interpretati o n Status fl ag s tate fo r ex ecuti o n 0000 EQ Equal / equals zero Z set 0001 NE Not equal Z clear 0010 CS/HS Carry set / unsigned higher or same C set 0011 CC/LO Carry clear / unsigned lower C clear 0100 MI Minus / negative N set 0101 PL Plus / positive or zero N clear 0110 VS Overflow V set 0111 VC No overflow V clear 1000 HI Unsigned higher C set and Z clear 1001 LS Unsigned lower or same C clear or Z set 1010 GE Signed greater than or equal N equals V 1011 LT Signed less than N is not equal to V 1100 GT Signed greater than Z clear and N equals V 1101 LE Signed less than or equal Z set or N is not equal to V 1110 AL Always any 1111 NV Never (do not use!) none
45 Condition Field •In ARM state, all instructions are conditionally executed according to the CPSR condition codes and the instruction’s condition field •Fifteen different conditions may be used •“Always”condition –Default condition –May be omitted •“Never”condition –The sixteen (1111) is reserved, and must not be used –May use this area for other purposes in the future
46 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
47 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
48 Data processing instructions •Enable the programmer to perform arithmetic and logical operations on data values in registers •The applied rules –All operands are 32 bits wide and come from registers or are specified as literals in the instruction itself –The result, if there is one, is 32 bits wide and is placed in a register (An exception: long multiply instructions produce a 64 bits result) –Each of the operand registers and the result register are independently specified in the instruction (This is, the ARM uses a ‘3-address’format for these instruction)
49 ADD r0, r1, r2 ; r0 := r1 + r2 Simple Register Operands The semicolon here indicates that everything to the right of it is a comment and should be ignored by the assembler The values in the register may be considered to be unsigned integer or signed 2’s-complement values
50 Arithmetic Operations •These instructions perform binary arithmetic on two 32- bit operands •The carry-in, when used, is the current value of the C bit in the CPSR r0 := r2 –r1 + C –1RSC r0, r1, r2 r0 := r2 –r1RSB r0, r1, r2 r0 := r1 –r2 + C –1SBC r0, r1, r2 r0 := r1 –r2SUB r0, r1, r2 r0 := r1 + r2 + CADC r0, r1, r2 r0 := r1 + r2ADD r0, r1, r2
51 Bit-Wise Logical Operations •These instructions perform the specified boolean logic operation on each bit pair of the input operands r0 := r1 AND (NOT r2)BIC r0, r1, r2 r0 := r1 XOR r2EOR r0, r1, r2 r0 := r1 OR r2ORR r0, r1, r2 r0 := r1 AND r2AND r0, r1, r2 r0[i] := r1[i] OPlogic r2[i] for i in [0..31] •BIC stands for ‘bit clear’ •Every ‘1’in the second operand clears the corresponding bit in the first operand
52 Example: BIC Instruction •r1 = 0x11111111 r2 = 0x01100101 BIC r0, r1, r2 •r0 = 0x10011010
53 Register Movement Operations •These instructions ignore the first operand, which is omitted from the assembly language format, and simply move the second operand to the destination r0 := NOT r2MVN r0, r2 r0 := r2MOV r0, r2 The ‘MVN’mnemonic stands for ‘move negated’
54 Comparison Operations •These instructions do not produce a result, but just set the condition code bits (N, Z, C, and V) in the CPSR according to the selected operation test equal bit test compare negated compare set cc on r1 XOR r2TEQ r1, r2 set cc on r1 AND r2TST r1, r2 set cc on r1 + r2CMN r1, r2 set cc on r1 –r2CMP r1, r2
55 Immediate Operands •If we wish to add a constant to a register, we can replace the second source operand with an immediate value ADD r3, r3, #1 ; r3 := r3 + 1 AND r8, r7, #&ff ; r8 := r7[7:0] A constant preceded by ‘#’ A hexadecimal by putting ‘&’after the ‘#’
56 Shifted Register Operands (1) •These instructions allows the second register operand to be subject to a shift operation before it is combined with the first operand •They are still single ARM instructions, executed in a single clock cycle •Most processors offer shift operations as separate instructions, but the ARM combines them with a general ALU operation in a single instruction ADD r3, r2, r1, LSL #3 ; r3 := r2 + 8 * r1
57 Shifted Register Operands (2) A synonym for LSLarithmetic shift leftASL LSL Fill the vacated bits at the LSB of the word with zeros logical shift left by 0 to 31 XXXXX 00000 031 LSL #5
58 Shifted Register Operands (3) LSR Fill the vacated bits at the MSB of the word with zeros logical shift right by 0 to 32 XXXXX 00000 031 LSR #5
59 Shifted Register Operands (4) Fill the vacated bits at the MSB of the word with zero (source operand is positive) arithmetic shift right by 0 to 32ASR 0 00000 0 031 ASR #5 ;positive operand
60 Shifted Register Operands (5) Fill the vacated bits at the MSB of the word with one (source operand is negative) arithmetic shift right by 0 to 32ASR 1 11111 1 031 ASR #5 ;negative operand
61 Shifted Register Operands (6) The bits which fall off the LSB of the word are used to fill the vacated bits at the MSB of the word Rotate right by 0 to 32ROR 031 ROR #5
62 Shifted Register Operands (7) The vacated bit (bit 31) is filled with the old value of the C flag and the operand is shifted one place to the right Rotate right extended by 1 place RRX C 031 RRX C C
63 Shifted Register Operands (8) •It is possible to use a register value to specify the number of bits the second operand should be shifted by •Ex: •Only the bottom 8 bits of r2 are significant ADD r5, r5, r3, LSL r2 ; r5:=r5+r3*2^r2
64 Setting the Condition Codes •Any data processing instruction can set the condition codes ( N, Z, C, and V) if the programmer wishes it to •Ex: 64-bit addition r0r1 r2r3+ r2r3 ADDS r2, r2, r0 ; 32-bit carry out->C ADC r3, r3, r1 ; C is added into ; high word Adding ‘S’to the opcode, standing for ‘Set condition codes’
65 Multiplies (1) •A special form of the data processing instruction supports multiplication •Some important differences –Immediate second operands are not supported –The result register must not be the same as the first source register –If the ‘S’bit is set, the C flag is meaningless MUL r4, r3, r2 ; r4 := (r3 x r2)[31:0]
66 Multiplies (2) •The multiply-accumulate instruction •In some cases, it is usually more efficient to use a short series of data processing instructions •Ex: multiply r0 by 35 MLA r4, r3, r2, r1 ; r4 := (r3 x r2 + r1)[31:0] ADD r0, r0, r0, LSL #2 ; r0’ := 5 x r0 RSB r0, r0, r0, LSL #3 ; r0’’:= 7 x r0’ ; move 35 to r1 MUL r3, r0, r1 ; r3 := r0 x 35 OR
67 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
68 Addressing mode •The ARM data transfer instructions are all based around register-indirect addressing –Based-plus-offset addressing –Based-plus-index addressing LDR r0, [r1] ; r0 := mem32[r1] STR r0, [r1] ; mem32[r1] := r0 Register-indirect addressing
69 Data Transfer Instructions •Move data between ARM registers and memory •Three basic forms of data transfer instruction –Single register load and store instructions –Multiple register load and store instructions –Single register swap instructions
70 Single Register Load / Store Instructions (1) •These instructions provide the most flexible way to transfer single data items between an ARM register and memory •The data item may be a byte, a 32-bit word, 16- bit half-word LDR r0, [r1] ; r0 := mem32[r1] STR r0, [r1] ; mem32[r1] := r0 Register-indirect addressing
71 Single Register Load / Store Instructions (2) Mem8[address] ←RdStore a byte in register into memorySTRB Rd ←signExtend(mem16[address])Load a signed half-word into registerLDRSH Rd ←signExtend(mem8[address])Load a signed byte into registerLDRSB Mem16[address] ←RdStore a half-word in register into memorySTRH Rd ←mem16[address]Load a half-word into registerLDRH Rd ←mem8[address]Load a byte into registerLDRB Mem32[address] ←RdStore a word in register into memorySTR Rd ←mem32[address]Load a word into registerLDR
72 Base-plus-offset Addressing (1) •Pre-indexed addressing mode –It allows one base register to be used to access a number of memory locations which are in the same area of memory LDR r0, [r1, #4] ; r0 := mem32[r1 + 4]
73 Base-plus-offset Addressing (2) •Auto-indexing (Preindex with writeback) –No extra time –The time and code space cost of the extra instruction are avoided LDR r0, [r1, #4]! ; r0 := mem32[r1 + 4] ; r1 := r1 + 4 The exclamation “!”mark indicates that the instruction should update the base register after initiating the data transfer
74 Base-plus-offset Addressing (3) •Post-indexed addressing mode –The exclamation “!”is not needed LDR r0, [r1], #4 ; r0 := mem32[r1] ; r1 := r1 + 4
75 Application ADR r1, table LOOP LDR r0, [r1], #4 ; r0 := mem32[r1] ; r1 := r1 + 4 ;do some operation on r0 … ADR r1, table LOOP LDR r0, [r1] ; r0 := mem32[r1] ADD r1, r1, #4 ; r1 := r1 + 4 ;do some operation on r0 …
76 Multiple Register Load / Store Instructions (1) •Enable large quantities of data to be transferred more efficiently •They are used for procedure entry and exit to save and restore workspace registers •Copy blocks of data around memory LDMIA r1, {r0, r2, r5} ; r0 := mem32[r1] ; r2 := mem32[r1 + 4] ; r5 := mem32[r1 + 8] The base register r1 should be word-aligned
77 Multiple Register Load / Store Instructions (2) Store multiple registersSTM Load multiple registersLDM Rn-4 Rn Rn+4*N Rn+4*N-4 End address Rn!Starting addressDescriptionAddressing mode Rn+4*NRn+4 Increment Before IB Rn-4*NRn-4*Rn+4 Decrement After DA Rn-4*N Rn Decrement Before Increment After DB IA Rn-4*N Rn+4*N Addressing mode for multiple register load and store instructions
78 Example (1) LDMIA r0, {r1, r2, r3} OR LDMIA r0, {r1-r3} r1 := 10 r2 := 20 r3 := 30 r0 := 0x100
79 Example (2) LDMIA r0!, {r1, r2, r3} r1 := 10 r2 := 20 r3 := 30 r0 := 0x10C
80 Example (3) LDMIB r0!, {r1, r2, r3} r1 := 20 r2 := 30 r3 := 40 r0 := 0x10C
81 Example (4) LDMDA r0!, {r1, r2, r3} r1 := 40 r2 := 50 r3 := 60 r0 := 0x108
82 Example (5) LDMDB r0!, {r1, r2, r3} r1 := 30 r2 := 40 r3 := 50 r0 := 0x108
83 Application ; r9 begin address of source data ; r10 begin address of target ; r11 end address of source data LOOP LDMIA r9! , {r0-r7} STMIA r10!, {r0-r7} CMP r9 , r11 BNE LOOP Low address High address r10 r9 r11 Copy Copy a block of memory
84 Application: Stack Operations •ARM use multiple load-store instructions to operate stack –POP: multiple load instructions –PUSH: multiple store instructions
85 The Stack (1) •Stack grows up or grows down –Ascending, ‘A’ –Descending, ‘D’ •Full stack, ‘F’: sp points to the last used address in the stack •Empty stack, ‘E’: sp points to the first unused address in the stack
86 The Stack (2) STMDASTMEDLDMIBLDMED遞減空ED STMIASTMEALDMDBLDMEA遞增空EA STMDBSTMFDLDMIALDMFD遞減滿FD STMIBSTMFALFMFALDMFA遞增滿FA =STMPUSH=LDMPOP說明 Addressing mode The mapping between the stack and block copy views of the multiple load and store instructions
87 Single Register Swap Instructions (1) •Allow a value in a register to be exchanged with a value in memory •Effectively do both a load and a store operation in one instruction •They are little used in user-level programs •Atomic operation •Application –Implement semaphores (multi-threaded / multi-processor environment)
88 Single Register Swap Instructions (2) tmp = mem8[Rn] mem8[Rn] = Rm Rd = tmp Byte exchangeSWPB tmp = mem32[Rn] mem32[Rn] = Rm Rd = tmp WORD exchangeSWP SWP{B} Rd, Rm, [Rn]
89 Example SWP r0, r1, [r2]
90 Load an Address into Register (1) •The ADR (load address into register) instruction to load a register with a 32-bit address •Example –ADR r0,table –Load the contents of register r0 with the 32-bit address "table"
91 Load an Address into Register (2) •ADR is a pseudo instruction •Assembler will transfer pseudo instruction into a sequence of appropriate normal instructions •Assembler will transfer ADR into a single ADD, or SUB instruction to load the address into a register.
92
93 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
94 Control Flow Instructions •Determine which instructions get executed next B LABEL … … LABEL … MOV r0, #0 ; initialize counter LOOP … ADD r0, r0, #1 ; increment loop counter CMP r0, #10 ; compare with limit BNE LOOP ; repeat if not equal … ; else fall through
95 Branch Conditions Branch Interpretati o n No rmal us es B BAL Unconditional Always Always take this branch Always take this branch BEQ Equal Comparison equal or zero result BNE Not equal Comparison not equal or non-zero result BPL Plus Result positive or zero BMI Minus Result minus or negative BCC BLO Carry clear Lower Arithmetic operation did not give carry-out Unsigned comparison gave lower BCS BHS Carry set Higher or same Arithmetic operation gave carry-out Unsigned comparison gave higher or same BVC Overflow clear Signed integer operation; no overflow occurred BVS Overflow set Signed integer operation; overflow occurred BGT Greater than Signed integer comparison gave greater than BGE Greater or equal Signed integer comparison gave greater or equal BLT Less than Signed integer comparison gave less than BLE Less or equal Signed integer comparison gave less than or equal BHI Higher Unsigned comparison gave higher BLS Lower or same Unsigned comparison gave lower or same
96 Branch Instructions PC=label, T=1 PC=Rm & 0xfffffffe, T=Rm & 1 LR = BLX後面的第一道指令的位址 帶返回的跳躍並 切換狀態 BLX PC=Rm & 0xfffffffe, T=Rm & 1跳躍並切換狀態BX PC=label LR=BL後面的第一道指令的位址 帶返回的跳躍BL PC=label跳躍B
97 Branch and Link Instructions (1) •BL instruction save the return address into r14 (lr) BL subroutine ; branch to subroutine CMP r1, #5 ; return to here MOVEQ r1, #0 … subroutine ; subroutine entry point … MOV pc, lr ; return
98 Branch and Link Instructions (2) •Problem –If a subroutine wants to call another subroutine, the original return address, r14, will be overwritten by the second BL instruction •Solution –Push r14 into a stack –The subroutine will often also require some work registers, the old values in these registers can be saved at the same time using a store multiple instruction
99 Branch and Link Instructions (3) BL SUB1 ; branch to subroutine SUB1 … SUB1 STMFD r13!, {r0-r2,r14} ; save work & link register BL SUB2 … LDMFD r13!, {r0-r2, pc} ; restore work register and ; return SUB2 … MOV pc, r14 ; copy r14 into r15 to return
100 Jump Tables (1) •A programmer sometimes wants to call one of a set of subroutines, the choice depending on a value computed by the program BL JUMPTAB .. JUMPTAB CMP r0, #0 BEQ SUB0 CMP r0, #1 BEQ SUB1 CMP r0, #2 BEQ SUB2 .. Note: slow when the list is long, and all subroutines are equally frequent
101 Jump Tables (2) •“DCD”directive instructs the assembler to reserve a word of store and to initialize it to the value of the expression to the right BL JUMPTAB .. JUMPTAB ADR r1, SUBTAB CMP r0, #SUBMAX LDRLS pc, [r1, r0, LSL #2] B ERROR SUBTAB DCD SUB0 DCD SUB1 DCD SUB2 ..
102 Supervisor Calls •SWI: SoftWare Interrupt •The supervisor calls are implemented in system software –They are probably different from one ARM system to another –Most ARM systems implement a common subset of calls in addition to any specific calls required by the particular application ; This routine sends the character in the bottom ; byte of r0 to the use display device SWI SWI_WriteC ; output r0[7:0]
103 Processor Actions for SWI (1) •Save the address of the instruction after the SWI in r14_svc •Save the CPSR in SPSR_svc •Enter supervisor mode •Disable IRQs •Set the PC to 0x8
104 Processor Actions for SWI (2) ... ADD r0, r1, r2 SWI 0x6 ADD r1, r2, r2 ... Reset Undef instr. SWI Prefetch abort Data abort Reserved IRQ FIQ 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c SWI handler ... User Program Vector Table SWI handler
105 Processor Actions for SWI (3) ... ADD r0, r1, r2 SWI 0x6 ADD r1, r2, r2 ... Reset Undef instr. SWI Prefetch abort Data abort Reserved IRQ FIQ 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c switch (rn) { case 0x1: … case 0x6: ... } User Program Vector Table SWI handler
106 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
107 Writing Simple Assembly Language Programs (ARM ADS) AREA HelloW, CODE, READONLY SWI_WriteC EQU &0 SWI_Exit EQU &11 ENTRY START ADR r1, TEXT LOOP LDRB r0, [r1], #1 CMP r0, #0 SWINE SWI_WriteC BNE LOOP SWI SWI_Exit TEXT = "Hello World",&0a,&0d,0 END AREA: chunks of data or code that are manipulated by the linker ENTRY: The first instruction to be executed within an application is marked by the ENTRY directive. An application can contain only a single entry point. EQU: give a symbolic name to a numeric constant (*) DCB: allocate one or more bytes of memory and define initial runtime content of memory (=)
108 General Assembly Form (ARM ADS) •The three sections are separated by at least one whitespace character (a space or a tab) • Actual instructions never start in the first column, since they must be preceded by whitespace, even if there is no label •All three sections are optional label <whitespace> instruction <whitespace> ;comment
109 GNU GAS Basic Format (1) .section .text .global main .type main,%function main: MOV r0, #100 ADD r0, r0, r0 .end •Assemble the following code into a section •Similar to “AREA”in armasm Filename: test.s
110 GNU GAS Basic Format (2) .section .text .global main .type main,%function main: MOV r0, #100 ADD r0, r0, r0 .end •“.global”makes the symbol visible to ld •Similar to “EXPORT”in armasm Filename: test.s
111 GNU ARM Basic Format (3) .section .text .global main .type main,%function main: MOV r0, #100 ADD r0, r0, r0 .end •This sets the type of symbol name to be either a function symbol or an object symbol •“.end”marks the end of the assembly file •Assembler does not process anything in the file past the “.end”directive Filename: test.s
112 GNU ARM Basic Format (4) .section .text .global main .type main,%function main: MOV r0, #100 ADD r0, r0, r0 .end •LABEL透過”:”來做識別 •armasm則是透過指令和保留 字的縮排來做識別 Filename: test.s •Comments •/* …your comments... */ •@ your comments (line comment)
113 Thumb Instruction Set •Thumb addresses code density –A compressed form of a subset of the ARM instruction set •Thumb maps onto ARMs –Dynamic decompression in an ARM instruction pipeline –Instructions execute as standard ARM instructions within the processor •Thumb is not a complete architecture •Thumb is fully supported by ARM development tools •Design for processor / compiler, not for programmer
114 Thumb-ARM Differences (1) •All Thumb instructions are 16-bits long –ARM instructions are 32-bits long •Most Thumb instructions are executed unconditionally –All ARM instructions are executed conditionally
115 Thumb-ARM Differences (2) •Many Thumb data processing instructions use a 2-address format (the destination register is the same as one of the source registers) –ARM use 3-address format •Thumb instruction are less regular than ARM instruction formats, as a result of the dense encoding
116 Thumb Applications •Thumb properties –Thumb requires 70% space of the ARM code –Thumb uses 40% more instructions than the ARM code –With 32-bit memory, the ARM code is 40% faster than the Thumb code –With 16-bit memory, the Thumb code is 45% faster than the ARM code –Thumb uses 30% less external memory power than ARM code
117 DSP Extensions •DSP Extensions “E” –16bit Multiply and Multiply-Accumulate instructions –Saturated, signed arithmetic –Introduced in v5TE –Available in ARM9E, ARM10E and Jaguar families
118 ARM Java Extensions - JazelleTM •Direct execution of Java ByteCode •8x Performance of Software JVM (Embedded CaffeineMark3.0) •Over 80% power reduction for Java Applications •Single Processor for Java and existing OS/applications •Supported by leading Java Run-time environments and operating systems •Available in ARM9, ARM10 & Jaguar families
119 ARM Media Extensions (ARM v6) •Applications –Audio processing –MPEG4 encode/decode –Speech Recognition –Handwriting Recognition –Viterbi Processing –FFT Processing •Includes –8 & 16-bit SIMD operations –ADD, SUB, MAC, Select •Up to 4x performance for no extra power •Introduced in ARM v6 architecture, Available in Jaguar
120 ARM Architectures THUMBTM DSP JazelleTM Media •Enhance performance through innovation – THUMBTM: 30% code compression – DSP Extensions: Higher performance for fixed-point DSP – JazelleTM: up to 8x performance for java – Media Extensions up to 4x performance for audio & video •Preserve Software Investment through compatibility Architecture v4T v5TE v5TEJ v6 Feature Set
121 Outline •Introduction •Programmers model •Instruction set •System design •Development tools
122 Example ARM-based System
AMBA Bridge Timer On-chip RAM ARM Interrupt Controller Remap/ Pause TIC Arbiter Bus InterfaceExternal ROM External RAM Reset System Bus Peripheral Bus • AMBA – Advanced Microcontroller Bus Architecture • ADK – Complete AMBA Design Kit • ACT – AMBA Compliance Testbench • PrimeCell – ARM’s AMBA compliant peripherals AHB or ASB APB External Bus Interface Decoder reference: http://www.intel.com/education/highered/modelcurriculum.htm
124 ARM Coprocessor Interface •ARM supports a general-purpose extension of its instructions set through the addition of hardware coprocessor •Coprocessor architecture –Up to 16 logical coprocessors –Each coprocessor can have up to 16 private registers (any reasonable size) –Using load-store architecture and some instructions to communicate with ARM registers and memory.
125 ARM7TDMI Coprocessor Interface •Based on “bus watching”technique •The coprocessor is attached to a bus where the ARM instruction stream flows into the ARM •The coprocessor copies the instructions into an internal pipeline •A “hand-shake”between the ARM and the coprocessor confirms that they are both ready to execute coprocessor instructions
126 Outline •Introduction •Programmers model •Instruction set •System design •Development tools
127 Development Tools (1) •Commercial –ARM –IAR –… •Open source –GNU Best code quality
128 Development Tools (2) binutilsfromelf Format converter Simulator in GDBARMulatorSimulator GDB, InsightArmsd, AXDDebugger newlibC libraryC library binutilsarmlinkLinker binutilsarmasmAssembler gccarmccCompiler GNUARM ADS
129 The Structure of ARM Cross- Development Toolkit assemblerC compiler C source asm source .aof C libraries linker .axf ARMsd debug ARMulator development system model board object libraries
130 ADS-Assembler •Compiler：產生Object •Linker：產生ELF 可執行碼
131 ADS- Pre-assembler •Pre-assembler –Pseudo code -> assembler -> Object
132 Example •Example of pr-compiler
133 Example •Example of pr-compiler

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Introduction to ARM Architecture

  • 3. 3 BACKGROUND • Architectural features of embedded processor • General rules (with exceptions): 1. Designed for efficiency (vs. ease of programming) 2. Huge variety of processors (resulting from 1.) 3. Harvard architecture 4. Heterogeneous register sets 5. Limited instruction-level parallelism or VLIW ISA 6. Different operation modes (saturating arithmetic, fixed point) 7. Specialised microcontroller & DSP instructions (bit-field addressing, multiply/accumulate, bit-reversal, modulo addressing) 8. Multiple memory banks • 9. No “fat”(MMU, caches, memory protection, target buffers, complex pipeline logic, ...) • These features have to be known to the compiler!
  • 4. 4 ARM Concept •What is ARM? –Advanced RISC Machine –Acorn and VLSI Technology built in 1990/11 –RISC –IP Core –T.I. ，PHILIPS，INTEL…… –RISC Microcontroller •ARM7、ARM9、ARM9E-S、StrongARM ARM10….. ARM的產品是 IP Core, 業務是銷 售晶片系統的核心技術IP，全球有 許多大型IT公司採用ARM的技術， 如TI, Intel。 ARM的專利收入主要來 自專利授權金以及按比例 收取產品的專利使用費
  • 5. 5 ARM Concept •Why ARM? –Low power、Low cost、Tiny –8/16/32 bit microprocessor –Thumb mode –Namely •T：Thumb Mode •D：Debug interface (JTAG) •M：Multiplier •I：ICE interface (Trace、Break point)
  • 6. 6 Why ARM here? •ARM is one of the most licensed and thus widespread processor cores in the world •Used especially in portable devices due to low power consumption and reasonable performance (MIPS / watt) •Several interesting extensions available or in development like Thumb instruction set and Jazelle Java machine –http://www.arm.com/armtech/jazelle?OpenDocument
  • 7. 7 ARM processor •ARM is a family of RISC architectures. •“ARM”is the abbreviation of “Advanced RISC Machines”. •ARM does not manufacture its own VLSI devices. –linceses •ARM7- von Neuman Architecture •ARM9 –Harvard Architecture
  • 8. 8 ARM vs. SoC •Architecture of ARM and SoC ARM核心就是個CPU， SoC則是把系統要的功 能全放到CPU內，可以 提供特定用途的單晶片 IC。以個人電腦為例， 將一部電腦除了電源 外，皆轉變到一顆IC 中。 Ex: LAN controller， LCD controller
  • 9. 9
  • 11. 11 ARM single-cycle instruction 3- stage pipeline operation fetch decode execute time 1 fetch decode execute fetch decode execute 2 3 instruction
  • 12. 12 ARM busses •AMBA: –Open standard. –Many external devices. •Two varieties: –AMBA High- Performance Bus (AHB). –AMBA Peripherals Bus (APB). CPU bridge memory I/O AHB APB
  • 13. 13 ARM instruction set •ARM processor (operating) states •ARM memory organization. •ARM programming model. •ARM assembly language. •ARM data operations. •ARM flow of control. •C to assembly examples •Exceptions •Coprocessor instructions •Summary
  • 14. 14 Processor Operating States •The ARM7TDMI processor has two operating states: –ARM - 32-bit, word-aligned ARM instructions are executed in this state. –Thumb -16-bit, halfword-aligned Thumb instructions are executed in this state.
  • 15. 15 •The operating state of the ARM7TDMI core can be switched between ARM state and Thumb state using the BX (branch and exchange) instructions
  • 16. 16 The Memory System •4 G address space –8-bit bytes, 16-bit half-words, 32-bit words –Support both little-endian and big-endian half-word4 word16 0123 4567 891011 byte0 byte 12131415 16171819 20212223 byte1byte2 half-word14 byte3 byte6 address bit 31 bit 0 half-word12 word8
  • 17. 17 Operating Modes • The ARM7TDMI processor has seven modes of operations: –User mode(usr) - Normal program execution mode –Fast Interrupt mode(fiq) - Supports a high-speed data transfer or channel process. –Interrupt mode(irq) - Used for general-purpose interrupt handling. –Supervisor mode(svc) - Protected mode for the operating system. –Abort mode(abt) - implements virtual memory and/or memory protection –System mode(sys) - A privileged user mode for the operating system. (runs OS tasks) –Undefined mode(und) - supports a software emulation of hardware coprocessors • Except user mode, all are known as privileged mode.
  • 18. 18 ARM programming model r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC) CPSR 31 0 N Z C V CPSR: Current Program Status Register SPSR: Saved Program Status Register
  • 19. 19 Registers •37 registers – 31 general 32 bit registers, including PC – 6 status registers – 15 general registers (R0 to R14), and one status registers and program counter are visible at any time –when you write user-level programs •R13 (SP) •R14 (LR) •R15 (PC) •The visible registers depend on the processor mode •The other registers (the banked registers) are switched in to support IRQ, FIQ, Supervisor, Abort and Undefined mode processing
  • 20. 20 ARM Registers (1) r13_und r14_undr14_irq r13_irq SPSR_und r14_abtr14_svc user mode fiq mode svc mode abort mode irq mode undefined mode usable in user mode system modes only r13_abt r13_svc r8_fiq r9_fiq r10_fiq r11_fiq SPSR_irqSPSR_abt SPSR_svcSPSR_fiqCPSR r14_fiq r13_fiq r12_fiq r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC)
  • 21. 21 Registers •R0 to R15 are directly accessible •R0 to R14 are general purpose •R13: Stack point (sp) (in common) –Individual stack for each processor mode •R14: Linked register (lr) •R15 holds the Program Counter (PC) •CPSR - Current Program Status Register contains condition code flags and the current mode bits •5 SPSRs (Saved Program Status Registers) which are loaded with CPSR when an exceptions occurs
  • 22. 22 The Program Counter (R15) • When the processor is executing in ARM state: –All instructions are 32 bits in length –All instructions must be word aligned –Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to zero (as instruction cannot be halfword or byte aligned). • R14 is used as the subroutine link register (LR) and stores the return address when Branch with Link (BL) operations are performed, calculated from the PC. • Thus to return from a linked branch MOV r15,r14 MOV pc,lr
  • 23. 23 Program Status Registers •The ARM contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers (SPSRs) for use by exception handlers. •These register’s functions are: –Hold information about the most recently performed ALU operation. –Control the enabling and disabling of interrupts. –Set the processor operating mode
  • 24. 24 Program Status Registers –The N, Z, C and V are condition code flags •may be changed as a result of arithmetic and logical operations in the processor •may be tested by all instructions to determine if the instruction is to be executed •N : Negative. Z : Zero. C : Carry. V : oVerflow –The I and F bits are the interrupt disable bits –The T bit is thumb bit –The M0, M1, M2, M3 and M4 bits are the mode bits
  • 25. 25 Program Counter (r15) •When the processor is executing in ARM state: –All instructions are 32 bits wide –All instructions must be word aligned –The PC value is stored in bits [31:2] with bits [1:0] undefined –Instructions cannot be halfword or byte aligned
  • 27. 27 Big Endian and Little Endian Big endian Little endian
  • 28. 28 Exceptions •Exceptions are usually used to handle unexpected events which arise during the execution of a program 執行系統任務之 計算與處理工作 系統任務 (Task) 初始化處理 處理事件(Event) 或設定旗號(Flag) 中斷服務程式 (ISR) 自中斷服務程式返回 中斷信號處理 與啟動中斷服 務程式 系 統 運 作 中 斷 處 理 回復(繼續) 執行任務 From 黃悅民等嵌入式系統設計-以ARM 處理器為基礎之 SoC平台
  • 30. 30 Exception Groups •Direct effect of executing an instruction –SWI –Undefined instructions –Prefetch aborts (memory fault occurring during fetch) •A side-effect of an instruction –Data abort (a memory fault during a load or store data access) •Exceptions generated externally –Reset –IRQ –FIQ
  • 31. 31 Exception Entry •Change to the corresponding mode •Save the address of the instruction following the exception instruction in r14 of the new mode •Save the old value of CPSR in the SPSR of the new mode •Disable IRQ •If the exception is a FIQ, disables further FIQ •Force PC to execute at the relevant vector address
  • 32. 32 Exception Vector Addresses Exception Mode Vector address Reset SVC 0x00000000 Undefinedinstruction UND 0x00000004 Software interrupt (SWI) SVC 0x00000008 Prefetch abort (instruction fetch memory fault) Abort 0x0000000C Data abort (data access memory fault) Abort 0x00000010 IRQ(normal interrupt) IRQ 0x00000018 FIQ(fast interrupt) FIQ 0x0000001C Intel x86 –0x00000 ~ 0x003FF (4 x 256) ARM –0x000000 ~ 0x00001F
  • 33. 33 Exception Return •Any modified user registers must be restored •Restore CPSR •Resume PC in the correct instruction stream
  • 34. 34 Exception Priorities •Reset •Data abort •FIQ •IRQ •Prefetch abort •SWI, undefined instruction Highest priority
  • 35. 35 Naming Rule of ARM •ARM {x} {y} {z} {T} {D} {M} {I} {E} {J} {F} {-S} –x: series –y: memory management / protection unit –z: cache –T: Thumb decoder –D: JTAG debugger –M: fast multiplier –I: support hardware debug –E: enhance instructions (based on TDMI) –J: Jazelle –F: vector floating point unit –S: synthesiable, suitable for EDA tools
  • 36. Development of the ARM Architecture SA-110 ARM7TDMI 4T 1 Halfword and signed halfword / byte support System mode Thumb instruction set 2 4 ARM9TDMI SA-1110 ARM720T ARM940T Improved ARM/Thumb Interworking CLZ 5TE Saturated maths DSP multiply- accumulate instructions XScale ARM1020E ARM9E-S ARM966E-S 3 Early ARM architectures ARM9EJ-S 5TEJ ARM7EJ-S ARM926EJ-S Jazelle Java bytecode execution 6 ARM1136EJ-S ARM1026EJ-S SIMD Instructions Multi-processing V6 Memory architecture (VMSA) Unaligned data support reference: http://www.intel.com/education/highered/modelcurriculum.htm
  • 37. 37 ARM assembly language •Fairly standard assembly language: LDR r0,[r8] ; a comment label ADD r4,r0,r1
  • 38. 38 ARM data types •32-bit word. •Word can be divided into four 8-bit bytes. •ARM addresses can be 32 bits long. •Address refers to byte. –Address 4 starts at byte 4. •Can be configured at power-up as either little- or bit-endian mode.
  • 39. 39 Instruction Set •The ARM processor is very easy to program at the assembly level •In this part, we will –Look at ARM instruction set and assembly language programming at the user level
  • 40. 40 Notable Features of ARM Instruction Set •The load-store architecture •3-address data processing instructions •Conditional execution of every instruction •The inclusion of every powerful load and store multiple register instructions •Single-cycle execution of all instruction •Open coprocessor instruction set extension
  • 41. 41 Conditional Execution (1) •One of the ARM's most interesting features is that each instruction is conditionally executed •In order to indicate the ARM's conditional mode to the assembler, all you have to do is to append the appropriate condition to a mnemonic CMP r0, #5 BEQ BYPASS ADD r1, r1, r0 SUB r1, r1, r2 BYPASS … CMP r0, #5 ADDNE r1, r1, r0 SUBNE r1, r1, r2 …
  • 42. 42 Conditional Execution (2) •The conditional execution code is faster and smaller ; if ((a==b) && (c==d)) e++; ; ; a is in register r0 ; b is in register r1 ; c is in register r2 ; d is in register r3 ; e is in register r4 CMP r0, r1 CMPEQ r2, r3 ADDEQ r4, r4, #1
  • 43. 43 The ARM Condition Code Field cond 31 28 27 0 •Every instruction is conditionally executed •Each of the 16 values of the condition field causes the instruction to be executed or skipped according to the values of the N, Z, C and V flags in the CPSR N: Negative Z: Zero C: Carry V: oVerflow
  • 44. 44 ARM Condition Codes Opco de [3 1 :2 8 ] Mnemo ni c ex tens i o n Interpretati o n Status fl ag s tate fo r ex ecuti o n 0000 EQ Equal / equals zero Z set 0001 NE Not equal Z clear 0010 CS/HS Carry set / unsigned higher or same C set 0011 CC/LO Carry clear / unsigned lower C clear 0100 MI Minus / negative N set 0101 PL Plus / positive or zero N clear 0110 VS Overflow V set 0111 VC No overflow V clear 1000 HI Unsigned higher C set and Z clear 1001 LS Unsigned lower or same C clear or Z set 1010 GE Signed greater than or equal N equals V 1011 LT Signed less than N is not equal to V 1100 GT Signed greater than Z clear and N equals V 1101 LE Signed less than or equal Z set or N is not equal to V 1110 AL Always any 1111 NV Never (do not use!) none
  • 45. 45 Condition Field •In ARM state, all instructions are conditionally executed according to the CPSR condition codes and the instruction’s condition field •Fifteen different conditions may be used •“Always”condition –Default condition –May be omitted •“Never”condition –The sixteen (1111) is reserved, and must not be used –May use this area for other purposes in the future
  • 46. 46 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
  • 47. 47 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
  • 48. 48 Data processing instructions •Enable the programmer to perform arithmetic and logical operations on data values in registers •The applied rules –All operands are 32 bits wide and come from registers or are specified as literals in the instruction itself –The result, if there is one, is 32 bits wide and is placed in a register (An exception: long multiply instructions produce a 64 bits result) –Each of the operand registers and the result register are independently specified in the instruction (This is, the ARM uses a ‘3-address’format for these instruction)
  • 49. 49 ADD r0, r1, r2 ; r0 := r1 + r2 Simple Register Operands The semicolon here indicates that everything to the right of it is a comment and should be ignored by the assembler The values in the register may be considered to be unsigned integer or signed 2’s-complement values
  • 50. 50 Arithmetic Operations •These instructions perform binary arithmetic on two 32- bit operands •The carry-in, when used, is the current value of the C bit in the CPSR r0 := r2 –r1 + C –1RSC r0, r1, r2 r0 := r2 –r1RSB r0, r1, r2 r0 := r1 –r2 + C –1SBC r0, r1, r2 r0 := r1 –r2SUB r0, r1, r2 r0 := r1 + r2 + CADC r0, r1, r2 r0 := r1 + r2ADD r0, r1, r2
  • 51. 51 Bit-Wise Logical Operations •These instructions perform the specified boolean logic operation on each bit pair of the input operands r0 := r1 AND (NOT r2)BIC r0, r1, r2 r0 := r1 XOR r2EOR r0, r1, r2 r0 := r1 OR r2ORR r0, r1, r2 r0 := r1 AND r2AND r0, r1, r2 r0[i] := r1[i] OPlogic r2[i] for i in [0..31] •BIC stands for ‘bit clear’ •Every ‘1’in the second operand clears the corresponding bit in the first operand
  • 52. 52 Example: BIC Instruction •r1 = 0x11111111 r2 = 0x01100101 BIC r0, r1, r2 •r0 = 0x10011010
  • 53. 53 Register Movement Operations •These instructions ignore the first operand, which is omitted from the assembly language format, and simply move the second operand to the destination r0 := NOT r2MVN r0, r2 r0 := r2MOV r0, r2 The ‘MVN’mnemonic stands for ‘move negated’
  • 54. 54 Comparison Operations •These instructions do not produce a result, but just set the condition code bits (N, Z, C, and V) in the CPSR according to the selected operation test equal bit test compare negated compare set cc on r1 XOR r2TEQ r1, r2 set cc on r1 AND r2TST r1, r2 set cc on r1 + r2CMN r1, r2 set cc on r1 –r2CMP r1, r2
  • 55. 55 Immediate Operands •If we wish to add a constant to a register, we can replace the second source operand with an immediate value ADD r3, r3, #1 ; r3 := r3 + 1 AND r8, r7, #&ff ; r8 := r7[7:0] A constant preceded by ‘#’ A hexadecimal by putting ‘&’after the ‘#’
  • 56. 56 Shifted Register Operands (1) •These instructions allows the second register operand to be subject to a shift operation before it is combined with the first operand •They are still single ARM instructions, executed in a single clock cycle •Most processors offer shift operations as separate instructions, but the ARM combines them with a general ALU operation in a single instruction ADD r3, r2, r1, LSL #3 ; r3 := r2 + 8 * r1
  • 57. 57 Shifted Register Operands (2) A synonym for LSLarithmetic shift leftASL LSL Fill the vacated bits at the LSB of the word with zeros logical shift left by 0 to 31 XXXXX 00000 031 LSL #5
  • 58. 58 Shifted Register Operands (3) LSR Fill the vacated bits at the MSB of the word with zeros logical shift right by 0 to 32 XXXXX 00000 031 LSR #5
  • 59. 59 Shifted Register Operands (4) Fill the vacated bits at the MSB of the word with zero (source operand is positive) arithmetic shift right by 0 to 32ASR 0 00000 0 031 ASR #5 ;positive operand
  • 60. 60 Shifted Register Operands (5) Fill the vacated bits at the MSB of the word with one (source operand is negative) arithmetic shift right by 0 to 32ASR 1 11111 1 031 ASR #5 ;negative operand
  • 61. 61 Shifted Register Operands (6) The bits which fall off the LSB of the word are used to fill the vacated bits at the MSB of the word Rotate right by 0 to 32ROR 031 ROR #5
  • 62. 62 Shifted Register Operands (7) The vacated bit (bit 31) is filled with the old value of the C flag and the operand is shifted one place to the right Rotate right extended by 1 place RRX C 031 RRX C C
  • 63. 63 Shifted Register Operands (8) •It is possible to use a register value to specify the number of bits the second operand should be shifted by •Ex: •Only the bottom 8 bits of r2 are significant ADD r5, r5, r3, LSL r2 ; r5:=r5+r3*2^r2
  • 64. 64 Setting the Condition Codes •Any data processing instruction can set the condition codes ( N, Z, C, and V) if the programmer wishes it to •Ex: 64-bit addition r0r1 r2r3+ r2r3 ADDS r2, r2, r0 ; 32-bit carry out->C ADC r3, r3, r1 ; C is added into ; high word Adding ‘S’to the opcode, standing for ‘Set condition codes’
  • 65. 65 Multiplies (1) •A special form of the data processing instruction supports multiplication •Some important differences –Immediate second operands are not supported –The result register must not be the same as the first source register –If the ‘S’bit is set, the C flag is meaningless MUL r4, r3, r2 ; r4 := (r3 x r2)[31:0]
  • 66. 66 Multiplies (2) •The multiply-accumulate instruction •In some cases, it is usually more efficient to use a short series of data processing instructions •Ex: multiply r0 by 35 MLA r4, r3, r2, r1 ; r4 := (r3 x r2 + r1)[31:0] ADD r0, r0, r0, LSL #2 ; r0’ := 5 x r0 RSB r0, r0, r0, LSL #3 ; r0’’:= 7 x r0’ ; move 35 to r1 MUL r3, r0, r1 ; r3 := r0 x 35 OR
  • 67. 67 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
  • 68. 68 Addressing mode •The ARM data transfer instructions are all based around register-indirect addressing –Based-plus-offset addressing –Based-plus-index addressing LDR r0, [r1] ; r0 := mem32[r1] STR r0, [r1] ; mem32[r1] := r0 Register-indirect addressing
  • 69. 69 Data Transfer Instructions •Move data between ARM registers and memory •Three basic forms of data transfer instruction –Single register load and store instructions –Multiple register load and store instructions –Single register swap instructions
  • 70. 70 Single Register Load / Store Instructions (1) •These instructions provide the most flexible way to transfer single data items between an ARM register and memory •The data item may be a byte, a 32-bit word, 16- bit half-word LDR r0, [r1] ; r0 := mem32[r1] STR r0, [r1] ; mem32[r1] := r0 Register-indirect addressing
  • 71. 71 Single Register Load / Store Instructions (2) Mem8[address] ←RdStore a byte in register into memorySTRB Rd ←signExtend(mem16[address])Load a signed half-word into registerLDRSH Rd ←signExtend(mem8[address])Load a signed byte into registerLDRSB Mem16[address] ←RdStore a half-word in register into memorySTRH Rd ←mem16[address]Load a half-word into registerLDRH Rd ←mem8[address]Load a byte into registerLDRB Mem32[address] ←RdStore a word in register into memorySTR Rd ←mem32[address]Load a word into registerLDR
  • 72. 72 Base-plus-offset Addressing (1) •Pre-indexed addressing mode –It allows one base register to be used to access a number of memory locations which are in the same area of memory LDR r0, [r1, #4] ; r0 := mem32[r1 + 4]
  • 73. 73 Base-plus-offset Addressing (2) •Auto-indexing (Preindex with writeback) –No extra time –The time and code space cost of the extra instruction are avoided LDR r0, [r1, #4]! ; r0 := mem32[r1 + 4] ; r1 := r1 + 4 The exclamation “!”mark indicates that the instruction should update the base register after initiating the data transfer
  • 74. 74 Base-plus-offset Addressing (3) •Post-indexed addressing mode –The exclamation “!”is not needed LDR r0, [r1], #4 ; r0 := mem32[r1] ; r1 := r1 + 4
  • 75. 75 Application ADR r1, table LOOP LDR r0, [r1], #4 ; r0 := mem32[r1] ; r1 := r1 + 4 ;do some operation on r0 … ADR r1, table LOOP LDR r0, [r1] ; r0 := mem32[r1] ADD r1, r1, #4 ; r1 := r1 + 4 ;do some operation on r0 …
  • 76. 76 Multiple Register Load / Store Instructions (1) •Enable large quantities of data to be transferred more efficiently •They are used for procedure entry and exit to save and restore workspace registers •Copy blocks of data around memory LDMIA r1, {r0, r2, r5} ; r0 := mem32[r1] ; r2 := mem32[r1 + 4] ; r5 := mem32[r1 + 8] The base register r1 should be word-aligned
  • 77. 77 Multiple Register Load / Store Instructions (2) Store multiple registersSTM Load multiple registersLDM Rn-4 Rn Rn+4*N Rn+4*N-4 End address Rn!Starting addressDescriptionAddressing mode Rn+4*NRn+4 Increment Before IB Rn-4*NRn-4*Rn+4 Decrement After DA Rn-4*N Rn Decrement Before Increment After DB IA Rn-4*N Rn+4*N Addressing mode for multiple register load and store instructions
  • 78. 78 Example (1) LDMIA r0, {r1, r2, r3} OR LDMIA r0, {r1-r3} r1 := 10 r2 := 20 r3 := 30 r0 := 0x100
  • 79. 79 Example (2) LDMIA r0!, {r1, r2, r3} r1 := 10 r2 := 20 r3 := 30 r0 := 0x10C
  • 80. 80 Example (3) LDMIB r0!, {r1, r2, r3} r1 := 20 r2 := 30 r3 := 40 r0 := 0x10C
  • 81. 81 Example (4) LDMDA r0!, {r1, r2, r3} r1 := 40 r2 := 50 r3 := 60 r0 := 0x108
  • 82. 82 Example (5) LDMDB r0!, {r1, r2, r3} r1 := 30 r2 := 40 r3 := 50 r0 := 0x108
  • 83. 83 Application ; r9 begin address of source data ; r10 begin address of target ; r11 end address of source data LOOP LDMIA r9! , {r0-r7} STMIA r10!, {r0-r7} CMP r9 , r11 BNE LOOP Low address High address r10 r9 r11 Copy Copy a block of memory
  • 84. 84 Application: Stack Operations •ARM use multiple load-store instructions to operate stack –POP: multiple load instructions –PUSH: multiple store instructions
  • 85. 85 The Stack (1) •Stack grows up or grows down –Ascending, ‘A’ –Descending, ‘D’ •Full stack, ‘F’: sp points to the last used address in the stack •Empty stack, ‘E’: sp points to the first unused address in the stack
  • 87. 87 Single Register Swap Instructions (1) •Allow a value in a register to be exchanged with a value in memory •Effectively do both a load and a store operation in one instruction •They are little used in user-level programs •Atomic operation •Application –Implement semaphores (multi-threaded / multi-processor environment)
  • 88. 88 Single Register Swap Instructions (2) tmp = mem8[Rn] mem8[Rn] = Rm Rd = tmp Byte exchangeSWPB tmp = mem32[Rn] mem32[Rn] = Rm Rd = tmp WORD exchangeSWP SWP{B} Rd, Rm, [Rn]
  • 90. 90 Load an Address into Register (1) •The ADR (load address into register) instruction to load a register with a 32-bit address •Example –ADR r0,table –Load the contents of register r0 with the 32-bit address "table"
  • 91. 91 Load an Address into Register (2) •ADR is a pseudo instruction •Assembler will transfer pseudo instruction into a sequence of appropriate normal instructions •Assembler will transfer ADR into a single ADD, or SUB instruction to load the address into a register.
  • 92. 92
  • 93. 93 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
  • 94. 94 Control Flow Instructions •Determine which instructions get executed next B LABEL … … LABEL … MOV r0, #0 ; initialize counter LOOP … ADD r0, r0, #1 ; increment loop counter CMP r0, #10 ; compare with limit BNE LOOP ; repeat if not equal … ; else fall through
  • 95. 95 Branch Conditions Branch Interpretati o n No rmal us es B BAL Unconditional Always Always take this branch Always take this branch BEQ Equal Comparison equal or zero result BNE Not equal Comparison not equal or non-zero result BPL Plus Result positive or zero BMI Minus Result minus or negative BCC BLO Carry clear Lower Arithmetic operation did not give carry-out Unsigned comparison gave lower BCS BHS Carry set Higher or same Arithmetic operation gave carry-out Unsigned comparison gave higher or same BVC Overflow clear Signed integer operation; no overflow occurred BVS Overflow set Signed integer operation; overflow occurred BGT Greater than Signed integer comparison gave greater than BGE Greater or equal Signed integer comparison gave greater or equal BLT Less than Signed integer comparison gave less than BLE Less or equal Signed integer comparison gave less than or equal BHI Higher Unsigned comparison gave higher BLS Lower or same Unsigned comparison gave lower or same
  • 96. 96 Branch Instructions PC=label, T=1 PC=Rm & 0xfffffffe, T=Rm & 1 LR = BLX後面的第一道指令的位址 帶返回的跳躍並 切換狀態 BLX PC=Rm & 0xfffffffe, T=Rm & 1跳躍並切換狀態BX PC=label LR=BL後面的第一道指令的位址 帶返回的跳躍BL PC=label跳躍B
  • 97. 97 Branch and Link Instructions (1) •BL instruction save the return address into r14 (lr) BL subroutine ; branch to subroutine CMP r1, #5 ; return to here MOVEQ r1, #0 … subroutine ; subroutine entry point … MOV pc, lr ; return
  • 98. 98 Branch and Link Instructions (2) •Problem –If a subroutine wants to call another subroutine, the original return address, r14, will be overwritten by the second BL instruction •Solution –Push r14 into a stack –The subroutine will often also require some work registers, the old values in these registers can be saved at the same time using a store multiple instruction
  • 99. 99 Branch and Link Instructions (3) BL SUB1 ; branch to subroutine SUB1 … SUB1 STMFD r13!, {r0-r2,r14} ; save work & link register BL SUB2 … LDMFD r13!, {r0-r2, pc} ; restore work register and ; return SUB2 … MOV pc, r14 ; copy r14 into r15 to return
  • 100. 100 Jump Tables (1) •A programmer sometimes wants to call one of a set of subroutines, the choice depending on a value computed by the program BL JUMPTAB .. JUMPTAB CMP r0, #0 BEQ SUB0 CMP r0, #1 BEQ SUB1 CMP r0, #2 BEQ SUB2 .. Note: slow when the list is long, and all subroutines are equally frequent
  • 101. 101 Jump Tables (2) •“DCD”directive instructs the assembler to reserve a word of store and to initialize it to the value of the expression to the right BL JUMPTAB .. JUMPTAB ADR r1, SUBTAB CMP r0, #SUBMAX LDRLS pc, [r1, r0, LSL #2] B ERROR SUBTAB DCD SUB0 DCD SUB1 DCD SUB2 ..
  • 102. 102 Supervisor Calls •SWI: SoftWare Interrupt •The supervisor calls are implemented in system software –They are probably different from one ARM system to another –Most ARM systems implement a common subset of calls in addition to any specific calls required by the particular application ; This routine sends the character in the bottom ; byte of r0 to the use display device SWI SWI_WriteC ; output r0[7:0]
  • 103. 103 Processor Actions for SWI (1) •Save the address of the instruction after the SWI in r14_svc •Save the CPSR in SPSR_svc •Enter supervisor mode •Disable IRQs •Set the PC to 0x8
  • 104. 104 Processor Actions for SWI (2) ... ADD r0, r1, r2 SWI 0x6 ADD r1, r2, r2 ... Reset Undef instr. SWI Prefetch abort Data abort Reserved IRQ FIQ 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c SWI handler ... User Program Vector Table SWI handler
  • 105. 105 Processor Actions for SWI (3) ... ADD r0, r1, r2 SWI 0x6 ADD r1, r2, r2 ... Reset Undef instr. SWI Prefetch abort Data abort Reserved IRQ FIQ 0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c switch (rn) { case 0x1: … case 0x6: ... } User Program Vector Table SWI handler
  • 106. 106 ARM Instruction Set •Data processing instructions •Data transfer instructions •Control flow instructions •Writing simple assembly language programs
  • 107. 107 Writing Simple Assembly Language Programs (ARM ADS) AREA HelloW, CODE, READONLY SWI_WriteC EQU &0 SWI_Exit EQU &11 ENTRY START ADR r1, TEXT LOOP LDRB r0, [r1], #1 CMP r0, #0 SWINE SWI_WriteC BNE LOOP SWI SWI_Exit TEXT = "Hello World",&0a,&0d,0 END AREA: chunks of data or code that are manipulated by the linker ENTRY: The first instruction to be executed within an application is marked by the ENTRY directive. An application can contain only a single entry point. EQU: give a symbolic name to a numeric constant (*) DCB: allocate one or more bytes of memory and define initial runtime content of memory (=)
  • 108. 108 General Assembly Form (ARM ADS) •The three sections are separated by at least one whitespace character (a space or a tab) • Actual instructions never start in the first column, since they must be preceded by whitespace, even if there is no label •All three sections are optional label <whitespace> instruction <whitespace> ;comment
  • 109. 109 GNU GAS Basic Format (1) .section .text .global main .type main,%function main: MOV r0, #100 ADD r0, r0, r0 .end •Assemble the following code into a section •Similar to “AREA”in armasm Filename: test.s
  • 110. 110 GNU GAS Basic Format (2) .section .text .global main .type main,%function main: MOV r0, #100 ADD r0, r0, r0 .end •“.global”makes the symbol visible to ld •Similar to “EXPORT”in armasm Filename: test.s
  • 111. 111 GNU ARM Basic Format (3) .section .text .global main .type main,%function main: MOV r0, #100 ADD r0, r0, r0 .end •This sets the type of symbol name to be either a function symbol or an object symbol •“.end”marks the end of the assembly file •Assembler does not process anything in the file past the “.end”directive Filename: test.s
  • 112. 112 GNU ARM Basic Format (4) .section .text .global main .type main,%function main: MOV r0, #100 ADD r0, r0, r0 .end •LABEL透過”:”來做識別 •armasm則是透過指令和保留 字的縮排來做識別 Filename: test.s •Comments •/* …your comments... */ •@ your comments (line comment)
  • 113. 113 Thumb Instruction Set •Thumb addresses code density –A compressed form of a subset of the ARM instruction set •Thumb maps onto ARMs –Dynamic decompression in an ARM instruction pipeline –Instructions execute as standard ARM instructions within the processor •Thumb is not a complete architecture •Thumb is fully supported by ARM development tools •Design for processor / compiler, not for programmer
  • 114. 114 Thumb-ARM Differences (1) •All Thumb instructions are 16-bits long –ARM instructions are 32-bits long •Most Thumb instructions are executed unconditionally –All ARM instructions are executed conditionally
  • 115. 115 Thumb-ARM Differences (2) •Many Thumb data processing instructions use a 2-address format (the destination register is the same as one of the source registers) –ARM use 3-address format •Thumb instruction are less regular than ARM instruction formats, as a result of the dense encoding
  • 116. 116 Thumb Applications •Thumb properties –Thumb requires 70% space of the ARM code –Thumb uses 40% more instructions than the ARM code –With 32-bit memory, the ARM code is 40% faster than the Thumb code –With 16-bit memory, the Thumb code is 45% faster than the ARM code –Thumb uses 30% less external memory power than ARM code
  • 117. 117 DSP Extensions •DSP Extensions “E” –16bit Multiply and Multiply-Accumulate instructions –Saturated, signed arithmetic –Introduced in v5TE –Available in ARM9E, ARM10E and Jaguar families
  • 118. 118 ARM Java Extensions - JazelleTM •Direct execution of Java ByteCode •8x Performance of Software JVM (Embedded CaffeineMark3.0) •Over 80% power reduction for Java Applications •Single Processor for Java and existing OS/applications •Supported by leading Java Run-time environments and operating systems •Available in ARM9, ARM10 & Jaguar families
  • 119. 119 ARM Media Extensions (ARM v6) •Applications –Audio processing –MPEG4 encode/decode –Speech Recognition –Handwriting Recognition –Viterbi Processing –FFT Processing •Includes –8 & 16-bit SIMD operations –ADD, SUB, MAC, Select •Up to 4x performance for no extra power •Introduced in ARM v6 architecture, Available in Jaguar
  • 120. 120 ARM Architectures THUMBTM DSP JazelleTM Media •Enhance performance through innovation – THUMBTM: 30% code compression – DSP Extensions: Higher performance for fixed-point DSP – JazelleTM: up to 8x performance for java – Media Extensions up to 4x performance for audio & video •Preserve Software Investment through compatibility Architecture v4T v5TE v5TEJ v6 Feature Set
  • 123. AMBA Bridge Timer On-chip RAM ARM Interrupt Controller Remap/ Pause TIC Arbiter Bus InterfaceExternal ROM External RAM Reset System Bus Peripheral Bus • AMBA – Advanced Microcontroller Bus Architecture • ADK – Complete AMBA Design Kit • ACT – AMBA Compliance Testbench • PrimeCell – ARM’s AMBA compliant peripherals AHB or ASB APB External Bus Interface Decoder reference: http://www.intel.com/education/highered/modelcurriculum.htm
  • 124. 124 ARM Coprocessor Interface •ARM supports a general-purpose extension of its instructions set through the addition of hardware coprocessor •Coprocessor architecture –Up to 16 logical coprocessors –Each coprocessor can have up to 16 private registers (any reasonable size) –Using load-store architecture and some instructions to communicate with ARM registers and memory.
  • 125. 125 ARM7TDMI Coprocessor Interface •Based on “bus watching”technique •The coprocessor is attached to a bus where the ARM instruction stream flows into the ARM •The coprocessor copies the instructions into an internal pipeline •A “hand-shake”between the ARM and the coprocessor confirms that they are both ready to execute coprocessor instructions
  • 128. 128 Development Tools (2) binutilsfromelf Format converter Simulator in GDBARMulatorSimulator GDB, InsightArmsd, AXDDebugger newlibC libraryC library binutilsarmlinkLinker binutilsarmasmAssembler gccarmccCompiler GNUARM ADS
  • 129. 129 The Structure of ARM Cross- Development Toolkit assemblerC compiler C source asm source .aof C libraries linker .axf ARMsd debug ARMulator development system model board object libraries