2013 2014 ieee vlsi titles
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This document lists 28 titles of papers presented at the 2013-2014 IEEE VLSI Symposia. The papers cover a wide range of topics related to VLSI systems design, including low-power camera architectures, turbo decoder designs, on-chip voltage regulators, comparator designs, built-in self-test techniques, reconfigurable hardware, power converters, delay line designs, job scheduling, signal processors, DAC testing, memristor modeling, reliable networks-on-chip, SAR ADC designs, frequency synthesizers, power gating, and random number generation.
2013 2014 ieee vlsi titles
- 1. IEEE 2013-2014 VLSI TITLES 1. A High Speed Low Power Cam With A Parity Bit And Power-Gated Ml Sensing 2. A Low-Complexity Turbo Decoder Architecture For Energy-Efficient Wireless Sensor Networks 3. Active Filter-Based Hybrid On-Chip Dc–Dc Converter For Point-Of-Load Voltage Regulation 4. Analysis And Design Of A Low-Voltage Low-Power Double-Tail Comparator 5. Broad Side And Skewed-Load Tests Under Primary Input Constraints 6. Built-In Generation Of Functional Broadside Tests Using A Fixed Hardware Structure 7. C-Based Complex Event Processing On Reconfigurable Hardware 8. Design And Analysis Of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping And Numerically Controlled OscillatorBased Frequency Modulation 9. Eliminating Synchronization Latency Using Sequenced Latching 10. Error Detection In Majority Logic Decoding Of Euclidean Geometry Low Density Parity Check (Eg-Ldpc) Codes 11. Gate Mapping Automation For Asynchronous Null Convention Logic Circuits 12. Glitch-Free Nand-Based Digitally Controlled Delay-Lines 13. Isonet: Hardware-Based Job Queue Management For Many-Core Architectures 14. Low-Power Digital Signal Processor Architecture For Wireless Sensor Nodes 15. Low-Resolution Dac-Driven Linearity Testing Of Higher Resolution Adcs Using Polynomial Fitting Measurements 16. MDC FFTIFFT Processor with Variable Length For MIMO-OFDM Systems
- 2. 17. Multi voltage Aware Resistive Open Fault Model 18. Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment 19. RATS Restoration-Aware Trace Signal Selection for Post-Silicon Validation 20. Robust Hybrid Memristor-CMOS Memory Modeling and Design 21. Self-Repairing Digital System With Unified Recovery Process Inspired By Endocrine Cellular Communication 22. Smart Reliable NetworkonChip 23. Split-SAR ADCs Improved Linearity With Power and Speed Optimization 24. Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD 25. Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches 26. Test Patterns of Multiple SIC Vectors Theory and Application in BIST Schemes 27. The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures 28. Time-Based All-Digital Technique for Analog Built-in Self-Test