2.computer org.

Unit – 4 Computer Organization Ch- 5 & 7 Morris Mano

Instruction Codes The organization of the computer is defined by its internal registers, the timing and control structure, and the set of instructions that it uses. The internal organization of a digital system is defined by the sequence of micro-operations it performs on data stored in its registers. The user can control the process by means of a program. A program is a set of instructions that specify the operations, operands & the sequence by which processing has to occur. A computer instruction is a binary code that specifies a sequence of microoperations for the computer. Every computer has its own instruction set. Instruction codes together with data are stored in memory. The computer reads each instruction from memory and places it in a control register. The control then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of micro-operations. An instruction code is a group of bits that instructs the computer to perform a specific operation.

It is usually divided into parts, each having its own interpretation. The most basic part of an instruction code is its operation part. For every operation code, the control issues a sequence of micro-operations needed for the hardware implementation of the specified operation. An instruction code must specify not only the operation but also the registers or the memory words where the result is to be stored. Memory words can be specified in instruction codes by their address.

Stored Program Organization : The simplest way to organize a computer is to have one processor register and an instruction code format with 2 parts. The first part specifies the operation to be performed and the second part specifies an address. Computers that have a single processor register usually assign to it the name accumulator and label it AC.

Stored program Organization (Fig 5.1) Opcode Address Binary Operand Instructions (Program) Operands (data) Memory 4096 x 16 Instruction format Processor register (AC) 15 12 11 0 15 0

Computer Registers (Fig 5-4 M.M.) The computer needs processor registers for manipulating data and a register for holding a memory address. List of Registers 1. DR DATA REGISTER 2. AR ADDRESS REGISTER 3. AC ACCUMULATOR 4. IR INSTRUCTION REGISTER 5. PC PROGRAM COUNTER 6. TR TEMPORARY REGISTER 7. INPR INPUT REGISTER 8. OUTR OUTPUT REGISTER

The AR and PC register has 12 bits since this is the width of a memory address. The DR holds the operand read from memory. The AC register is a general-purpose processing register. The instruction read from memory are placed in the IR. The TR is used for holding temporary data during processing. Two registers INPR and OUTR are used for input and output device and these are of 8 bits.

COMMON BUS SYSTEM (Fig 5.4) The basic computer has 8 registers, a memory unit and a control unit. Paths must be provided to transfer information from one register to another and between memory and registers. The no. of wires will be excessive if connections are made between the output of each register and the inputs of other registers. A more efficient scheme for transferring information in a system with many registers is to use a common bus.

COMPUTER INSTRUCTIONS INSTRUCTION FORMAT : The basic computer has 3 instruction code formats. Each format has 16 bits. The operation code (opcode) part of the instruction contains 3 bits and the meaning of the remaining 13 bits depends on the operation code encountered. A memory-reference instruction uses 12 bits to specify an address and one bit to specify the addressing mode I. I is equal to 0 for direct address and 1 for indirect address. The register-reference instruction does not need operand from memory ; therefore 12 bits are used to specify the operation to be executed. Register-reference instructions are recognized by opcode 111 and 0 in the leftmost bit. Input-output reference instructions are recognized by opcode 111 and 1 in the leftmost bit. The remaining 12 bits are used to specify the type of input-output operation.

Basic Computer Instruction formats (Table 5.2) I Opcode Address 0 1 1 1 Register operation 1 1 1 1 I/O operation 15 14 12 11 0 15 12 11 0 15 14 12 11 0

INSTRUCTION SET COMPLETENESS The set of instructions are said to be complete if the computer includes a sufficient number of instructions in each of the following categories: Arithmetic, logical and shift instructions Instructions for moving information to and from memory and processor registers Program control instructions together with instructions that check status conditions Input and output instructions

TIMING AND CONTROL (Sec 5.4) The timing for all registers in the basic computer is controlled by a master clock generator. The clock pulses are applied to all flip-flops and registers in the system, including the flip-flops and registers in the control unit. The clock pulses do not change the state of a register unless the register is enabled by a control signal. The control signals are generated in the control unit.

2 TYPES OF CONTROL ORGANIZATIONS: Hardwired control Microprogrammed control Hardwired control : In this the control logic is implemented with gates, flip-flops, decoders and other digital circuits. Advantage: Can be optimized to produce a fast mode of operation. Microprogrammed Control : In the microprogrammed organization, the control information is stored in a control memory. The control memory is programmed to initiate the required sequence of microoperations. Any updation can be easily done by updating the microprogram in control memory.

Control Unit of Basic Computer (Fig 5.6) It consists of 2 decoders, a sequence counter and a number of control logic gates. An instruction read from memory is placed in the IR where it is divided into 3 parts: the I bit, opcode and bits 0 through 11. The 4 bit sequence counter can count in binary from 0 through 15. The outputs of the counter are decoded into 16 timing signals T 0 Through T 15 .

Accumulator Logic (Sec-5.10) Refer fig 5-19 The adder and logic circuit has 3 sets of inputs. One set of 16 inputs comes from the output of AC. Another set of 16 inputs comes from DR. A third set of 8 inputs comes from the input register INPR. The output of the adder and logic circuit provide the data inputs for the register. In addition, it is necessary to include logic gates for controlling the LD, INR and CLR inputs for controlling the operation of the adder and logic circuit.

CONTROL OF AC REGISTER: Refer the figure 5-20 The gate structure controls the LD,INR and CLR inputs of AC . The output of the gate that generates the control function for the clear micro-operation is connected to the CLR input of the register . Similarly, the output of the gate that implements the increment micro-operation is connected to the INR input of the register. The other 7 micro-operations are generated in the adder and logic circuit and are loaded into AC at the proper time. These outputs are used in the design of the adder and logic circuit.

Adder and Logic Circuit: The adder and logic circuit can be subdivided into 16 stages, with each stage corresponding to 1 bit of AC. Each stage has a JK flip-flop and 2 AND gates. One stage of the adder and logic circuit consists of 7 AND gates, one OR gate and a full-adder (FA). The AND operation is achieved by ANDing AC(i) with the corresponding bit in the date register DR(i). The ADD operation is obtained using a binary adder . The complement micro-operation is obtained by inverting the bit value in AC. The complete adder and logic circuit consists of 16 stages connected together.

CONTROL MEMORY (Chapter 7 M.M.) The function of the control unit is to initiate sequences of micro-operations. The control function that specifies a micro-operation is a binary variable. When it is in one binary state, the corresponding micro-operations is executed. A control variable in the opposite binary state does not change the state of the registers in the system. A control unit whose binary variables are stored in memory is called a microprogrammed control unit. Each word in control memory contains within it a micro-instruction. The micro-instruction specifies one or more micro-operations for the system. Since alterations of the micro-program are not needed once the control unit is on operation, the control memory can be a read-only memory (ROM).

A more advanced development known as dynamic micro-programming permits a micro-program to be loaded initially from an auxiliary memory such as a magnetic disk. A memory that is a part of control unit is referred to as a control memory . A computer that employs a micro-programmed control unit will have 2 separate memories: A main memory and a control memory. The control memory holds a fixed micro-program that cannot be altered by the occasional user. The micro-instructions generate the micro-operations to fetch the instruction from memory.

Refer the figure –7.1 The control memory is assumed to be a ROM, within which all control information is permanently stored. The control address register specifies the address of the micro-instruction. The control data register holds the micro-instruction read from memory. The next address generator is called a micro-program sequencer, as it determines the address sequence that is read from control memory. The main advantage of microprogrammed control is the fact that once the hardware configuration is established, there should be no need for further hardware or wiring changes. If we want to establish a different control sequence for the system, all we need to do is specifying a different set of micro-instructions for the control memory.

Address Sequencing (Chapter 7 M.M.) Micro-instructions are stored in control memory in groups, with each group specifying a routine. Each instruction has its own micro-program routine in control memory to generate the micro-operations that execute the instruction. The hardware must be capable of sequencing the micro-instructions within a routine and be able to branch from one routine to another. Steps for Address Sequencing: An initial address is loaded into the control address register when power is turned on in the computer. The fetch routine may be sequenced by incrementing the control address register through the rest of micro-instructions. The control memory next must go through the routine that determines the effective address of the operand. The effective address computation routine in control memory can be reached through a branch micro-instruction.

When the effective address computation routine is completed, the address of the operand is available in the memory address register. The next step is to generate the micro-operations that execute the instruction fetched from memory. The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process. A mapping procedure is a rule that transforms the instruction code into a control memory address. After the required routine is reached, the micro-instructions that execute the instruction may be sequenced by incrementing the control address register. The address sequencing capabilities required in a control memory are: Incrementing of the control address register. Unconditional branch or conditional branch, depending on status bit conditions. A mapping process from the bits of the instruction to an address for control memory. A facility for subroutine call and return.

Refer the figure-7.2 The micro-instruction in control memory contains a set of bits to initiate micro-operations in computer registers and other bits to specify the method by which the next address is obtained. There are 4 different paths from which the Control Address Register (CAR) receives the address. The incrementer increments the content of the control address register by one, to select the next microinstruction in sequence. Branching is achieved by specifying the branch address in one of the fields of the micro-instruction. Conditional branching is obtained by using part of the micro-instruction to select a specific status bit in order to determine its condition. The return address for a subroutine is stored in a special register whose value is then used when the micro-program wishes to return from the subroutine.

Mapping Of Instruction: A special type of branch exists when a micro-instruction specifies a branch to the first word in control memory where a micro-program routine for an instruction is located. The status bits for this type of branch are the bits in the operation code part of the instruction. The mapping function is sometimes implemented by means of an integrated circuit called programmable logic device or PLD. A PLD is similar to ROM in concept except that it uses AND and OR gates with internal electronic fuses. Subroutines: Subroutines are programs that are used by other routines to accomplish a particular task. A subroutine can be called from any point within the main body of the micro program. Micro-instructions can be saved by employing subroutines that use common sections of micro-code. For example, the sequence of micro-operations needed to generate the effective address of the operand for an instruction is common to all memory-reference instructions .

MICRO-INSTRUCTION FORMAT (Chapter 7 M.M.) Refer the figure 7.6 The 20 bits of the micro-instruction are divided into 4 functional parts. The 3 fields F1,F2 AND F3 specify micro-operations for the computer. The CD field selects status bit conditions. The BR field specifies the type of branch to be used. The AD field contains a branch address. The address field is 7 bits wide, since the control memory has 128=2 7 words. The micro-operations are subdivided into 3 fields of 3 bits each. The 3 bits in each field are enclosed to specify 7 distinct micro-operations. This gives a total of 21 microoperations. No more than 3 microoperations can be chosen for a micro-instruction, one from each field. If fewer than 3 microoperations are to be used, one or more of the fields will use the binary code 000 for no operation.

The CD (condition) field consists of 2 bits which are encoded to specify 4 status bit conditions. The BR(BRANCH) field consists of 2 bits. It is used in conjunction with the address field AD, to choose the address of the next micro-instruction. It can be jump, call, return. SYMBOLIC MICRO-INSTRUCTION: A symbolic micro-program can be translated into its binary equivalent by means of an assembler. The simplest way to formulate an assembly language for a micro-program is to define symbols for each field of the micro-instruction and to give users the capability for defining their own symbolic addresses. Each micro-instruction is divided into 5 fields: Label, microoperations, CD, BR and AD.

The fields specify the following information: The label field may be empty or it may specify a symbolic addresses. A label is terminated with a colon (:). The microoperations field consists of one, two or three symbols, separated by commas. The CD field has one letter like U (Unconditional branch). The BR field contains one symbol. The AD field specifies a value for the address field of the micro-instruction.

Instruction Cycle A program residing in the memory unit of the computer consists of a sequence of instructions. The program is executed in the computer by going through a cycle for each instruction. Each instruction cycle is subdivided into a sequence of phases. In the basic computer each instruction cycle consists of the following phases: Fetch an instruction from memory. Decode the instruction. Read the effective address from memory if the instruction has an indirect address. Execute the instruction. (Note (very Important) : Fig 5-9 Flow Chart for Instruction Cycle)

Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the next instruction. Fetch and Decode Initially, the program counter PC is loaded with the address of the first instruction in the program. The sequence counter SC is cleared to 0, providing a decoded timing signal T 0 . After each clock pulse, SC is incremented by one, so that the timing signals go through a sequence T 0 , T 1 , T 2 and so on.

The micro-operations for the fetch and decode phases can be specified by the following register transfer statements. T O : AR PC T 1 : IR M[AR], PC PC + 1 T 2 : D 0 ,….., D 7 Decode IR(12-14). AR IR(0-11), I IR(15) Since only AR is connected to the address inputs of memory, it is necessary to transfer the address from PC to AR during the clock translation associated with timing signal T 0. The instruction read from memory is then placed in the instruction register IR with the clock transition associated with timing signal T 1 .

At the same time, PC is incremented by one to prepare it for the address of the next instruction in the program. At time T 2 , the operation code in IR is decoded, the indirect bit is transferred to flip-flop I, and the address part of the instruction is transferred to AR. Note that SC is incremented after each clock pulse to produce the sequence T 0 , T 1 and T 2 . Refer to figure 5-8.

To provide the data path for the transfer of PC to AR we must apply timing signal T 0 to achieve the following connection: Place the content of PC onto the bus by making the bus selection inputs S 2 S 1 S 0 equal to 010. Transfer the content of the bus to AR by enabling the LD inputs of AR. It is necessary to use timing signal T 1 to provide the following connections in the bus systems. Enable the read input of memory. Place the content of memory onto the bus by making S 2 S 1 S 0 =111. Transfer the content of the bus to IR by enabling the LD input of PC. Increment PC by enabling the INR input of PC.

Types of instructions: Memory-Reference Instructions Register-Reference Instructions Input-Output Instructions The Total no. of instructions chosen for the basic computer is equal to 25.

Determine the Type of Instruction The timing signal that is active after the decoding is T 3 . During time T 3 , the control unit determines the type of instruction that was just read from memory. Register-Reference Instructions Register-reference instructions are recognized by the control when D 7 = 1 and I = 0. These instructions use bits 0 through 11 of the instruction code to specify one of 12 instructions. These instructions are executed with the clock transition associated with timing variable T 3 . Each control function needs the Boolean relation D 7 I’T 3 , which we designate for convenience by the symbol r. The control function is distinguished by one of the bits in IR(0-11). We assign the symbol B i to bit i of IR.

The execution of the Register-reference instruction is completed at time T 3 . The sequence counter SC is cleared to 0 and the control goes back to fetch the next instruction with timing signal T 0 . The register-reference instructions are following: CLA rB 11 Clear AC CLE rB 10 Clear E CMA rB 9 Complement AC CME rB 8 Complement E CIR rB 7 Circulate right CIL rB 6 Circulate left INC rB 5 Increment AC SPA rB 4 Skip if positive SNA rB 3 Skip if negative SZA rB 2 Skip if AC zero SZE rB 1 Skip if E zero HLT rB 0 Halt computer

2. Memory-Reference Instructions These are recognized by the control when D 7 =0. When D 7 = 0 and I= 1, then it is Indirect memory-reference instruction. When D 7 = 0 and I = 0, then it is direct memory-reference instruction. The effective address of the instruction is in the address register AR and was placed there during timing signal T 2 when I = 0, or during timing signal T 3 when I = 1. The execution of the memory-reference instruction starts with timing signal T 4 . The actual execution of the instruction in the bus system will require a sequence of micro-operations. This is because data stored in memory can not be processed directly. The data must be read from memory to a register where they can be operated on logic circuits.

Memory-reference instructions are: Symbol Operation Symbolic decoder description ---------------------------------------------------------------- AND D0 AC AC ^ M[AR] ADD D1 AC AC + M[AR] LDA D2 AC M[AR] STA D3 M[AR] AC BUN D4 PC AR BSA D5 M[AR] PC, PC AR + 1 ISZ D6 M[AR] M[AR] + 1, If M[AR] + 1=0 THEN PC PC + 1

3. Input-Output Instructions A computer can serve no useful purpose unless it communicates with the external environment. Instructions and data stored in memory must come from some input device. Computational results must be transmitted to the user through some output device. Input-Output Configuration: The terminal sends and receives serial information. Each quantity of information has eight bits of an alphanumeric code. The serial information from the keyboard is shifted into the input register INPR. The serial information for the printer is stored in the output register OUTR. These 2 registers communicate with a communication interface serially and with the AC in parallel. Refer figure 5-12

The transmitter interface receives serial information from the keyboard and transmits it to INPR. The receiver interface receives information from OUTR and sends it to the printer serially. The 1-bit input flag FGI is a control flip-flop. The flag bit is set to 1 when new information is available in the input device and is cleared to 0 when the information is accepted by the computer. The flag is needed to synchronize the timing rate difference between the input device and the computer. The output register OUTR works similarly but the direction of information flow is reversed.

Input-Output Instructions are needed for transferring information to and from AC register, for checking the flag bits and for controlling the interrupt facility. Input-output Instructions are: SC:- 0 Clear SC INP AC(0-7):- INPR, FGI:- 0 Input character OUT OUTR:-AC(0-7), FGO:- 0 Output character SKI If(FGI =1) then (PC:- PC+1) Skip on Input flag SKO If(FGO =1) then (PC:- PC+1) Skip on output flag ION IEN:-1 Interrupt enable on IOF IEN:-0 Interrupt enable off -------------------------------------------------------------------------------

Microprogram Sequencer (Chapter 7 M.M.) The basic components of a micro-programmed control unit are the control memory and the circuits that selects the next address. The address selection part is called a micro-program sequencer. A micro-program sequencer can be constructed with digital functions to suit a particular application. The purpose of a micro-program sequencer is to present an address to the control memory so that a micro-instruction can be read and executed.

The next address logic of the sequencer determines the specific address source to be loaded into the control address register. The choice of the address source is guided by the next-address information bits that the sequencer receives from the present micro-instruction. Refer the figure… There are 2 multiplexers in the circuit. The first multiplexer selects an address from one of 4 sources and routes it into a Control Address Register (CAR). The second multiplexer tests the value of a selected status bit and the result of the test is applied to an input logic circuit. The output from CAR provides the address for the control memory.

The content of CAR is incremented and applied to one of the multiplexer inputs and to the subroutine register SBR. The CD field of the micro-instruction selects one of the status bits in the multiplexer. If the bit selected is equal to 1, the T (test) variable is equal to 1; otherwise it is equal to 0. The T value together with the two bits from the BR (branch) field go to an input logic circuit. The input logic in a particular sequencer will determine the type of operations that are available in the unit.

The typical sequencer operations are: increment, branch or jump, call and return from subroutine, load an external address, push or pop the stack and other address sequencing operations. With 3 inputs, the sequencer can provide up to 8 address sequencing operations. The input logic circuit has 3 inputs, I 0 ,I 1 and T and 3 outputs, S 0 ,S 1 and L. Variables S 0 and S 1 select one of the source addresses for CAR. Variable L enables the load input in SBR. The binary values of the 2 selection variables determine the path in the multiplexer. For example, with S 1 S 0 = 10, multiplexer input number 2 is selected and establishes a transfer path from SBR to CAR.

Stack Organization A stack is a storage device that stores the information in such a manner that the item stored last is the first item received. The register that holds the address for the stack is called a stack pointer (SP) because its value always points at the top item of the stack. The 2 operations of stack are PUSH (for insertion) and POP (For deletion).

REGISTER STACK: A stack can be placed in a portion of a large memory or it can be organized as a collection of a finite number of memory words or registers. For example, in a 64-word stack, the SP contains 6 bits because 2 6 =64. There are 2 one-bit registers FULL and EMTY. If stack is full, then FULL is set to 1. When the stack is empty of item, EMTY is set to 1. DR is the data register that holds the binary data to be written or read out of the stack.

MEMORY STACK : A stack can be implemented in RAM attached to the CPU. The implementation of a stack in the CPU is done by assigning a portion of memory to a stack operation and using a processor register as a stack pointer. S tack limits: Most computers do not provide hardware to check overflow ( full stack ) or underflow (empty stack). The stack limits can be checked by using two processors registers: One to hold the upper limit and the other to hold the lower limit. After a push operation, SP is compared with the upper-limit register and after a pop operation, SP is compared with the lower-limit register.

A stack organization is very effective for evaluating arithmetic expressions. The common arithmetic expressions are written in infix notation, with each operator written between the operands, but it causes some difficulties when expression is evaluated by the computer. For example, A * B + C * D So, we can use Prefix notation or Postfix notation.

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