This document contains questions from a seventh semester computer engineering exam on advanced computer architecture. It asks questions about instruction set architecture, pipelining, hazards, and branch prediction. Specifically:
- Part A asks about ISA dimensions, MTTF calculations, and emerging technologies critical to modern implementations. It also asks about pipeline stages and minimizing hazards through forwarding.
- Part B asks about scheduling and unrolling a MIPS loop to calculate cycles per iteration under different scenarios. It also asks about drawbacks of 1-bit dynamic branch prediction and how 2-bit prediction overcomes this.