8051 Microcontroller

8051 Micro-controller
Ravikumar Tiwari
Assistant Professor
Dept. of Electronics Engineering,
G.H. Raisoni College of Engineering,Nagpur
ravikumar.tiwari@raisoni.net

Three criteria in Choosing a
Microcontroller
R.K.Tiwari(ravikumar.tiwari@raisoni.net)
 meeting the computing needs of the task efficiently
and cost effectively
◦ speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption
◦ easy to upgrade
◦ cost per unit
◦ Noise of environment
 availability of software development tools
◦ assemblers, debuggers, C compilers, emulator, simulator,
technical support
 wide availability and reliable sources of the
microcontrollers

Comparison of the 8051 Family
Members
 ROM type
◦ 8031 no ROM
◦ 80xx mask ROM
◦ 87xx EPROM
◦ 89xx Flash EEPROM
 89xx
◦ 8951
◦ 8952
◦ 8953
◦ 8955
◦ 898252
◦ 891051
◦ 892051
 Example (AT89C51,AT89LV51)
◦ AT= ATMEL(Manufacture)
◦ C = CMOS technology
◦ LV= Low Power(3.0v)

8051 Basic Component/
Feature
 4K bytes internal ROM
 128 bytes internal RAM
 Four 8-bit I/O ports (P0 - P3).
 Two 16-bit timers/counters
 One serial interface
 64k external memory for code
 64k external memory for data
 210 bit addressable

The basic 8051 Core
• 8-bit CPU optimized for control applications
• Capability for single bit Boolean operations.
• Supports up to 64K of program memory.
• Supports up to 64K of data memory.
• 4 K bytes of on-chip program memory.
• Newer devices provide more.
• 128 or 256 bytes of on-chip data RAM
• Four 8 bit ports.
• Two 16-bit timer/counters
• UART
• Interrupts
• On-chip clock oscillator

General Block Diagram
CPU
On-chip
RAM
On-chip
ROM for
program
code
4 I/O Ports
Timer 0
Serial
PortOSC
Interrupt
Control
External interrupts
Timer 1
Timer/Counter
Bus
Control
TxD RxDP0 P1 P2 P3
Address/Data
Counter
Inputs

8051 Internal Block Diagram

8051
Schematic
Pin out

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P1.0
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL1
(INT0)P3.2
(RD)P3.7
(WR)P3.6
Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051
(8031)
(8751)
(8951)
(INT1)P3.3
P1.1
XTAL2
GND
8051
Foot Print

Power-On RESET Circuit
30 pF
30 pF
8.2 K
10 uF
+
11.0592 MHz
EA/VPP
X1
X2
RST
31
19
18
9
Vcc

Port 0 with Pull-Up Resistors
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
DS5000
8751
8951
Vcc
10 K
Port
0

IMPORTANT PINS
(IO Ports)
One of the most useful features of the 8051 is that it
contains four I/O ports (P0 - P3)
Each port can be used as input or output (bi-direction)
Port 0
pins 32-39 （P0.0～P0.7）
◦ 8-bit R/W - General
Purpose I/O
◦ Or acts as a
multiplexed low byte
address and data
bus for external
memory design

IMPORTANT PINS (IO Ports)
 Port 1
（pins 1-8）（P1.0～
P1.7）
◦ Only 8-bit R/W -
General Purpose
I/O

 Port 2
 （pins 21-28（P2.0
～P2.7）
◦ 8-bit R/W -
General
Purpose I/O
◦ Or high byte of
the address
bus for external
memory design

 Port 3
 （pins 10-17 （P3.0～
P3.7）
◦ General Purpose
I/O
◦ if not using any of
the internal
peripherals (timers)
or external
interrupts.

Port 3 Alternate Functions

 ALE - Address latch enable
to select valid address
 EA/Vpp - External access enable
EA-0 execute program in external
memory
EA-1 execute program in internal
memory
Vpp it receives 21 V for on chip EPROM
PSEN Program store enable
store to read the external program memory

Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the
8051

Parallel I/O Ports
• Each port can be input or output
• Direction is set in Special Function
Registers
Port0
latch
Port1
latch
Port2
latch
Port3
latch
Port0 Port1 Port2 Port3

DPTR
 The data pointer consists of a high
byte(DPH) and a low byte (DPL). Its
function is to hold a 16 bit address. It
may be manipulated as a 16 bit data
register or two independent 8 bit
register. It serves as a base register in
indirect jumps, lookup table
instructions and external data transfer.

PROGRAM STATUS WORD
(PSW)
CY AC F0 RS1 RS0 OV P
RS0 RS
1
BANK SELECTION
0 0 00H – 07H BANK0
0 1 08H – 0FH BANK 1
1 0 10H – 17H BANK2
1 1 18H – 1FH BANK 3

Memory Organization
 The 8051 memory organization is rather complex.
 The 8051 has separate address spaces for
Program Memory, Data Memory, and external
RAM.
 This is refereed to as a Harvard architecture.
 Both program memory and external data memory
are 8 bits wide and use 16 bits of address. The
internal data memory is accessed using an 8-bit
address.
 Since the same address can refer to different
locations the specific location is determined by the
type of instruction.

RAM Memory Space
Allocation
 There are 128 bytes of RAM in 8051.
 The 128 bytes of RAM inside 8051 are
assigned addresses 00h to 7FH.
 These 128 bytes are divided into three
different groups as Follows:

RAM Memory Space
Allocation
 1. A total of 32 bytes from location 00
to 1F hex are set aside for register
banks and the stack( 4 register bank
each of 8 byte)
 2. A total of 16 byte from location 20h
to 2F h are set aside for bit
addressable RAM.
 3. A total of 80bytes from 30h to 7Fh
are used for RD/WR storage which is
normally called as Scratch Pad.

RAM Memory Space
Allocation
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(Stack) Register Bank
1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM

Stack in the 8051
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(Stack) Register Bank
1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
 The register used to access
the stack is called SP (stack
pointer) register.
 The stack pointer in the
8051 is only 8 bits wide,
which means that it can
take value 00 to FFH. When
8051 powered up, the SP
register contains value 07.

8051 Microcontroller

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8051 Microcontroller