unit-2.pptx
- 1. Arya College of Engineering & IT. Kukas-Jaipur Microprocessor Prepared By Dr. Priyanka Jain Department of Electrical Engineering
- 3. 3 The overall system cost is high. Alarge sized PCB is required for assembling all the components. Overall product design requires more time. Physical size of the product is big. Adiscrete components are used, the system is not reliable. Disadvantages of microprocessor
- 4. 4 As the peripherals are integrated into a single chip, the overall system cost is very less. The product is of small size compared to micro processor based system. The system design now requires very little efforts As the peripherals are integrated with a microprocessor the system is more reliable. Though microcontroller may have on chip ROM,RAM and I/O ports, addition ROM, RAM I/O ports may be interfaced externally if required. On chip ROM provide a software security. Advantages of Microcontroller based System
- 5. 5 meeting the computing needs of the task efficiently and cost effectively. • speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption. • easy to upgrade. • cost per unit. • Noise of environment. availability of software development tools • assemblers, debuggers, C compilers, emulator, simulator, technical support wide availability and reliable sources of the microcontrollers Why we Choosing a Microcontroller
- 6. 6 ROM type • 8031 no ROM • 80xx mask ROM • 87xx EPROM • 89xx Flash EEPROM 89xx • 8951 • 8952 • 8953 • 8955 • 898252 • 891051 • 892051 Comparison of the 8051 Family Members Example (AT89C51,AT89LV51) AT= ATMEL(Manufacture) C = CMOS technology LV= Low Power(3.0v)
- 7. 7 Comparison some of the 8051 Family Members ROM RAM Timer 8051 4k 128 2 8031 - 128 2 8751 4k eprom 128 2 8052 8krom 256 3 8032 - 256 3 8752 8k eprom 256 3
- 8. 4K bytes internal ROM 128 bytes internal RAM Four 8-bit I/O ports (P0 - P3). Two 16-bit timers/counters One serial interface 64k external memory for code 64k external memory for data 210 bit addressable Microcontroller 8051 Basic Component 8
- 9. 9 The basic 8051 Core 8-bit CPU optimized for control applications Capability for single bit Boolean operations. Supports up to 64K of program memory. Supports up to 64K of data memory. 4 K bytes of on-chip program memory. Newer devices provide more. 128 or 256 bytes of on-chip data RAM. Four 8 bit ports. Two 16-bit timer/counters UART. Interrupts. On-chip clock oscillator.
- 10. 10 S. No Microprocessor Microcontroller 1 Amicroprocessor is a general purpose device which is called a CPU A microcontroller is a dedicated chip which is also called single chip computer. 2 Amicroprocessor do not contain onchip I/OPorts, Timers, Memories etc.. Amicrocontroller includes RAM, ROM, serial and parallel interface, timers, interrupt circuitry (in addition to CPU) in a single chip. 3 Microprocessors are most commonly used as the CPU in microcomputer systems Microcontrollers are used in small, minimum component designs performing control-oriented applications. 4 Microprocessor instructions are mainly nibble or byte addressable Microcontroller instructions are both bit addressable as well as byte addressable. 5 Microprocessor instruction sets are mainly intended for catering to large volumes of data. Microcontrollers have instruction sets catering to the control of inputs and outputs. Differences between 8086 and 8051
- 11. 11 6 Microprocessor based system design is complex and expensive Microcontroller based system design is rather simple and cost effective 7 The Instruction set of microprocessor is complex with large number of instructions. The instruction set of a Microcontroller is very simple with less number of instructions. For, ex: PIC microcontrollers have only 35 instructions. 8 Amicroprocessor has zero status flag Amicrocontroller has no zero flag. Differences between 8086 and 8051 cont…
- 12. Block diagram of 8051 Figure: Block diagram of 8051 12
- 13. Block Diagram CPU On-chip RAM On-chip ROM for program code 4 I/O Ports Serial Port OSC Interrupt Control External interrupts Timer/Counter Timer 1 Timer 0 Bus Control TxD RxD P0 P1 P2 P3 Address/Data Counter Inputs 13
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- 18. Power-On RESET Circuit 30 pF 30 pF 8.2 K Vcc + 10 uF 11.0592 MHz EA/VPP X1 X2 RST 31 19 18 9 18
- 19. Port 0 with Pull-Up Resistors P0.0 DS5000 P0.1 8751 P0.2 8951 P0.3 P0.4 P0.5 P0.6 P0.7 Vcc 19 10 K Port 0
- 20. • Port 0 pins 32-39 （P0.0～P0.7） – 8-bit R/W - General Purpose I/O. – Or acts as a multiplexed low byte address and data bus for external memory design. IMPORTANT PINS (IO Ports) One of the most useful features of the 8051 is that it contains four I/O ports (P0 - P3). Each port can be used as input or output (bi-direction). 20
- 21. Port 1 （pins 1-8） （P1.0～P1.7） • Only 8-bit R/W - General Purpose I/O IMPORTANT PINS (IO Ports) 21
- 22. Port 2 （pins 21-28（P2.0～ P2.7） • 8-bit R/W - General Purpose I/O • Or high byte of the address bus for external memory design IMPORTANT PINS (IO Ports) 22
- 23. Port 3 （pins 10-17 （P3.0～P3.7） • General Purpose I/O • if not using any of the internal peripherals (timers) or external interrupts. IMPORTANT PINS (IO Ports) 23
- 25. Hardware Structure of I/O Pin 25 Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 D Q P1.X Clk Q P1.X pin B1 B2
- 26. 26 Each pin of I/O ports • Internally connected to CPU bus. • AD latch store the value of this pin. • Write to latch＝1：write data into the D latch. 2 Tri-state buffer： • B1: controlled by ― Read pin‖. • Read pin＝1：really read the data present at the pin. • B2: controlled by ― Read latch‖. • Read latch＝1：read value from internal latch. Atransistor M1 gate • Gate=0: open • Gate=1: close Hardware Structure of I/O Pin
- 27. Writing - 1 to Output Pin P1.X 27 Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 D Q P1.X Clk Q 2. output pin is Vcc P1.X pin 1. write a 1 to the pin 1 0 output 1 B1 B2
- 28. Writing - 0‖ to Output Pin P1.X 28 Vcc Internal Pull-Up Read latch Read pin Write to latch Internal CPU bus M1 D Q P1.X Clk Q P1.X pin 2. output pin is ground 1. write a 0 to the pin 0 1 output 0 B1 B2
- 29. Reading High‖ at Input Pin 29 Vcc Internal Pull-Up Read latch Write to latch Internal CPU bus M1 D Q P1.X Clk Q P1.Xpin 2. MOV A,P1 external pin=High 1. write a 1 to the pin MOV P1,#0FFH 1 0 1 B1 Read pin 3. Read pin=1 Read latch=0 B2
- 30. Reading Low‖ at Input Pin 30 D Q Clk Q Vcc Internal Pull-Up Read latch Write to latch Internal CPU bus M1 P1.X pin P1.X 2. MOV A,P1 external pin=Low 1. write a 1 to the pin MOV P1,#0FFH 1 0 0 B1 Read pin 3. Read pin=1 Read latch=0 B2
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- 32. Memory organization 32 External DATA Memory (up to 64KB) RAM External CODE Memory (up to 64KB) ROM 8051 Chip 0000h FFFFh FFFFh Internal RAM SFRs Internal code Memory (EEPROM) 0000h
- 33. Types of Memory 33 External Code Memory (64k) External RAM Data Memory (64k) Internal Code Memory • 4k,8k,12k,20k • ROM, EPROM, EEPROM Internal RAM • First 128 bytes: Register Banks. BitAddressable RAM. General Purpose RAM. o 00h to 1Fh o 20h to 2Fh o 30 to 7Fh Next 128 bytes: • 80h to FFh Special Function Registers.
- 34. /EA（pin 31）：External access • /EA=‗0‘indicates that code is stored externally. • /PSEN ＆ ALE are used for external ROM. • For 8051 internal code, /EApin is connected to Vcc. • ― /‖ means active low. /PSEN（pin 29）：program store enable. • Output- connected to OE of ROM. • Read signal – fetch from ROM ALE（pin 30): Address latch enable. • It is an output pin and is active high. • 8051 port 0 provides both address and data. • The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. 252 External Memory
- 36. Program or Code Memory 36 May consist of internal or external program memory. The amount of internal program memory varies depending on the device. 4K bytes typical in older devices. The MOVC instruction can be use to read code memory. To reference code memory I will use the notation: CM = CM(0,…,FFFFH) = CM(0,…,FFFFH; 7,…,0) This notation can be used to specify particular bits and bytes of code memory. For example CM(1234H) refers to the byte of code memory at address 1234H. CM(1234H;7) refers to the most significant bit in that address.
- 37. CM MOVC A,@A + DPTR ;A CM(A+DPTR) MOVC A,@A + PC ;A CM(A+PC) PC = PC(15..0) DPTR = DPTR(15..0) 37
- 38. 38 • The original 8051 had 128 bytes of on-chip data RAM. – This memory includes 4 banks of general purpose registers at DM(00..1F) – Only one bank can be active at a time. – If all four banks are used, DM(20..7F) is available for program data. – DM(20..2F) is bit addressable as BADM(00..7F). • DM(80,…,FF) contains the special function registers such as I/O ports, timers, UART, etc. – Some of these are bit addressable using BADM(80..FF) • On newer versions of the 8051, DM(80,…,FF) is also use as data memory. Thus, the special functions registers and data memory occupy the same address space. Which is accessed is determined by the instruction being used. Data Memory
- 39. Data memory XM DM MOV A,62H MOV R1,#62H MOV A@R1 MOV A,0A2H MOV R1,#0A2H MOV A@R1 39
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- 42. Register set of 8051 42 A B R0 R1 R2 R3 R4 R5 R6 R7 DPH DPL PC DPTR PC Some 8051 16-bit Register Some 8-bitt Registers of the 8051
- 43. DPTR 43 • The data pointer consists of a high byte(DPH) and a low byte (DPL). Its function is to hold a 16 bit address. It may be manipulated as a 16 bit data register or two independent 8 bit register. It serves as a base register in indirect jumps, lookup table instructions and external data transfer.
- 44. CY AC F0 RS1 RS0 OV P PROGRAM STATUS WORD (PSW) 44 R S0 R S 1 BANK SELECTION 0 0 00H – 07H BANK0 0 1 08H – 0FH BANK 1 1 0 10H – 17H BANK2 1 1 18H – 1FH BANK 3
- 45. The register used to access the stack is called SP (stack pointer) register. The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07. Stack in the 8051 45 7FH 30H 2FH 20H 10H 0FH 08H 07H 1FH 18H 17H 00H Register Bank 0 (Stack) Register Bank 1 Register Bank 2 Register Bank 3 Bit-Addressable RAM Scratch pad RAM
- 46. 46 In 8051 microcontroller there certain registers which uses the RAM addresses from 80h to FFh and they are meant for certain specific operations .These registers are called Special function registers (SFRs).Some of these registers are bit addressable also. The list of SFRs and their functional names are given below. In these SFRs some of them are related to I/O ports (P0,P1,P2 and P3) and some of them are meant for control operations (TCON,SCON, PCON..) and remaining are the auxiliary SFRs, in the sense that they don't directly configure the 8051. SPECIALFUNCTION REGISTERS (SFRs)
- 47. 47 S.No Symbol Name of SFR Address (Hex) 1 ACC* Accumulator 0E0 2 B* B-Register 0F0 3 PSW* Program Status word register 0DO 4 SP Stack Pointer Register 81 5 DPT R DPL Data pointer low byte 82 DPH Data pointer high byte 83 6 P0* Port 0 80 P1* Port 1 90 8 P2* Port 2 0A 9 P3* Port 3 0B 10 IP* Interrupt Priority control 0B8 11 IE* Interrupt Enable control 0A8 12 TMOD Tmier mode register 89 13 TCON* Timer control register 88 14 TH0 Timer 0 Higher byte 8C 15 TL0 Timer 0 Lower byte 8A 16 TH1 Timer 1Higher byte 8D 17 TL1 Timer 1 lower byte 8B 18 SCON* Serial control register 98 19 SBUF Serial buffer register 99 20 PCON Power control register 87
- 48. An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. Interrupts vs. Polling A single microcontroller can serve several devices. There are two ways to do that: – interrupts – polling. Interrupts
- 49. In Polling , the microcontroller ‘s program simply checks each of the I/O devices to see if any device needs servicing. If so, it performs the service. In the interrupt method, whenever any device needs microcontroller ‘s service, it tells to microcontroller by sending an interrupt signal. The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.
- 50. Finish current instruction and saves the PC on stack. Jumps to a fixed location in memory depend on type of interrupt. Starts to execute the interrupt service routine until RETI (return from interrupt). Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack. Steps in executing an interrupt
- 51. Original 8051 has 6 sources of interrupts 1. Reset 2. Timer 0 overflow 3. Timer 1 overflow 4. External Interrupt 0 5. External Interrupt 1 6. Serial Port events buffer full, buffer empty, etc) Interrupt Sources
- 52. Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins. External Interrupt 0 Timer 0 overflow External Interrupt 1 Timer 1 overflow Serial Timer 2 overflow(8052+) : : : : : : 0003h 000Bh 0013h 001Bh 0023h 002bh Interrupt Vectors Note: that there are only 8 memory locations between vectors.
- 53. Interrupt Enable (IE) register All interrupt are disabled after reset We can enable and disable them by IE
- 54. Enabling an interrupt by bit operation Recommended in the middle of program SETB EA SETB ET0 SETB ET1 SETB EX0 SETB EX1 SETB ES ;EnableAll ;Enable Timer0 over flow ;Enable Timer1 over flow ;Enable INT0 ;Enable INT1 ;Enable Serial port by mov instruction Recommended in the first of program • MOV IE, #10010110B SETB SETB SETB SETB SETB SETB IE.7 IE.1 IE.3 IE.0 IE.2 IE.4
- 55. Disabling an interrupt CLRB EA ;Disable All CLRB ET0 ; Disable Timer0 over flow CLRB ET1 ; Disable Timer1 over flow CLRB EX0 ; Disable INT0 CLRB EX1 ; Disable INT1 CLRB ES ; Disable Serial port
- 56. What if two interrupt sources interrupt at the same time? The interrupt with the highest PRIORITY gets serviced first. All interrupts have a power on default priority order. 1. External interrupt 0 (INT0) 2. Timer interrupt0 (TF0) 3. External interrupt 1 (INT1) 4. Timer interrupt1 (TF1) 5. Serial communication (RI+TI) Priority can also be set to “high” or “low” by IP reg. Interrupt Priorities
- 57. IP .7: reserved IP .6: reserved IP.5: timer 2 interrupt priority bit(8052 only) IP.4: serial port interrupt priority bit IP.3: timer 1 interrupt priority bit IP.2: external interrupt 1 priority bit IP.1: timer 0 interrupt priority bit IP.0: external interrupt 0 priority bit Interrupt Priorities (IP) Register
- 58. MOV IP , #00000100B or SETB IP.2 gives priority order 1. Int1 2. Int0 3. Timer0 4. Timer1 5. Serial MOV IP , #00001100B gives priority order 1. Int1 2. Timer1 3. Int0 4. Timer0 5. Serial Interrupt Priorities Example --- PX0 --- PT2 PS PT1 PX1 PT0
- 59. Counter/timer hardware is a crucial component of most embedded systems. ... In some cases, a timer measures elapsed time (counting processor clock ticks). In others, we want to count or time external events. The names counter and timer can be used interchangeably when talking about the hardware. 8051 has two 16-bit programmable timers/counters. They can be configured to operate either as timers or as event counters. The names of the two counters are T0 and T1 respectively. The timer content is available in four 8-bit special function registers, viz, TL0,TH0,TL1 and TH1 respectively. In the "timer" function mode, the counter is incremented in every machine cycle. Thus, one can think of it as counting machine cycles. Hence the clock rate is 1/12 th of the oscillator frequency. In the "counter" function mode, the register is incremented in response to a 1 to 0 transition at its corresponding external input pin (T0 or T1). It requires 2 machine cycles to detect a high to low transition. Hence maximum count rate is 1/24 th of oscillator frequency. TIMER/COUNTER
- 60. The operation of the timers/counters is controlled by two special function registers, TMOD and TCON respectively. Timer Mode control (TMOD) Special Function Register: TMOD register is not bit addressable. TMOD Address: 89 H Operation of Timer/Counter
- 61. Various bits of TMOD are described as follows -
- 62. Timer/ Counter control logic: Figure: Timer/ Counter control logic Diagram
- 63. Timer Mode-0: In this mode, the timer is used as a 13-bit UP counter as follows. Timer modes of operation Fig: Operation of Timer in Mode 2 The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count. Upper 3 bits of TLX are ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is generated. The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the counter is controlled by input. This mode is useful to measure the width of a given pulse fed to input.
- 64. This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit mode. Timer Mode-1: Fig: Operation of Timer in Mode 1 Timer Mode-2: (Auto-Reload Mode) This is a 8 bit counter/timer operation. Counting is performed in TLX while THX stores a constant value. In this mode when the timer overflows i.e. TLX becomes FFH, it is fed with the value stored in THX. For example if we load THX with 50H then the timer in mode 2 will count from 50H to FFH. After that 50H is again reloaded. This mode is useful in applications like fixed time sampling
- 65. Fig: Operation of Timer in Mode 2 Timer Mode-3: Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0. Timer0 in mode-3 establishes TL0 and TH0 as two separate counters. Fig: Operation of Timer in Mode 3 Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0 are available to Timer-0 lower 8 bits(TL0).
- 66. Timer control (TCON) Special function register: TCON is bit addressable. The address of TCON is 88H. It is partly related to Timer and partly to interrupt. The various bits of TCON are as follows. TF1 : Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is cleared when processor vectors to execute ISR located at address 001BH. TR1 : Timer1 run control bit. Set to 1 to start the timer / counter. TF0 : Timer0 overflow flag. (Similar to TF1) TR0 : Timer0 run control bit.
- 67. IE1 : Interrupt1 edge flag. Set by hardware when an external interrupt edge is detected. It is cleared when interrupt is processed. IE0 : Interrupt0 edge flag. (Similar to IE1) IT1 : Interrupt1 type control bit. Set/ cleared by software to specify falling edge / low level triggered external interrupt. IT0 : Interrupt0 type control bit. (Similar to IT1) As mentioned earlier, Timers can operate in four different modes. They are as follows
- 68. Timer Delay = Delay Value × Timer Clock Cycle Duration Delay Value = how many counts before register(s) roll over Timer Clock Cycle Duration = 6/oscillator frequency Delay Value = Maximum Register Count – Timer Reload Value Maximum Register Count = 65535 Timer Delay and Timer Reload Value
- 69. The serial port of 8051 is full duplex, i.e., it can transmit and receive simultaneously. The register SBUF is used to hold the data. The special function register SBUF is physically two registers. One is, write-only and is used to hold data to be transmitted out of the 8051 via TXD. The other is, read-only and holds the received data from external sources via RXD. Both mutually exclusive registers have the same address 099H. Serial communication
- 70. Serial Port Control Register (SCON) Register SCON controls serial data communication. Address: 098H (Bit addressable) Mode select bits SM2: multi processor communication bit REN: Receive enable bit TB8: Transmitted bit 8 (Normally we have 0-7 bits transmitted/received) RB8: Received bit 8 TI: Transmit interrupt flag RI: Receive interrupt flag
- 71. Power Mode control Register (PCON) Register PCON controls processor powerdown, sleep modes and serial data baud rate, only one bit of PCON is used with respect to serial communication. The seventh bit (b7) (SMOD) is used to generate the baud rate of serial communication. Figure: PCON Register SMOD: Serial baud rate modify bit GF1: General purpose user flag bit 1 GF0: General purpose user flag bit 0 PD: Power down bit IDL: Idle mode bit
- 72. Serial port in mode-0 • Baud rate = oscillating frequency / 12 Serial port in mode-1 Generating the baud rates
- 73. Serial port in mode-2 If smod = 1 then baud rate = 1/32 *oscillator frequency If smod = 0 then baud rate = 1/64 *oscillator frequency
- 75. Baud rates for SMOD=0 Machine cycle freq. = 12 MHz / 12 = 1 MHz and 1MHz / 32 = 28,800 Hz since SMOD = 0
- 76. Examples
- 77. A 10khz square wave with 50% duty cycle XTAL = 12MHz ORG 0 ;Reset entry point LJMP MAIN ;Jump above interrupt ORG 000BH ;Timer 0 interrupt vector T0ISR:CPL P1.0 ;Toggle port bit RETI ;Return from ISR to Main program ORG 0030H ;Main Program entry point MAIN:MOV TMOD,#02H ;Timer 0, mode 2 MOV TH0,#50 ;50 us delay SETB TR0 ;Start timer MOV IE,#82H ;Enable timer 0 interrupt SJMP main ;Do nothing just wait END Programming Timer interrupts
- 78. Example Show the instructions to (a) enable the serial interrupt, Timer 0 interrupt, and external hardware interrupt 1 (EX1), and (b) disable (mask) the Timer 0 interrupt, then (c) show how to disable all the interrupts with a single instruction. a) MOV IE, #10010110B b) CLR IE.1 c) CLE IE.7
- 79. Write a program using interrupts to simultaneously create 7 kHz and 500 Hz square waves on P1.7 and P1.6. XTAL = 12MHz Timer0 & Timer1 Interrupt Example 71s 143s 1ms 2ms P1.7 P1.6 8051
- 80. 71s 143s 1ms 2ms P1.7 P1.6 8051 Solution ORG 0 LJMP MAIN ORG 000BH LJMP T0ISR ORG 001BH LJMP T1ISR ORG 0030H MAIN: MOV TMOD,#12H MOV IE,#8AH MOV TH0,#-71 MOV TH1,#0fcH MOV TL1,#18H SETB TR1 SETB TR0 SJMP main T0ISR: CPL P1.7 RETI T1ISR: CLR TR1 MOV TH1,#0fcH MOV TL1,#18H SETB TR1 CPL P1.6 RETI END
- 81. Example Write a program that continuously gets 8-bit data from P0 and sends it to P1 while simultaneously creating a square wave of 200 ms period on pin P2.1. Use Timer 0 to create the square wave. Assume that XTAL = 11.0592 MHz. ORG 0000H LJMP MAIN //ISR FOR TIMER 0 TO GENERATE SQUARE WAVE ORG 000BH CPL P2.1 RETI //
- 82. //MAIN PROGRAM FOR INITIALIZATION ORG 0030H MAIN: MOV TMOD, #02H MOV P0, #0FFH MOV TH0, #-92 MOV IE, #82H SETB TR0 BACK: MOV A, P0 MOV P1, A SJMP BACK END CONTINUE….
- 83. External interrupts INT0 and INT1 PROGRAMMING EXTERNAL HARDWARE INTERRUPTS
- 84. RI and TI flags and interrupts – 1 interrupt is set for serial communication – used to both send and receive data – when RI or TI is raised the 8051 gets interrupted and jumps to memory address location 0023H to execute the ISR – the ISR must examine the TI and RI flags to see which one caused the interrupt and respond accordingly Programming the serial communication interrupt