8086-microprocessor
- 1. 8086 MICROPROCESSOR INTERFACING Dr.P.Yogesh, Senior Lecturer, DCSE, CEG Campus, Anna University, Chennai-25.
- 2. 8086 based Microcomputer System An 8086-based microcomputer system has the following components 8086 CPU ROM RAM Peripherals Control bus Address bus
- 3. 8086 based Microcomputer System Data bus Clock generator Interrupt Controller DMA Controller Latches Transceivers
- 5. Buses The basic control bus consists of the signals labeled M/IO (Active Low), RD (Active Low) and WR (Active Low) The other two buses of 8086 are address bus and data bus These two buses are represented as ADDR/DATA The logic behind this is to save number of pins The lower 16 bits of addresses are multiplexed on the data bus
- 6. Buses External latches such as the 74LS373 octal devices are used to grab the lower 16 bits of the address placed in this address and hold it during the rest of the operation To strobe these latches at the proper time, 8086 outputs a signal called Address Latch Enable or ALE Once the address is stored on the outputs of the latches, the 8086 removes the address from the address/data bus and uses the bus for reading or writing data
- 7. Buses 8286 transceiver is used by most of the devices such as ROMs, RAMs and ports Clock generator uses a crystal to produce the stable-frequency clock signal which steps the 8086 through execution of its instructions in an orderly manner
- 8. Operating Modes There are two modes of operation for Intel 8086 namely the minimum mode and the maximum mode When only one 8086 CPU is to be used in a micro computer system the 8086 is used in the minimum mode of operation In this mode the CPU issues the control signals required by memory and I/O devices In a multi processor system it operates in the maximum mode
- 9. Maximum Mode and Minimum Mode In case of maximum mode of operation control signals are issued by Intel 8288 bus controller which is used with 8086 for this purpose The level of the pin MN/MX (active low) decides the operating mode of 8086 When MN/MX (active low) is high the CPU operates in a minimum mode
- 10. Maximum Mode and Minimum Mode When it is low the CPU operates in the maximum mode. From pin 24 to 31 issue two different sets of signals One set of signals is issued when the CPU is operating in the minimum mode The other sort of signal is issued when the CPU is operating in the maximum mode
- 11. Minimum Mode
- 12. Minimum Mode INTA (active low)(output)Pin No 24. Interrupt Acknowledge. On receiving interrupt signal the processor issues an interrupt acknowledge signal. ALE (output) Pin No 25. Address Latch Enable. It goes high during T1. The microprocessor sends the signal to latch the address in to the Intel 8282/8283 latch.
- 13. Minimum Mode DEN (output) Pin No 26. Data Enable. When Intel 8286/8287 octal bus transceiver is used, this signal acts as an output enable signal. It is active low. DT/R (active low)(output) Pin No 27. Data Transmit/Receive. When Intel 8286/8287 octal bus transceiver is used, this signal controls the direction of data flow through the transceiver. When it is high data are sent out. When it is low data are received.
- 14. Minimum Mode N/IO (active low)(output) Pin No 28. Memory or I/O access. When it is high the CPU wants to access memory. When it is low, the CPU wants to access IO device. WR (active low)(output) Pin No 29. Write. When it is low the CPU performs memory or I/O write operation. HLDA (output) Pin No 30. Hold Acknowledge. It is used by the processor when it receives hold signal. When hold request is removed, HLDA goes low. HOLD (input) Pin No 31. Hold. When another device in the complex microcomputer system wants to use the address and the data bus, it sends a hold request through this pin.
- 15. Minimum Mode
- 17. Maximum Mode
- 18. Maximum Mode – Instruction Queue Status QS1 QS0 Meaning 0 0 Nooperation 0 1 1st byteofopcodefromqueue 1 0 Emptythequeue 1 1 Subsequentbytefromqueue
- 19. Maximum Mode – Status Signals S2(AL) S1(AL) S0(AL) Meaning 0 0 0 Interruptacknowledge 0 0 1 ReaddatafromI/Oport 0 1 0 WritedataintoI/Oport 0 1 1 Halt 1 0 0 Opcodefetch 1 0 1 Memoryreading 1 1 0 Memorywriting 1 1 1 Passivestate
- 20. S2 S1 S0 BusCycleType 0 0 1 Read I/O – Initiated by the Execution Unit or the Refresher Control Unit. A19:16 are driven tozero 1 0 0 InstitutionPrefetch–InitiatedbytheBIU.Data readfromthebusfillstheprefetchqueue 1 0 1 ReadMemory–InitiatedbytheExecutionUnit or theRefresher Control Unit. A19-0 select the desiredbyteorwordmemorylocation
- 21. S2 S1 S0 BusCycleType 0 1 0 Write I/O – Initiated by executing IN, OUT, INS, OUTS instructions. A15:0 select the desiredI/Oport.A19:16aredriventozero 1 1 0 Write Memory – Initiated by any one of the Byte/Word memoryinstructions. A19:0 selects thedesiredbyteorwordmemorylocation
- 22. Bus Cycles Instruction Cycle The time taken to fetch and execute an entire instruction is referred to as an instruction cycle An instruction cycle consists of one or more machine cycles
- 23. Bus Cycles Machine Cycle The basic operation of reading/writing a byte from/to a memory location/a port is called a machine cycle The time taken to complete a machine cycle is represented as Tcy A machine cycle is made up of many T states
- 24. Types of Read Cycles S2 S1 S0 BusCycleType 0 0 1 Read I/O – Initiated by the Execution Unit or the Refresher Control Unit. A19:16 are driven tozero 1 0 0 InstitutionPrefetch–InitiatedbytheBIU.Data readfromthebusfillstheprefetchqueue 1 0 1 ReadMemory–InitiatedbytheExecutionUnit ortheRefresherControl Unit. A19-0 selectthe desiredbyteorwordmemorylocation
- 25. Types of Write Cycles S2 S1 S0 BusCycleType 0 1 0 Write I/O – Initiated by executing IN, OUT, INS, OUTS instructions. A15:0 select the desiredI/Oport.A19:16aredriventozero 1 1 0 Write Memory – Initiated by any one of the Byte/Word memoryinstructions. A19:0 selects thedesiredbyteorwordmemorylocation
- 26. One Bus Cycle T1 T2 T3 T4 CLK Address Out In DataAD0-AD15 Out Address Status AD16-AD19 S3-S6 MN/MX M/IO ALE BHE/S7 RD DT/R DEN BHE S7 READ BUS CYCLE
- 27. Read Bus Cycle The 4 processor clock cycles are called T states. Four cycles is the shortest time that the processor can use for carrying out a read or an input cycle. At the beginning of T1, the processor outputs S2, S1, S0, A16/S3…A19/S6, AD0..AD15 and BHE#/S7. The 8288 bus controller transitions the ALE signal from low to high, thereby allowing the address to pass through the transparent latches (74HC373).
- 28. Read Bus Cycle The address, along with the BHE# signal is latched when ALE goes low, providing the latched address A0..A19. During T2 the processor removes the address and data. S3..S6 status is output on the upper 4 address/status lines of the processor. The AD0..AD15 signals are floated as inputs, waiting for data to be read.
- 29. Read Bus Cycle Data bus transceivers (74HC245) are enabled towards the microprocessor (the READ direction) by the DT/R# and DEN signals. The MRDC# (ie MEMR#) or IORC# (IOR#) signal is asserted. The signals are maintained during T3. At the end of T3 the microprocessor samples the input data. During T4 the memory and I/O control lines are de- asserted.
- 30. Write Bus Cycle
- 31. Write Bus Cycle The 4 processor clock cycles are called T states. Four cycles is the shortest time that the processor can use for carrying out a write or an output cycle. At the beginning of T1, the processor outputs S2, S1, S0, A16/S3…A19/S6, AD0..AD15 and BHE#/S7. The 8288 bus controller transitions the ALE signal from low to high, thereby allowing the address to pass through the transparent latches (74HC373). The address, along with the BHE# signal is latched when ALE goes low, providing the latched address A0..A19.
- 32. Write Bus Cycle During T2 the processor removes the address and data. S3..S6 status is output on the upper 4 address/status lines of the processor. Output data is driven out on the AD0..AD15 lines. Data bus transceivers (74HC245) are enabled away from the microprocessor (the WRITE direction) by the DT/R# and DEN signals. The MWRC# (ie MEMW#) or IOWC# (IOW#) signal is asserted at the beginning of T3.
- 33. Write Bus Cycle The signals are maintained during T3. During T4 the memory and I/O control lines are de-asserted. In simple Intel Architecture systems, the data is usually written to the memory or output device at the rising edge of the MWRC# or IOWC# signal.
- 37. 16-bit Data Bus Byte Transfers
- 38. 16-bit Data Bus Byte transfers
- 39. 16-Bit Data Bus Even Word Transfers
- 40. 16-Bit data Bus Odd Word Transfers